New Cortex-M7 Chip to Help Power Sophisticated IoT Solutions

New Cortex-M7 Chip to Help Power Sophisticated IoT Solutions
by Tom Simon on 11-01-2016 at 4:00 pm

IoT architects face a dilemma in partitioning the compute power of their systems between the cloud and the edge. The cloud offers large storage and heavy duty compute power, making it an attractive place to perform the computation needed for IoT tasks. However, moving large amounts of data from the edge to the cloud servers, can … Read More


Webinar on Revolutionary Changes in SOC IP Access

Webinar on Revolutionary Changes in SOC IP Access
by Tom Simon on 10-22-2016 at 7:00 am

Knowledge is power, and I’ve seen the trend over time of people getting more and deeper access to knowledge as each year goes by. I remember, as a student in high school back the in 70’s, the first time I wanted to buy stock in a company. You could only get a quote by calling a broker or visiting the broker’s office. Today you can get real … Read More


Webinar Offers View into TSMC IP Design Methodology

Webinar Offers View into TSMC IP Design Methodology
by Tom Simon on 10-21-2016 at 12:00 pm

Standard cell and memory IP are key enablers for new process node availability. These two items must be in place early and be completely ready for a process node to scale to volume. Development of both leaves no room for error and they require the highest performance possible. Foundries are extremely focused on this and spend a lot… Read More


SOC Design Techniques that Enable Autonomous Vehicles

SOC Design Techniques that Enable Autonomous Vehicles
by Tom Simon on 10-11-2016 at 4:00 pm

Robots – we have all been waiting for them since we were young. We watched Star Wars, or in the case of the slightly longer-lived of us, we watched Forbidden Planet or Lost in Space. We knew that our future robot friends would be able to move around and interact with their environment. What we did not foresee long ago was that instead of… Read More


Processors, Processors, Processors Everywhere

Processors, Processors, Processors Everywhere
by Tom Simon on 10-06-2016 at 7:00 am

At first glance a processor conference might seem a bit arcane, however we live in an era where processors are ubiquitous. There is hardly any aspect of our lives that they do not touch in some way. Last week at the Linley Processor Conference the topics included deep learning, autonomous driving, energy, manufacturing, smart cities,… Read More


16nm HBM Implementation Presentation Highlights CoWoS During TSMC’s OIP

16nm HBM Implementation Presentation Highlights CoWoS During TSMC’s OIP
by Tom Simon on 09-29-2016 at 12:00 pm

Once a year, during the TSMC’s Open Innovation Platform (OIP) Forum you can expect to see cutting edge technical achievements by TSMC and their partners. This year was no exception, with Open-Silicon presenting its accomplishments in implementing an HBM reference design in 16nm. It’s well understood that HBM offers huge benefits… Read More


Solutions for Variation Analysis at 16nm and Beyond

Solutions for Variation Analysis at 16nm and Beyond
by Tom Simon on 09-22-2016 at 7:00 am

Variation is still the tough nut to crack for advanced process nodes. The familiar refrain of lower operating voltages and higher performance requirements make process variation an extremely important design consideration. As far back as the early 2000’s design teams have been looking for a better approach to model variation… Read More


TSMC and Solido to Share Experiences with Managing Variation in Webinar

TSMC and Solido to Share Experiences with Managing Variation in Webinar
by Tom Simon on 09-10-2016 at 7:00 am

TSMC knows better than anyone the effect that variation can have at advanced process nodes. Particularly in memory designs and in standard cell designs, variation has become a very critical because of its effects on yield and because of the high-cost of compensating for it. Smaller feature sizes combined with lower voltage thresholds… Read More


Statistical Simulation Provides Insight into 6T SRAM Optimization

Statistical Simulation Provides Insight into 6T SRAM Optimization
by Tom Simon on 08-24-2016 at 12:00 pm

ARM’s Azeez Bhavnagarwala recently gave a talk hosted by Solido on the benefits of variation aware design in optimizing 6T bit cells. Azeez sees higher clock rates, increasing usage of SRAM per processor and the escalating number of processors, shown in the diagram below, as trends that push designers toward 6T. Six Transistor… Read More


Solido Saves Silicon with Six Sigma Simulation

Solido Saves Silicon with Six Sigma Simulation
by Tom Simon on 08-16-2016 at 4:00 pm

When pushing the boundaries of power and performance in leading edge memory designs, yield is always an issue. The only way to ensure that memory chips will yield is through aggressive simulation, especially at process corners to predict the effects of variation. In a recent video posted on the Solido website, John Barth of Invecas… Read More