At the recent TSMC Technology Symposium, TSMC provided a detailed discussion of their development roadmaps. Previous articles have reviewed the highlights of silicon process and packaging technologies. The automotive platform received considerable emphasis at the Symposium – this article specifically focuses on the… Read More
Author: Tom Dillinger
Highlights of the TSMC Technology Symposium 2021 – Automotive
Highlights of the TSMC Technology Symposium 2021 – Packaging
The recent TSMC Technology Symposium provided several announcements relative to their advanced packaging offerings.
General
3DFabricTM
Last year, TSMC merged their 2.5D and 3D package offerings into a single, encompassing brand – 3DFabric.
2.5D package technology – CoWoS
The 2.5D packaging options are divided into the CoWoS… Read More
Highlights of the TSMC Technology Symposium 2021 – Silicon Technology
Recently, TSMC held their annual Technology Symposium, providing an update on the silicon process technology and packaging roadmap. This article will review the highlights of the silicon process developments and future release plans.
Subsequent articles will describe the packaging offerings and delve into technology … Read More
Machine Learning Applied to Increase Fab Yield
Machine learning applications have become pervasive and increasingly complex, from recommendation agents in online interactions to personal assistants for command response to (ultimately) autonomous vehicle control. Yet, an often overlooked facet of machine learning technology is the deployment in industrial process… Read More
Extending Moore’s Law with 3D Heterogeneous Materials Integration
A great deal has been written of late about the demise of Moore’s Law. The increase in field-effect transistor density with successive process nodes has slowed from the 2X every 2 1/2 years pace of earlier generations. The economic nature of Moore’s comments 50 years ago has also been scrutinized – the reduction in cost per transistor… Read More
Intel’s EMIB Packaging Technology – A Deep Dive
The evolution of low-cost heterogeneous multi-chip packaging (MCP) has led to significant system-level product innovations. Three classes of MCP offerings have emerged:
- wafer-level fan-out redistribution, using reconstituted wafer substrates of molding compound as the surface for interconnections between die (2D)
Adaptive Power/Performance Management for FD-SOI
A vexing chip design issue is how to achieve (or improve) performance and power dissipation targets, allowing for a wide range of manufacturing process variation (P) and dynamic operation voltage and temperature fluctuations (VT). One design method is to analyze the operation across a set of PVT corners, and ensure sufficient… Read More
Webinar: Rapid Exploration of Advanced Materials (for Ferroelectric Memory)
There are many unsung heroes in our industry – companies that provide unique services and expertise that enable the rapid advances in fabrication process development that we’ve come to rely upon. Some of these companies offer “back-end” services, assisting semiconductor fabs with yield diagnostic engineering and failure… Read More
Resistive RAM (ReRAM) Computing-in-Memory IP Macro for Machine Learning
The term von Neumann bottleneck is used to denote the issue with the efficiency of the architecture that separates computational resources from data memory. The transfer of data from memory to the CPU contributes substantially to the latency, and dissipates a significant percentage of the overall energy associated with … Read More
Electromagnetic and Circuit RLCK Extraction and Simulation for Advanced Silicon, Interposers and Package Designs
For years, there have been rather distinct domains for the extraction of interconnect models from physical design data.
Chip designers commonly focused on RC parasitics for circuit/path delay calculations and dynamic I*R voltage drop analysis. The annotation of extracted parasitics to a netlist model required the layout… Read More
Intel High NA Adoption