Integrated wafer-level fanout (WLFO) packaging technology is emerging as a foundation for multi-die solutions. Mobile product applications require focus on both aggressive chip-to-chip interface performance, as well as the final package volume. Traditional multi-chip packages using PCB laminate substrates do not readily… Read More
Author: Tom Dillinger
The Package Assembly Design Kit (PADK)… the start of something big
Rigid-Flex Cabling is Cool! (and requires unique EDA support)
The three F’s of electronic product development are: form, fit, and function. Although the F/F/F assessment typically refers to the selection of the right component, it most definitely also refers to the selection of the proper cabling between assemblies. The requirements for cables are varied, and demanding: ability… Read More
Custom layout productivity requires unrelenting EDA vendor focus
The EDA tools industry relies upon ongoing productivity enhancements to existing products, to manage increasing SoC complexity and to address shrinking design schedules. The source of ideas for enhancements can come from a variety of sources – e.g., customer feedback, collaboration with the foundries, and features found … Read More
Foundry Technology Packaging Solutions
A significant shift is underway in the fabless semiconductor business model. As the application markets have become more diverse (and more cost-sensitive), product requirements have necessitated a new focus on multi-die packaging technology. … Read More
Mainstream PCB Design Requires a Complete Tool Platform, Too
The EDA tool offerings for printed circuit board design commonly address one of three customer markets: (1) the enterprise design team, (2) the product development engineer, and (3) the “maker”. … Read More
STT-MRAM – Coming soon to an SoC near you
An increasing percentage of SoC die area is being allocated to memory arrays, as applications require more data/instruction storage and boot firmware. Indeed, foundries invest considerable R&D resources into optimizing their array technology IP offerings, often with more aggressive device features than used for other… Read More
High Level Synthesis Update
High-level synthesis (HLS) involves the generation of an RTL hardware model from a C/C++/SystemC description. The C code is typically referred to as abehavioraloralgorithmicmodel. The C language constructs and semantics available to architects enable efficient and concise coding – the code itself is smaller, easier to write/read,… Read More
It’s Time to Put Your Spice Netlists on a Diet
Spice circuit simulation remains the backbone of IC design validation. Digital cell library developers rely upon Spice for circuit characterization, to provide the data for Liberty models. Memory IP designers utilize additional Spice features to perform statistical sampling. Analog and I/O interface designers extend these… Read More
Is the U.S. ready to adopt a new financial model to support microelectronics?
Amidst all the active news about new process introductions at 16/14/10/7nm and the status of next-generation lithography development, there was a recent press release that could have as large an impact upon the microelectronics industry in the United States. A groundbreaking ceremony was recently held in Marcy, New York for… Read More
Top Ten #53DAC Highlights
Here is a very subjective list of the Top 10 logistical and technical highlights from DAC’53.
(10) With DAC attendance down from its peak days, the Austin Convention Center served as an excellent venue. There was good participation from companies with design centers in the “Silicon Hills”. And, I saw colleagues from Silicon Valley,… Read More
Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity