A significant shift is underway in the fabless semiconductor business model. As the application markets have become more diverse (and more cost-sensitive), product requirements have necessitated a new focus on multi-die packaging technology.
The optimum solution to meet cost, schedule, and performance constraints may result in a mix of silicon technologies integrated on a system-in-package (SiP). The traditional goal to implement a new product as a single die, with all functionality scaled to the latest process node may no longer be the right choice.
The development and qualification of existing IP macros in a new process requires considerable financial and engineering resources. For consumer/mobile markets, that investment in scaling IP may have an adverse impact on cost and schedule, if performance (and power) targets can be met with existing offerings. For systems products pushing performance, multi-die packaging technology enables an aggressive path between processor and memory – e.g., the recent introduction of vertically-stacked array die in High-Bandwidth Memory, or HBM.
In short, emerging 2.5D multi-die package technologies are enabling:
(1) a mixed silicon technology selectionCost and schedule constraints may dictate an assemblage of IP from multiple process nodes.
(2) performance gainsTypical die-package-board-package-die interface delays are reduced.
(3) a suitable power dissipation tradeoffAlthough not an integrated design, the local interconnect loading between die on package redistribution layers (RDL) is reduced over discrete packages, saving I/O power dissipation.
The emergence of 2.5D packaging is not new – so, what is the significant market shift? The foundries are responding to this trend by directly offering customers a single solution, providing both silicon fabrication and advanced packaging technology.
The traditional business model has been for customers to work with both a foundry and an outsourced assembly and test (OSAT) provider, to ship the packaged product. The OSAT offers a full suite of back-end services, typically starting with bumping to final package test (and potentially electrical/thermal characterization, qualification, and failure analysis).
For a 2.5D package, however, the utilization of silicon as an intermediate interposer, combined with the aggressive lithographic line width/space requirements for the redistribution metal layers, employ manufacturing technologies very familiar to the foundries. (Note that an integral feature of many 2.5D packages utilize backside grinding or thinning of the interposer wafer and assembled die, a technological expertise that typically resides with both the foundry and the OSAT.) Perhaps most significantly, customers may accrue logistical and cost benefits from working with a single supplier for a new silicon/package solution.
An indication of this shift in solutions provider strategy came from the recent DAC presentation from the Samsung Foundry division of Samsung Semiconductor. Samsung released their advanced packaging technology roadmap available to foundry customers. Samsung has the unique benefit of being both a foundry supplier and a large, vertical Integrated Device Manufacturer (IDM), to help amortize the R&D investment in these new packaging technologies.
The figure below depicts the advanced package roadmap.
In addition to the silicon interposer-based 2.5D technologies in the High Density category, Samsung highlighted several unique Package-on-Package(PoP) offerings for mobile markets, focused on Thin and Small (and low-cost).
The goals for Samsung’s System-in-Packaged-PoP (SiPed-PoP) are depicted below. Here, the key opportunities are an overall cost reduction, as well as significant area savings due to component and package integration.
On the 2.5D packaging front, Samsung Foundry is looking at supporting an increase of the interposer size support from 25mm x 32mm to 50mm x 32mm, effectively doubling the maximum available (single-exposure) lithographic field. Also, note the planned evolution to a lower-cost organic-based interposer on the future roadmap.
The figure below highlights another unique PoP package offering.
Laser-drilled package (LDP) technology is applied to the bottom package of the PoP, offering (dense) connectivity through the bottom substrate, with interconnect vias through the bottom molding compound. A thermal interface material (TIM) layer enhances vertical heat transfer through the PoP stack.
As customers demand 2.5D package solutions to satisfy a broader range of requirements for cost, power, (memory interface) bandwidth, and (vertical and horizontal) footprint, a richer set of SiP-PoP technologies will need to be developed. The package roadmap from Samsung provides a glimpse into that R&D investment for the next few years.
And, customers will also be seeking solutions that will no doubt result in changes in the existing foundry + OSAT business model.
An excellent compendium of 2.5D technology information is available for free download at: www.esd-alliance.org , link for the Multi-Die IC User Guide.
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