I always enjoy welcoming new corporate members to the SemiWiki platform. Each company brings new technology, a different perspective and the opportunity for the SemiWiki community to hear about another aspect of chip design and manufacturing. But this introduction is different. This time, a new corporate member is opening … Read More
Author: Mike Gianfagna
Do You Love DAC? Here’s Why I Do
Hello all, and welcome to DAC Season. As you all probably know by now, there are some twists to DAC Season this year. First, it’s being held July 20 – 24 this year instead of in June. I believe there was one other time the conference spilled into July, so this isn’t the norm. DAC, like pretty much every other conference these days has also… Read More
PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support
A couple of months ago I introduced PLDA, a new member of the SemiWiki community, with a post about PLDA’s switch IP and its support for PCIe and NVMe solid state disks. Working in the area of high-performance data interconnects requires support for a growing list of standards, standards that continually evolve. The trick is to stay… Read More
A Thoughtful Semiconductor Outlook – Needed Now More Than Ever
If you’re not dizzy from all the changing market projections lately, you soon will be. At times like this, I believe it’s important to keep perspective and look beyond the next 24-hour news cycle to try and understand what the future holds. I’m happy to report there’s a great event coming up in June that will do just that.
The Silicon… Read More
SEMI Takes the Jim Hogan and Simon Butler Conversation Virtual
As I originally reported a few weeks ago, the Jim Hogan fireside chat with Methodic’s CEO and founder Simon Butler was moved to a virtual event on May 1. The event was produced by the Electronic System Design (ESD) Alliance, a SEMI Strategic Technology Community. Bob Smith, executive director of ESDA, moderated the event. I am happy… Read More
Cadence – Redefining EDA Through Computational Software
Based on what I’m seeing, I believe Cadence is looking at the world a bit differently these days. I first reported about their approach to machine learning for EDA in March, and then there was their white paper about Intelligent System Design in April. It’s now May, and Cadence is shaking things up again with a new white paper entitled… Read More
How to Modify, Release and Update IP in 30 Minutes or Less
I had the opportunity to attend a ClioSoft webinar recently on the topic of IP traceability. ClioSoft provides a broad range of tools for design data management and IP reuse. Entitled The New Trend in IP Traceability that IP Developers and Design Managers Rely On, the webinar was presented by Karim Khalfan, director of applications… Read More
Webinar: Build Your Next HBM2/2E Chip with SiFive
I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board. Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow… Read More
Slash Tapeout Times with Calibre in the Cloud
I’ve spent many years in the ASIC business, and I’ve seen my share of complex chip tapeouts. All of these projects share one important challenge – compute requirements explode when you get close to the finish line. Certain tools need to run on the full-chip layout for final verification and the run times for those tools can get excessively… Read More
Starting a Chip Company? Silicon Catalyst and Arm Are Ready to Help
Anyone who has started a company knows that landing the seed round of investment is just the beginning. There are many decisions to face. When to start building a sales team? What parts of the company’s infrastructure to outsource? How to price and promote your product? These are just a few of the questions to be answered. If your… Read More
Intel’s Path to Technological Leadership: Transforming Foundry Services and Embracing AI