The popular Linley Processor Conference kicked off its spring event at 9AM Pacific on Monday, April 6, 2020. The event began with a keynote from Linley Gwennap, principal analyst and president at The Linley Group. Linley’s presentation provided a great overview of the application of AI across several markets. Almost all of the… Read More
Author: Mike Gianfagna
Wally Rhines: Mentoring Generations of Semiconductor and EDA Professionals
I had the good fortune to catch a live webinar recently that was quite compelling – Conversation with Dr. Walden Rhines: Predicting Semiconductor Business Trends After Moore’s Law! Dr. Rhines, known to most as Wally, doesn’t need much of an introduction. Any semiconductor or EDA professional knows who he is and what he’s accomplished.… Read More
Synopsys is Changing the Game with Next Generation 64-Bit Embedded Processor IP
Synopsys issued a press release this morning that has some important news – Synopsys Introduces New 64-bit ARC Processor IP Delivering Up to 3x Performance Increase for High-End Embedded Applications. At first glance, one could assume this is just an announcement for some new additions to the popular ARC processor family. While… Read More
UPDATE: Everybody Loves a Winner
Building a successful startup is hard, very hard. Creating a new category along the way is even more difficult. Those that succeed at both endeavors are quite rare. This is why an upcoming ESD Alliance event is a must-see in my view. The event is entitled “Jim Hogan and Methodics’ Simon Butler on Bootstrapping a Startup to Profitability… Read More
Filling the ASIC Void – Part 2
I concluded my last post on the topic with an inventory of the key attributes needed to fill the ASIC void created by the relentless consolidation in semiconductors. There were five items, as follows:
- Design and manufacturing expertise in a market that requires custom chips
- Differentiating IP and the skills to integrate it into
Chip-to-Chip Communication for Enterprise and Cloud
I recently had the opportunity to attend a SemiWiki webinar entitled “Chip-to-Chip Communication for Enterprise and Cloud”. The webinar was presented by SiFive and explored chip-to-chip communication strategies for a variety of applications. In the first part of the webinar, Ketan Mehta, director of SoC IP product marketing… Read More
Filling the ASIC Void – Part 1
It started slowly at first. Then it began picking up steam. I’m referring to consolidation in the semiconductor sector. I had a front-row seat for what consolidation did to the ASIC part of semiconductor and that is the topic of this discussion. I was the VP of marketing at eSilicon, the company that invented the fabless ASIC model.… Read More
Security in I/O Interconnects
I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.
First, a bit about Richard. He is the technical… Read More
Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion
I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration… Read More
Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one… Read More
Micron- “The first cut isn’t the deepest”- Chops production & forecast further