Cadence Increases Verification Efficiency up to 5X with Xcelium ML

Cadence Increases Verification Efficiency up to 5X with Xcelium ML
by Mike Gianfagna on 08-13-2020 at 6:00 am

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SoC verification has always been an interesting topic for me. Having worked at companies like Zycad that offered hardware accelerators for logic and fault simulation, the concept of reducing the time needed to verify a complex SoC has occupied a lot of my thoughts. The bar we always tried to clear was actually simple to articulate… Read More


HCL Webinar Series – HCL VersionVault Delivers Version Control and More

HCL Webinar Series – HCL VersionVault Delivers Version Control and More
by Mike Gianfagna on 08-06-2020 at 10:00 am

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HCL is an interesting organization. You may know them as an Indian company that provides software and hardware services.  At about $10B US and over 110,000 employees working around the world, they are indeed a force in the industry. They’ve also created a software company called HCL Software that develops tools and technologies… Read More


How Samtec Puts the Customer First

How Samtec Puts the Customer First
by Mike Gianfagna on 08-05-2020 at 10:00 am

Samtec SnapEDA

An exceptional customer experience starts before the sale. Successful companies realize it never ends. Dedicated post-sales support and a robust ecosystem for aftermarket product extensions are ingredients that tend to delight the customer. These comments are relevant in the consumer sector, but they apply to high tech as… Read More


Cadence on Automotive Safety: Without Security, There is no Safety

Cadence on Automotive Safety: Without Security, There is no Safety
by Mike Gianfagna on 08-04-2020 at 10:00 am

Attack vectors and EDA countermeasures

One of the Designer Track at this year’s DAC focused on the popular topic of automotive electronics.  The title was particularly on-point, The Modern Automobile: A Safety and Security “Hot Zone”. The session was chaired by Debdeep Mukhopadhyay, a Professor at the Indian Institute of Technology in Kharagpur.

This special, invited… Read More


Synopsys Presents SAT-Sweeping Enhancements for Logic Synthesis

Synopsys Presents SAT-Sweeping Enhancements for Logic Synthesis
by Mike Gianfagna on 07-31-2020 at 10:00 am

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There was a “research reviewed” panel on Thursday at DAC entitled Shortening the Wires Between High-Level Synthesis and Logic Synthesis. Chaired by Alric Althoff of Tortuga Logic, the panel explored methods to deal with wire delays in high-level synthesis and logic synthesis. The four speakers and their focus were:

  • Licheng
Read More

DAC Panel: Cadence Weighs in on AI for EDA, What Applications, Where’s the Data?

DAC Panel: Cadence Weighs in on AI for EDA, What Applications, Where’s the Data?
by Mike Gianfagna on 07-29-2020 at 6:00 am

Drivers of Convergence in Computational Software

DAC was full of great panels, research papers and chip design stories this year, the same as other years. Being a virtual show, there were some differences of course. I’ve heard attendance was way up, allowing a lot more folks to experience the technical program.  This is likely to be true for a virtual event. I’m sure we’ll see more… Read More


Synopsys Webinar: A Comprehensive Overview of High-Speed Data Center Communications

Synopsys Webinar: A Comprehensive Overview of High-Speed Data Center Communications
by Mike Gianfagna on 07-27-2020 at 6:00 am

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High-speed communication is a critical component for many applications, most notably in the data center. The serializer/deserializer physical interface, or SerDes PHY is the backbone of many different forms of high-speed communication for this application. Use cases include on chip, between chips, between boards and racks… Read More


How yieldHUB Helps Bring a New Product to Market

How yieldHUB Helps Bring a New Product to Market
by Mike Gianfagna on 07-24-2020 at 10:00 am

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Collecting and analyzing semiconductor test data is a subject that holds a special place for me. Developing a factory data collection and analysis system was my first job out of school. The company was RCA, and the factories were in Findlay, Ohio (analog/mixed signal) and West Palm Beach, Florida (digital). There was a pilot… Read More


Alchip Delivers Cutting Edge Design Support for Supercomputer Processor

Alchip Delivers Cutting Edge Design Support for Supercomputer Processor
by Mike Gianfagna on 07-23-2020 at 6:00 am

MN 3 Supercomputer

Alchip issued a press announcement recently entitled Alchip Provides Supercomputer Processor Design Support. The release is literally a tour de force of technology, with many advanced design and packaging accomplishments. First, let’s examine the basics of the design.

Preferred Networks, Inc (PFN) is the customer. They … Read More


PLDA – Delivering Quality IP with a Solid Verification Process and an Extensive Ecosystem

PLDA – Delivering Quality IP with a Solid Verification Process and an Extensive Ecosystem
by Mike Gianfagna on 07-21-2020 at 10:00 am

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For those who design advanced and complex SoCs, the term “off-the-shelf IP” can be elusive. While this approach works for a wide range of IP titles, the pressure for maximum performance or minimum power can lead to custom-tailoring requirements for the IP.

PLDA has seen these requirements for the class of complex, high-performance… Read More