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Collecting and analyzing semiconductor test data is a subject that holds a special place for me. Developing a factory data collection and analysis system was my first job out of school. The company was RCA, and the factories were in Findlay, Ohio (analog/mixed signal) and West Palm Beach, Florida (digital). There was a pilot… Read More
Alchip issued a press announcement recently entitled Alchip Provides Supercomputer Processor Design Support. The release is literally a tour de force of technology, with many advanced design and packaging accomplishments. First, let’s examine the basics of the design.
Preferred Networks, Inc (PFN) is the customer. They … Read More
For those who design advanced and complex SoCs, the term “off-the-shelf IP” can be elusive. While this approach works for a wide range of IP titles, the pressure for maximum performance or minimum power can lead to custom-tailoring requirements for the IP.
PLDA has seen these requirements for the class of complex, high-performance… Read More
Semiconductor technology advances have a way of rewriting the rule book. As process geometries shrink, subtle effects graduate to mainstream problems. Performance curves can become inverted. And no matter what else occurs, low power demands are constantly reducing voltage and design margins along with it. Sometimes these… Read More
Most of us will remember the productivity boost that hierarchical analysis provided vs. analyzing a chip flat. This “divide and conquer” approach has worked well for all kinds of designs for many years. But, as technology advances tend to do, the bar is moving again. The new challenges are rooted in the iterative nature of high complexity… Read More
As chip complexity grows, so does the need for a well-thought-out design data management strategy. This is a hot area, and Cliosoft is in the middle of it. When I was at eSilicon, we used Cliosoft technology to manage the design and layout of high-performance analog designs across widely separated design teams. The tool worked… Read More
Ansys addresses complex Multiphysics simulation and analysis tasks, from device to chip to package and system. When I was at eSilicon we did a lot of work on 2.5D packaging and I can tell you tools from Ansys were a critical enabler to get the chip, package and system to all work correctly.
Ansys recently published an Application Brief… Read More
DAC is a complex event with many “moving parts”. While the conference has gone virtual this year (as all events have), the depth of the event remains the same. The technical program has always been of top quality, with peer-reviewed papers presented across many topics and across the world. This is also the oldest part of DAC, dating… Read More
As reported recently by Dan Nenni, Siemens has signed an agreement to acquire Cambridge, UK-based UltraSoC Technologies Ltd. We’ve all seen plenty of mergers and acquisitions in EDA. Some transactions perform better than others. The best ones enhance an existing product or service by blending non-overlapping technologies.… Read More
A few months ago, I wrote about the announcement of a new digital full flow from Cadence. In that piece, I focused on the machine learning (ML) aspects of the new tool. I had covered a discussion with Cadence’s Paul Cunningham a week before that explored ML in Cadence products, so it was timely to dive into a real-world example of the … Read More
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Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity