DAC is a complex event with many “moving parts”. While the conference has gone virtual this year (as all events have), the depth of the event remains the same. The technical program has always been of top quality, with peer-reviewed papers presented across many topics and across the world. This is also the oldest part of DAC, dating… Read More
Author: Mike Gianfagna
A Tour of This Year’s DAC IP Track with Randy Fish
Siemens Acquires UltraSoC to Drive Design for Silicon Lifecycle Management
As reported recently by Dan Nenni, Siemens has signed an agreement to acquire Cambridge, UK-based UltraSoC Technologies Ltd. We’ve all seen plenty of mergers and acquisitions in EDA. Some transactions perform better than others. The best ones enhance an existing product or service by blending non-overlapping technologies.… Read More
The Future of Chip Design with the Cadence iSpatial Flow
A few months ago, I wrote about the announcement of a new digital full flow from Cadence. In that piece, I focused on the machine learning (ML) aspects of the new tool. I had covered a discussion with Cadence’s Paul Cunningham a week before that explored ML in Cadence products, so it was timely to dive into a real-world example of the … Read More
How to Grow with Poise and Grace, a Tale of Scalability from ClioSoft
ClioSoft published a white paper recently entitled Best Practices are the Foundations of a Startup. The piece discusses the needs and challenges associated with building a scalable infrastructure to support growth.
Before I get into more details on ClioSoft’s white paper, I would offer my own experience on this topic – the need… Read More
Seeing is Believing, the Benefits of Delta’s Low-Resolution Vision Chip
Presto Engineering recently held a webinar discussing vision chip technology – what a vision chip is, what are the applications and how can you optimize its use. Samer Ismail, a design engineer at Presto Engineering with deep domain expertise in vision chip technology was the presenter. Samer takes you on a very informative … Read More
Cadence Adds “Always On” to vManager Verification Management with Distributed and Cloud Access
Cadence vManager™ Verification Management provides what the company describes as metric-driven signoff. Anyone who has been through the tapeout process for a complex SoC knows the perils of verification sign-off. How much of the chip has been verified? What’s left to do? Will all be ready when the tapeout deadline arrives? … Read More
Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
I had the opportunity to preview an upcoming webinar from Synopsys on SoC Glitch Power – what it is and how to reduce it. There is some eye-opening information in this webinar. Glitch power is a bigger problem than you may think and Synopsys has some excellent strategies to help reduce the problem. The webinar is available via replay… Read More
Synopsys Introduces Industry’s First Complete USB4 IP Solution
Synopsys announced an addition to its popular DesignWare IP portfolio recently that has some significant ramifications. The company announced the industry’s first complete USB4 IP solution. Before we get into the details of the announcement, let’s take a quick look at the USB standard and why it’s important.
Standards… Read More
Silicon Catalyst Announces a New Startup Ecosystem for MEMS Led by Industry Veteran Paul Pickering and supported by STMicroelectronics
A little over a month ago, I wrote about the substantial support that Silicon Catalyst and Arm were providing for chip startups. There have been many incubators for technology companies over the years. These organizations typically provide office space, some basic infrastructure, advisory help and sometimes access to seed … Read More
Moortec Delivers Distributed, Real-Time Thermal Sensing on TSMC N5 Process
Moortec is known for its innovative in-chip monitoring and sensing products. They’re based in the UK and have been delivering this kind of embedded technology since 2010. Dan Nenni covered an overview of the company recently. SemiWiki also hosted a webinar about optimizing power and increasing data throughput in AI from Moortec… Read More
LRCX- Mediocre, flattish, long, U shaped bottom- No recovery in sight yet-2025?