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Last year when I visited Tanner EDA at DAC I heard about how they integrated the Analog FastSPICE circuit simulator from Berkeley DA.
This made sense to me because BDA has a good reputation for speeding up SPICE without compromising on accuracy, and Tanner users may want to mix and match tools from multiple EDA vendors.
This year they’ve… Read More
In April I blogged about a webinar on co-simulation hosted by Aldec and Tanner EDA where they showed how the RTL simulator (Riviera PRO) and SPICE simulator (T-Spice) had been connected together for IC designers wanting to do real AMS simulations.
The availability date of the co-simulation wasn’t clear, so today the press… Read More
Yesterday I met with Michael Buehler-Garcia, Director of Marketing at Mentor Graphics for Calibre in Wilsonville, Oregon to get an update on what’s coming up at DAC, the premier conference and trade show for our industry.
… Read More
In June I’ll be visiting several first time companies at DAC in order to learn more about what they have to offer in terms of EDA software, then blog about what I discover.
Here’s my list:… Read More
Next month at DAC I plan to visit the ClioSoft booth to get an update on what’s new with hardware configuration management (HCM). Last year I met with Srinath Anantharaman to get an introduction to their company and how their tools are used by both front-end engineers and back-end IC layout designers.
Srinath Anantharaman,… Read More
Collaboration between EDA, Foundry and Design was the key idea today in a webinar hosted by IBM and Cadence about 20nm custom IC design. The three presenters were:
John Stabenow, Cadence
Jeremiah Cessna, Cadence
Keith Barkley, IBM… Read More
One year ago activist investor Carl Icahn started a hostile takeover bid for Mentor Graphics and was able to offer up three new board members, however yesterday we read that Mentor Graphics will:
- Have their annual shareholder meeting on May 30th
- Two of Icahn’s board members are not on the roster for renewal
- Mr. Icahn has no
…
Read More
While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.… Read More
It’s been 34 years since I graduated from the University of Minnesota with a degree in Electrical Engineering so I was curious about what has changed in quantum physics since then. Alastair Rae is the UK-based author who wrote the book – Quantum Physics: A Beginner’s Guide. I read this on my Kindle Touch e-book… Read More
IC device physics uncovers limits to reliable operation, so IC designers are learning to first identify and then fix reliability issues prior to tape-out. Here’ s a list of reliability issues to keep you awake at night:… Read More
Ncredible Nvidia