Analog FastSPICE added to Tanner EDA

Analog FastSPICE added to Tanner EDA
by Daniel Payne on 05-24-2012 at 10:18 am

Last year when I visited Tanner EDA at DAC I heard about how they integrated the Analog FastSPICE circuit simulator from Berkeley DA.

This made sense to me because BDA has a good reputation for speeding up SPICE without compromising on accuracy, and Tanner users may want to mix and match tools from multiple EDA vendors.

This year they’ve… Read More


Aldec and Tanner EDA at DAC

Aldec and Tanner EDA at DAC
by Daniel Payne on 05-18-2012 at 10:19 am

In April I blogged about a webinar on co-simulation hosted by Aldec and Tanner EDA where they showed how the RTL simulator (Riviera PRO) and SPICE simulator (T-Spice) had been connected together for IC designers wanting to do real AMS simulations.

The availability date of the co-simulation wasn’t clear, so today the pressRead More


Hardware Configuration Management at DAC 2012

Hardware Configuration Management at DAC 2012
by Daniel Payne on 05-11-2012 at 4:54 pm

Next month at DAC I plan to visit the ClioSoft booth to get an update on what’s new with hardware configuration management (HCM). Last year I met with Srinath Anantharaman to get an introduction to their company and how their tools are used by both front-end engineers and back-end IC layout designers.

Srinath Anantharaman,Read More


Carl Icahn Blinks in Bid for Mentor Graphics

Carl Icahn Blinks in Bid for Mentor Graphics
by Daniel Payne on 05-02-2012 at 3:42 pm

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One year ago activist investor Carl Icahn started a hostile takeover bid for Mentor Graphics and was able to offer up three new board members, however yesterday we read that Mentor Graphics will:

  • Have their annual shareholder meeting on May 30th
  • Two of Icahn’s board members are not on the roster for renewal
  • Mr. Icahn has no
Read More

IC design at 20nm with TSMC and Synopsys

IC design at 20nm with TSMC and Synopsys
by Daniel Payne on 05-02-2012 at 10:25 am

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While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.… Read More


Book Review – Quantum Physics: A Beginner’s Guide

Book Review – Quantum Physics: A Beginner’s Guide
by Daniel Payne on 04-30-2012 at 8:00 am

It’s been 34 years since I graduated from the University of Minnesota with a degree in Electrical Engineering so I was curious about what has changed in quantum physics since then. Alastair Rae is the UK-based author who wrote the book – Quantum Physics: A Beginner’s Guide. I read this on my Kindle Touch e-book… Read More


IC Reliability and Prevention During Design with EDA Tools

IC Reliability and Prevention During Design with EDA Tools
by Daniel Payne on 04-27-2012 at 5:04 pm

IC device physics uncovers limits to reliable operation, so IC designers are learning to first identify and then fix reliability issues prior to tape-out. Here’ s a list of reliability issues to keep you awake at night:… Read More