Design Automation and the Engineering Workstation

Design Automation and the Engineering Workstation
by Daniel Nenni on 09-28-2018 at 7:00 am

This is the seventeenth in the series of “20 Questions with Wally Rhines”

Several common aspects have existed for what is now the modern Electronic Design Automation (EDA) industry. When I joined TI in 1972, the company was very proud of its design automation capability as a competitive differentiator. Much of the… Read More


Custom SoC Platform Solutions for AI Applications at the TSMC OIP

Custom SoC Platform Solutions for AI Applications at the TSMC OIP
by Daniel Nenni on 09-27-2018 at 12:00 pm

The TSMC OIP event is next week and again it is packed with a wide range of technical presentations from TSMC, top semiconductor, EDA, and IP companies, plus long time TSMC partner and ASIC provider Open-Silicon, a SiFive Company. You can see the full agenda HERE.

AI is revolutionizing and transforming virtually every industry… Read More


Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where… Read More


Systems Design vs Integrated Circuit Design

Systems Design vs Integrated Circuit Design
by Daniel Nenni on 09-21-2018 at 7:00 am

This is the sixteenth in the series of “20 Questions with Wally Rhines”

Electronic design automation (EDA) began and grew with the integrated circuit (IC) design business probably because IC design grew in complexity faster than printed circuit boards. The race for superiority in PCB design evolved in parallel,… Read More


Semiconductor IP Reality Check

Semiconductor IP Reality Check
by Daniel Nenni on 09-19-2018 at 12:00 pm

A robust, proven library of IP is a critical enabler for the entire semiconductor ecosystem. Without it, ASIC design is pretty much impossible, given time-to-market pressures. Said another way, designing IP for your next chip simply doesn’t fit the schedule – most teams have barely enough time to integrate and validate pre-existing… Read More


UMC and GF or Samsung and GF?

UMC and GF or Samsung and GF?
by Daniel Nenni on 09-17-2018 at 7:00 am

One of the interesting rumors in Taiwan last week was the possibility that UMC and GF will do a deal to merge or UMC will buy some GF fabs. I have talked to quite a few industry experts about it and will talk to more this week at the GSA US Executive Forum (more at the end). The US Executive Forum is what they call a C Level event which means it… Read More


Mentor Rise and Fall

Mentor Rise and Fall
by Daniel Nenni on 09-14-2018 at 7:00 am

This is the fifteenth in the series of “20 Questions with Wally Rhines”

During 1980 and 1981, three companies, Daisy, Mentor and Valid were founded. Daisy and Valid attacked the computer automated design business with custom hardware workstations plus software to provide the unique capabilities required by engineers.… Read More


2018 Semiconductor Winners and Losers

2018 Semiconductor Winners and Losers
by Daniel Nenni on 09-12-2018 at 7:00 am

This is an ongoing conversation inside the semiconductor ecosystem, especially when I am traveling. Everyone wants to know what is going on here or there and since I just returned from Taiwan I will post my thoughts. Last week was also my birthday which was cut short due to the time change but I did get preferential treatment on the … Read More


Mentor Graphics Makes a Transition

Mentor Graphics Makes a Transition
by Daniel Nenni on 09-07-2018 at 12:00 pm

This is the fourteenth in the series of “20 Questions with Wally Rhines”

I joined Mentor Graphics (now Mentor, A Siemens Business), in late 1993. Tom Engibous, one of my direct reporting people at TI, was promoted to replace me as head of the Semiconductor business of TI and I moved on to what I knew would be a real challenge,… Read More


Turnkey 2.5D HBM2 Custom SoC SiP Solution for Deep Learning and Networking Applications

Turnkey 2.5D HBM2 Custom SoC SiP Solution for Deep Learning and Networking Applications
by Daniel Nenni on 09-07-2018 at 7:00 am

Before we jump into the specifics, let us understand what’s driving custom solutions in the high performance computing and networking space. It’s the growing demand for core capacity and greater performance, which is due to the increase in the level of parallelism and multitasking required to handle the enormous amount of data… Read More