As artificial intelligence systems become larger and more demanding, memory is becoming one of the most important constraints in server design. Modern AI workloads do not only require powerful GPUs and accelerators; they also require enormous amounts of data to move quickly and efficiently between memory and compute engines.… Read More
Author: Daniel Nenni
How SOCAMM2 Could Reshape Server Memory for AI
Executive Interview with James Huang of AlChip
I had a chance sit down with James Huang, Director of Engineering at Alchip Technologies, to discuss the company’s recent multi-die packaging achievements and learn about Alchip’s next steps in pushing the boundaries of innovation for next generation AI ASIC.
James is acknowledged as a leading light in advanced node ASICs, based… Read More
Synopsys Demonstrates Leadership in AI-Powered Engineering at 2026 DAC Chips to Systems Conference
Purple was in fashion at the 2026 Design Automation Conference, where Synopsys reinforced its position at the forefront of AI-powered engineering. Under the conference’s “Chips to Systems” theme, the company showcased intelligent, end-to-end technologies designed to help the semiconductor industry manage unprecedented… Read More
WAVE-J: Redefining High-Performance JPEG for the 8K Era
Chips&Media WAVE-J is a high-performance JPEG codec intellectual property core designed for advanced imaging systems that require very large image support, high throughput, flexible pixel formats, and integrated pre- and post-processing. It succeeds the CODAJ12V architecture while retaining compatibility with … Read More
CEO Interview with Joseph Krause of Radical AI
Joseph F. Krause is an American materials scientist, entrepreneur, and U.S. Army National Guard veteran. He is the cofounder and CEO of Radical AI, a New York deep-tech startup founded to accelerate the discovery of advanced materials.
Before Radical AI, Krause conducted nanomaterials research at Rice University, worked on… Read More
CEO Interview with Chuck McClish of Lattrex Inc.
Chuck McClish is the founder of Lattrex Inc., a fabless semiconductor startup building Kyttar, an asynchronous, clockless reconfigurable processor for real-time signal processing. He spent 15 years at Microchip Technology in chip design and verification, working across RTL design, UVM verification, synthesis, place-and-route,… Read More
The Difference Between TSMC CoWoS-S and CoWoS-R
CoWoS-S and CoWoS-R are two versions of TSMC’s Chip-on-Wafer-on-Substrate advanced packaging platform. Both technologies are designed to combine high-performance processors, chiplets and high-bandwidth memory, or HBM, within a single package. This shortens the electrical connections between computing and memory components,… Read More
Previewing FMS 2026: The Next Frontier of Enterprise Memory, CXL, and AI-Era Storage
For anyone tracking enterprise infrastructure, the storage landscape is moving at a breakneck pace. The explosive growth of generative AI, multi-million token context windows, and massive data-centric workloads have pushed traditional memory and storage architectures to their absolute limits.
This August, the industry… Read More
ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation
For ASIC design teams, the gap between RTL simulation and first silicon remains one of the most consequential stages of the development cycle. Simulation provides controllability and visibility, but it cannot always reproduce the software workloads, interface behavior, clock interactions, and sustained system activity… Read More
Interview with Simon Davidmann, AI + EDA Researcher and Former CEO of Imperas
Simon Davidmann is a renowned EDA industry pioneer and serial technology entrepreneur with more than 40 years of experience in simulation and verification. After Synopsys acquired Imperas, which he founded in 2005, he was Synopsys Vice President responsible for Processor Modeling and Simulation. He left Synopsys in 2025 and… Read More
ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance