Tom Jackson is a serial entrepreneur who founded multiple successful technology ventures with expertise in turning around struggling companies. Experienced in developing strategic partnerships across the technology sector. Skilled at translating complex technical innovations into compelling, value propositions for customers and investors.
Tell us about your company?
SoftChip is developing DRDCL, a novel logic structure that delivers dramatic effective-density gains and improves performance, power, area, and thermal efficiency. Dynamically Reconfigurable Differential Cascode Logic uses a common differential cascode evaluation tree and a patented Cross-Switch circuits to produce multiple useful outputs from one evaluation, and switching among functions and outputs, at nanosecond scale.
SoftChip was founded by semiconductor veterans with Intel and IBM heritage. CTO Jim Davis previously led IBM’s VLSI Silicon effort and is co- inventor of the foundational differential cascode logic. DRDCL builds on that history, but adds the patented Cross-Switch mechanism for dynamic output routing and function selection.
The differential cascode foundation is already powerful. DCVL/DCVS is inherently at least 2x speed and at least 2x lower dynamic power versus conventional CMOS logic. DRDCL layers on multiple outputs, nanosecond-scale reconfiguration, and much larger effective-density gains.
A common differential cascode tree evaluates the input space, while the Cross-Switch determines which function or output grouping is expressed. A key efficiency point is that a DRDCL tree has one active discharge path during evaluation, even when the Cross-Switch expresses multiple useful outputs per evaluation.
Another important benefit is in-logic state retention. Selected DRDCL nodes may retain local intermediate state long enough to reduce movement to separate register or SRAM structures in bounded datapaths, combining logic evaluation, output selection, reconfiguration, and temporary local state in the same compact circuit structure.
That separation of common evaluation from function and output selection is the core invention. As tree height increases, the structure supports dramatically more potential logic mappings using exponentially fewer transistors. Effective-density gain vs. fixed CMOS: 134x for 3-high, 1,200x for 4-high, and 5,200x for 5-high DRDCL trees. Simultaneous evaluation drives effective density, and effective density drives the PPA advantage.
Why does dynamic reconfiguration matter?
Dynamic reconfiguration is built into DRDCL. Cross-Switch control allows a common differential cascode tree to change its expressed function or output grouping at nanosecond scale without LUTs, configuration bitstreams, or FPGA-style routing fabric.
The value is effective density and utilization, not generic flexibility. The same physical transistor structure can express different related functions, output groupings, precision modes, or dataflow as AI models, sparsity patterns, memory hierarchies, and accelerator dataflows evolve.
What problems are you solving?
We target functions where fixed CMOS realization is costly: structured, reduction-heavy, output-rich, control-heavy, or dominated by intermediate movement. In AI, that appears in KV-cache movement, attention reduction, routing, scheduling, and accelerator-fabric utilization.
DRDCL attacks the problem at the circuit-structure level. Common differential trees and programmable output routing resolve more useful work per evaluation, which can translate into higher sustained tokens per watt in AI inference.
Our near-term path is characterized, latch-bounded DRDCL logic blocks with conventional digital interfaces that customers can evaluate against equivalent CMOS implementations and integrate into standard EDA and semiconductor design flows.
What application areas are your strongest?
Our first application is near-memory compute for AI inference, which we call Soft-NMC. Transformer decode repeatedly moves and reprocesses KV-cache data, consuming bandwidth, power, and thermal budget. Soft-NMC applies DRDCL-based logic near the memory interface to perform selected attention reduction and control work closer to where the data resides.
At the traffic level, our architecture model targets 60-80% reduction in repeated KV/attention movement in selected decode paths. At the system level, our model estimates approximately 12-13x local improvement at the memory-interface path and 3-4x sustained tokens/sec improvement in decode-dominated, KV-bound scenarios.
The advantage comes from simultaneous evaluation and reduced intermediate work. DRDCL can use common evaluation structures across tightly coupled reduction, gating, selection, and accumulation operations.
Beyond Soft-NMC, DRDCL is relevant wherever PPA limits useful throughput, especially in semiconductor blocks where fixed CMOS spends too much area, power, or switching to produce the required outputs.
What keeps your customers up at night?
PPA, bandwidth, and integration risk. Customers care about sustained useful throughput, not just peak TOPS or peak bandwidth. Real workloads stall on memory movement, routing congestion, intermediate state, power density, control overhead, and heat.
What does the competitive landscape look like and how do you differentiate?
Most approaches improve systems above the circuit level: architectures, memory packaging, compute-in-memory, sparsity, accelerators, EDA, or process nodes. DRDCL is different because it changes the underlying logic structure itself, adding Cross-Switch output selection, multiple outputs, in-logic state retention, and circuit-speed function reconfiguration to the differential cascode logic lineage.
DRDCL does not use lookup tables, multiplexer fabrics, or configuration bitstreams. It uses the intrinsic evaluation structure of differential cascode trees with programmable output routing, so reconfiguration happens at the circuit level in nanoseconds rather than through a separate configuration layer.
For our first logic-block family, our target is multi-x PPA improvement versus equivalent CMOS in selected paths: 2-5x useful throughput per area/power as a conservative first-silicon target, 5-10x effective PPA as a stronger product target, and 10x+ upside where multi-output evaluation, dynamic reconfiguration, lower switching, and local state retention are strong, pending silicon characterization.
What new features/technology are you working on?
We are working on three extensions of the same core DRDCL principle: using a dense, reconfigurable transistor structure to do more useful work.
The first is ARMOR, a resilience and remapping concept. The thesis is that DRDCL can cover broad regions of digital logic with a very small reconfigurable repair layer, targeting under 1% area overhead. In logic-rich fabrics such as accelerator tiles, routing/control logic, and compute datapaths, DRDCL can reassign, bypass, or replace selected digital logic functions at nanosecond scale to improve effective yield, reduce redundancy overhead, and extend useful silicon life.
The second is Soft-TTC, or Timing, Throughput, and Control. Scheduling, arbitration, routing, gating, priority, and control decisions are often structured, output-rich, and timing-sensitive, making them natural DRDCL candidates. Our initial target is 2-5x effective PPA improvement in selected timing, arbitration, routing, gating, and scheduling paths.
The third is in-logic state retention. Selected DRDCL nodes may hold intermediate state inside the logic structure, reducing movement of short-lived state to separate registers or SRAM. In Soft-NMC, we estimate 5-15% incremental efficiency inside the near-memory block by retaining temporary attention and reduction state locally. In Soft-TTC, we estimate 10-30% improvement in selected control paths where short-lived arbitration, routing, gating, and scheduling state stays close to the logic that uses it.
How do customers normally engage with your company?
SoftChip is an IP company, not a chip company. We aim to work with a small number of semiconductor, foundry, memory-interface, and AI hardware partners to validate DRDCL IP against CMOS baselines on real process paths. The expected model is NRE-funded logic-block evaluation leading to IP licensing.
A typical first engagement defines a bounded DRDCL logic block, an equivalent CMOS baseline, the characterization methodology, and target PPA metrics. From there we build, simulate, characterize, and potentially tape out a proof-of-concept block.
The adoption bridge is a latch-bounded logic block, characterized across PVT and delivered with conventional digital interfaces for standard EDA and physical design flows. Today, the foundation is analytical and circuit-level; the next milestone is a characterized silicon comparison against equivalent CMOS.
What should readers remember?
DRDCL changes the structure of digital logic itself. It is not a process-node, packaging, or architecture-only optimization. It is a circuit-level way to extract more useful work per area and per joule.
Our first application is AI memory-traffic reduction through Soft-NMC. We are also exploring ARMOR for resilience, remapping, effective yield, and longer useful silicon life. The broader thesis is the same: DRDCL increases effective logic density, substantially improve PPA.
SoftChip is not about making transistors smaller. It is about making them do more.
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