Cadence Integrates Power Integrity Analysis and Fix into Design

As integration levels increase, clock frequencies rise, and feature sizes shrink it is not surprising that all or most aspects of semiconductor design become more complex and demand more from design technologies. One example where the traditional approach is breaking down is in optimizing power distribution networks (PDNs) for electromigration and IR drop (EMIR). Historically designer have first run detailed EMIR analysis, then have implemented fixes to fold into the next design update, repeating periodically as implementation evolves. That method is no longer scaling effectively for very large designs at 7nm and below. To address this scaling problem Cadence has just announced a new AI-centric EMIR optimization tool supporting a combined analysis and fix in-design flow, following the path timing analysis took in earlier generations. They see this new approach to EMIR as an IR 2.0.

The problem statement

The trick in designing a PDN for a design is to ensure that metal routes are sufficiently low resistance, from the top level down through multiple metal layers to a gate that is switching. If resistance through that path is sufficiently high, that will result in a voltage drop below the nominal operating voltage causing the gate to switch more slowly than intended, therefore triggering unanticipated timing failures. Naturally other gates switching at the same time (aggressors) add to current demand in the same vicinity, further amplifying the voltage drop. In FinFET designs aggressors account for as much of the IR drop experienced by any given node. In effect, managing noise on the power network has become just like a signal integrity problem.

The IR 1.0 approach to the problem has been focused on analysis to find the hotspots, providing guidance to designers on what they need to fix. That has worked very well, but below 7nm resistance in the lower-level metal networks has become so significant that a victim in a block instance may have as many as 8-10k aggressors contributing up to 80% of the drop on the gate of immediate interest.

These compounded contributions complicate the analysis problem, but more important they create a deluge of IR drop violations (hundreds of thousands), making it impossible for a designer to fix any but a few of the most critical issues. Worse yet, in fixing one issue the designer has little insight into how an individual fix will impact timing for the other thousands of connected gates. The real goal should be to eliminate the great majority of violations without messing up PPA or DRC.

IR 2.0 with Voltus InsightAI

The only way to address the problem is to intelligently automate EMIR analysis/fixing together with PDN implementation, in the same we were forced to couple timing analysis and optimization with physically aware synthesis years ago. This is a perfect application for AI, not because a smart designer can’t figure out how to fix an individual IR drop problem or a problem coupled with a bit of surrounding complexity but because the sheer scale of coupled devices and interconnect has grown beyond human abilities to manage, no matter how skilled the engineer.

Voltus InsightAI uses a generative AI approach to develop and refine a power grid to minimize EMIR issues, maintain timing and power goals, while avoiding area overhead for an over-designed power grid. At the outset when reading in a design, the Learn capability creates AI models for the power grid, suitable for fast incremental IR drop analysis based on dynamic vector data. Discover runs root-cause analysis to prioritize large drops by finding aggressors and looks for resistance bottlenecks in the grid and power density hotspots.

Improve is a recommender technology which looks at many methods through which IR drop problems could be fixed and suggests optimal choices to address as many as violations as possible while honoring PPA and DRC constraints. The solution integrates through Empower with Innovus, Tempus, Voltus Power Integrity, and Pegasus in support of on-the-fly fix and check iterations.

In PDN design with Voltus InsightAI, designers use the tool first before signal routing. After signal routing has been inserted, they use the tool again to further refine optimization. Throughout the tool is self-training, updating after every few rounds of changes. No specialized pre-training is required.

All sounds good on paper; how does it deliver in practice? Several customers have been running trials, MediaTek among them. They have already provided an endorsement with hard numbers. They say they have seen a 65-70% reduction in IR drop violations at the block level, optimizing using both vectorless and vector-based flows. Not bad.

Very interesting stuff. You can learn more HERE.