RTL Design Engineer, PCIe-Related Protocols

Job Description/Responsibilities
The opening is for an RTL design engineer who is responsible for the design and integration of different SerDes subsystems that go into Achronix’s Speedster class of FPGAs, which includes PCIe Gen3/4/5, CXL/CCIX, etc. This employee will be responsible for subsystem-level IP RTL design and integration that meets high-quality RTL design standards, performance, power and frequency targets. This employee is expected to take independent ownership of complex design challenges.

The primary responsibilities include:

Micro-architecture development from a high-level PRD or specification
RTL code development
Timing constraints development with STA team
Support performance modeling
Post-Si bring-up support
FPGA-specific soft IP generation
The employee is also expected to participate regularly in interactions with global teams spanning system engineering, software and product engineering

Required Skills
Expertise with SerDes-related protocols and design, specifically PCIe Gen3/4/5
Expertise in CCIX or CXL is a plus
Experience in micro-architecture development
Strong RTL coding skills, with good working knowledge of Verilog and System Verilog
Hands-on experience of implementing multi-protocol PCS (PCIE/Ethernet/Interlaken) is a plus

Hands-on experience in integrating/validating system interconnect (AXI interconnect)
Experience with synthesis and STA constraint development and timing analysis
Experience with system-level performance modeling is a plus

Experience with post-Si bring-up and debug is a plus

Very good verbal and written communication skills

Ability to work in a dynamic and fast-paced environment, with a proactive mindset
Education and Experience

Preferred BS/MS + 6-12 years of experience in RTL design and verification

Previous experience with at least 2-3 product developments, including post-Si bring-up