PHY IP Software Development

PHY IP Software Development

The high speed SerDes 112 IP group at Cadence architects, designs, and validates wireline transceivers integrated into complex networking SoCs. The ideal candidate for this position will join a team of highly competent developers involved in the design, implementation and verification of mixed signal systems. The successful candidate will build and lead a team of software engineer and be responsible for the PHY API and firmware for multiple DSP-based and analog PHYs, while working closely with the architecture and design team.

Key qualifications:

5+ years of experience in real-time/embedded programming and firmware
Proficiency in multi-layered software architecture build for real time multi-threaded systems
Solid foundations in signals and systems, fundamental concepts, and communications systems
Working knowledge scripting languages (e.g. Perl, Python) a plus
Strong analytical skills – ability to triage a problem root cause in a complex system
Ability to work well in a multi-disciplinary team environment
Basic knowledge of hardware description language (i.e. Verilog)
Education MSEE preferable