Advantages when Designing with FD-SOI

In total we have blogged 41 times about FD-SOI on SemiWiki which has drawn an audience of 202,960 thus far. Of that traffic 31.68% came directly to SemiWiki (Newsletter), 30.13% came from search, 26.17% from social media (LinkedIn, FaceBook, Twitter, Google+, Reddit, etc…), and 11.99% came from other referring sites. The most interesting number here is “search” which means more than 60,000 visits were from people searching for FD-SOI related topics over the last two years. So, if there is a question in your mind as to when FD-SOI will come to the mainstream semiconductor market the answer is very soon, absolutely.

Speaking of FD-SOI, there is a workshop this week during the ISSCC conference in San Francisco sponsored by STMicroelectronics. The theme of ISSCC this year is SILICON SYSTEMS — SMALL CHIPS for BIG DATA which fits nicely with FD-SOI because big data will require small ULTRA POWER EFFICIENT chips.

Please notice that at 11:20am I will be moderating a panel on “Advantages and Opportunities when Designing with FD-SOI.” I’m working on questions for the panelists so please let me know in the comments section if you have any. Lunch will be offered to all the attendants. Registration is mandatory, free and open to everyone. I hope to see you there: SOI Consortium FD-SOI and RF-SOI Forum

Friday, February 27[SUP]th[/SUP], 2015 in San Francisco, USA

Leading companies are joining the SOI Industry Consortium to organize a forum covering planar FD-SOI as well as RF-SOI technologies. The full day workshop will be held in San Francisco (Palace Hotel) on Friday February 27[SUP]th[/SUP] 2015, the same week of ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys, VeriSilicon will present compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.

The day will be articulated as following:
[TABLE] style=”width: 100.0%”
|-
| style=”width: 47px” | 8.00am
| Registration
|-
| style=”width: 47px” | 8.30am
| Welcome Speech – SOI Consortium introduction
|-
| 8.40am
| FD-SOI Workshop – FD-SOI Foundry Offer

• FD-SOI advantages for applications and ecosystem (by Philippe Magarshack, STMicroelectronics)
• 28FD-SOI: Cost effective low power solution for long lived 28nm (by Kelvin Low, Samsung SSI)
• [Title TBA] (by Jamie Schaeffer, GlobalFoundries)

|-
| 9.40am
| FD-SOI Workshop – FD-SOI IP Offer

• Synopsys FD-SOI IP Solutions (by Mike McAweeney, Synopsys)
• FD-SOI: Ecosystem and IP Design (by Amir Bar-Niv, Cadence)

|-
| 10.20am
| Break
|-
| 10.35am
| FD-SOI Workshop – FD-SOI Design Experience

• [Title TBA] (by Naim Ben-Hamida, Ciena)
• 28nm FD-SOI Design/IP Infrastructure (by Shirley Jin, Verisilicon)

|-
| 11.20am
| FD-SOI Workshop – Panel Discussion

• Advantages and Opportunities when Designing with FD-SOI (Moderator: Dan Nenni, SemiWiki)

|-
| 12.30pm
| FD-SOI Workshop – Innovation

• Driving Profitable Innovation and Rapidly Growing Ecosystems with a Semiconductor Start-up Incubator (by Mike Noonen, Silicon Catalyst)

|-
| 12.50pm
| Morning Conclusion
|-
| 1.00pm
| Lunch
|-
| 2.30pm
| More than Moore Workshop

• RFSOI: Redefining mobility and more in the front-end (by Mark Ireland, IBM Systems & Technology Group)
• Towards a Highly-Integrated Front-End Module in RF-SOI using Electrical-Balance Duplexers (by Barend Van Liempd, IMEC / VUB)
• RF SOI: from Material to ICs – an Innovative Characterization Approach (by Mostafa Emam, Incize)
• ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration (by Laura Formenti, ST Microelectronics)

|-
| 4:30pm
| Afternoon Conclusions and coming events announcements
|-
| 5:00pm
| Social Event: Cheese & Wine
|-

Hotel location:
Palace Hotel
2 New Montgomery Street, San Francisco, California, 94105 (USA)

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