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WTL Leverage FDSOI to Achieve Both Low Power AND High Speed

WTL Leverage FDSOI to Achieve Both Low Power AND High Speed
by Eric Esteve on 10-07-2014 at 11:46 am

In fact, this is the title of a presentation given by Pete Foley during FD-SOI Forum 2014 held in Shanghai, a couple of weeks ago. What is nice with clever people like Pete Foley is that they get the point, and get it quickly. Getting the point is to insert AND in capital in the title, as using FD-SOI technology allows to benefit from low-power (thanks to the SOI technology) and performance, thanks to Forward Body Bias (FBB). I didn’t know who is Pete Foley and a quick look at Linkedin give me a hint: Pete’s DNA is innovation. In 1983 Pete was the “Third member of the original Apple VLSI team”, in 1987 he “Led the Newton hardware architecture development before it was redefined from a slate into a “PDA” form factor”… and so on. He is since 2009 the CEO of Waves Semiconductor, a “fabless semiconductor startup that is commercializing a programmable solution addressing power, concurrency, design time, design cost, and deep submicron challenges facing the semiconductor market.” This article is inspired from his presentation that you can find it here FD-SOI Forum 2014 along with other presentation from ST-Microelectronic, Synopsys, IBS and more.

Waves Semiconductor is developing real products based on Waves Threshold Logic (WTL). If we want to make it short, WTL is not based on standard Boolean logic, is asynchronous and “unifies Data and Control into a single “Logically Determined” paradigm. Simple words are not enough, that’s why the above picture should help! As you can see, there is no clock, no register, just DATA and NULL pipeline stages, and Acknowledge signals generated by the data. Alternating DATA/NULL provide data behavior, Pete Foley claim that WTL is “Data Driven Completion”. Asynchronous means that no clock is used, with several immediate consequences: no clock means no glitch (lower risk), no necessity to provision time for set-up and hold or for clock skew and budget for worst case PVT (better performance), and no need for register and CDM (40% real estate saving). Last but not least, much less dynamic power, as the pipeline only consumes power when the data change. So WTL is fast, fully standard CMOS compatible, but is also very low-power, especially when used on FD-SOI technology.

If you remember this blog in Semiwiki, a device designed on FD-SOI will offer better performance than the same design on Bulk Silicon (assuming the same node) if you use Forward Body Bias (FBB), or will exhibit much lower power consumption… but not at the same time. According with Pete Foley, WTL can use both types of transistor simultaneously to achieve speed of LVT devices under FBB but leakage of RVT devices under Reverse BB (RBB): the best of both worlds! You could argue that WTL is a nice but theoretical concept… In fact Waves Semi is designing products based on WTL like Azure pictured below:

If you are scared about WTL, and prefer to discuss about an existing SoC product initially designed on 32/28 LP Bulk and ported in FD-SOI 28nm, this example of an ARM Cortex A9 will be appropriate. You can find it in the presentation “The FD-SOI Technology for Energy Efficient SoCs” from Giorgio Cesana. The total power consumption, on the Y axis, is increasing with the CPU frequency (as expected), but the power clearly grow faster and get higher with the A9 on Bulk (in vertical blue) than the same design on FD-SOI (in vertical yellow). And you can see that using the FD-SOI Forward Body Bias effect helps further decreasing power consumption (in vertical green). If we try to quantify the gain in power, we have to look at the horizontal yellow and green horizontal curves. This gives a 50% lower power consumption for the A9 on FD-SOI FBB and 40% on FD-SOI, both compared with Bulk.

As a conclusion, just watch this slide (also from ST): “FD-SOI, Ecosystem available in the whole chain” extracted from this presentation. SOI wafers can be found at multiple sources, design solutions are enabled by EDA and IP vendors (or from IP porting) and the designed SoC can be fabed in production at ST facility and starting in 2015 at Samsung…

From Eric Esteve from IPNEST

More Articles by Eric Esteve…..

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