FD-SOI Better Than FinFET?

As I said earlier in the month, I was going to be talking about FD-SOI at the Electronic Design Process Symposium (EDPS) in Monterey. I am not especially an expert on FD-SOI but I know enough to be dangerous and given that we were already talking about FinFET and 3D/2.5D chips, it fitted in nicely.

The 10,000 foot view is that FD-SOI has some things for which it seems to be superior to FinFET. But ST Microelectronics is the only company that is committed to it (Global Foundries announced last year that they would be second sourcing it, but then they lost enthusiasm. And that was before the recent Samsung announcement). Wally Rhines dinner keynote pointed to the other problem that only having ST involved means that the learning will be slower for FD-SOI than FinFET and so even though it might have a cost and some other advantages, those could be overwhelmed by wafer volume. Despite Cooley’s snide remarks in his latest newsletter about this, I’ve talked about this before and I talked about it again at Monterey.

Much of what I used as base material for my talk came from ST’s various presentations on the technology over the last 6 months or so. But another key source was a recent report by Handel Jones of IBS that I talked about herecalled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel had put together cost models for both FinFETs and FD-SOI and came to the conclusion that FD-SOI is marginally cheaper than bulk planer (the more expensive starting material is offset by fewer processing steps). His analysis comparing FD-SOI to FinFET concludes that:At 14nm/16nm, the FD-SOI die cost for a 100mm[SUP]2[/SUP] die is 28.2% lower than the bulk FinFET die cost and has higher yield. The leakage of FD-SOI devices is projected to be comparable to that of FinFET devices.

I have said many times before that I think that people underestimate the economic end of Moore’s Law. Yes, transistors will be faster, and yes they will be lower power. But you will not get more transistors per dollar and this means that the strong economic driver that has driven the whole electronics industry, especially when looked at over decadal timescales, is at best weaking a lot and at worse going away. Never again will we hae another transformation like that one that made multimillion dollar flight simulators available in your pocket for a few hundred dollars reducing the cost by a factor of maybe 50,000 in the last 30 years. FD-SOI is clearly one opportunity to get that back on track at least for a couple more process generations. Carpe Diem, or Carpe Die in FD-SOI anyway.

Funnily enough, the week before I was at the GSA Silicon Symposium where on one panel people said they had seen these graphs and they were not true. Then after that I went to the Mentor user group meeting U2U and heard that the Samsung keynote had said that 20/14nm would not reduce costs, and later in the day I attended a TSMC presentation saying 16nm would not be a cost-reduction node. So I guess we will just have to wait and see. If FD-SOI designs really are nearly 30% cheaper than FinFET then that is a big gap to close by yield learning, it is approximately half a process node (and an old cost-reduction one at that).

More articles by Paul McLellan…