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Solido – Variation Analysis and Design Software for Custom ICs

Solido – Variation Analysis and Design Software for Custom ICs
by Daniel Payne on 08-15-2011 at 7:11 pm

Introduction
When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that’s what I used for my circuit simulations.
Today it’s not so intuitive what the worst case process corners are for each specific IC design, so you could just use brute force Monte-Carlo simulations to find them. This approach takes a massive amount of time, CPUs and SPICE licenses. There has to be a better way.

Variation Analysis at DAC
My DAC schedule got completely filled this year on Sunday thru Wednesday, so I didn’t get to hear from Solido about what’s new. As soon as DAC ended and I blogged my trip reports I soon heard from Solido, so we scheduled some time in July to review what they presented at DAC in San Diego.

I spoke by phone with Kris Breen, Director of Corporate AEs and he walked me through their DAC presentation and demo.

Also on the call was Amit Gupta, CEO of Solido.

DAC Presentation Title – Variation Analysis and Design Software for Custom ICs.

The Solido mission is to analyze variation impact, identify electrical hotspots, then fix specification failures. They’ve been in business since 2005 and are growing, always a good sign to look for.

Amit’s first EDA company was Analog Design Automation which grew for 5 years and was then sold to Synopsys, it was more of an optimization company.

Q: Who would benefit from using tools from Solido?
A: IC Designers that work on:

  • Analog (Transistor level)
  • IO
  • Memory
  • Std Cell

Q: At what process node did variation analysis become important?
A: We started seeing customers benefit from variation analysis at the 130nm node.

Q: Why is variation analysis important in the design process?
A: If you don’t account for variation analysis then your design can have unacceptably low yield levels, or you may be over-designing or under-designing.

Q: What types of variation should an IC designer be concerned about?
A: We categorize seven types of variation:
[LIST=1]

  • Environmental (voltage, temperature)
  • Loading
  • Parasitic dependent effects
  • Layout dependent effects
  • Power dependent effects
  • Global process variation
  • Local process variation

    Q: What would be a first step with your tools?
    A: We recommend that you first identify electrical hotspots.

    Q: Once you find a hotspot do your tools change or optimize my transistor sizes automatically?
    A: No, we don’t optimize your transistor sizes. You have to make that decision based on feedback from our tools, change sizes, then analyse the effects of your new design. We make the whole process easy.

    Q: How would your tools fit into the AMS Reference Flow from TSMC?
    A: Solido tools fit into the AMS Reference Flow 2.0 in five sub-flows:

    • Advanced PVT
    • Advanced Monte Carlo
    • Layout-Dependent Effects (not a product yet)
    • Parasitic Constraint Creation (not a product yet)
    • Power Integrity Constraint Creation (not a product yet)

    Solido Products and Partners
    Here’s the overview picture of Solido products. You continue using your favorite circuit simulator (Spectre, APS, HSPICE, HSIM, AFS, FineSim, Eldo, internal SPICE) along with the foundry-supplied PDK (TSMC, GLOBALFOUNDRIES, Internal for IDMs).

    New at DAC 2011

    • Fast PVT (still Beta), finds the worst case corners about 5-50X faster than running all possible combinations. This is a huge time saver for circuit designers.

    • High-Sigma Monte Carlo, 100x to 1M x faster than pure MC (only uses about 1,000 runs)
    • DesignSense, an interactive, goal-oriented, variation-aware sensitivity tool.

    Q: Which SPICE circuit simulators does Variation Designer work with?
    A: Really any SPICE Simulator – your favorite SPICE, Analog FastSPICE, FastSPICE or internal simulator.

    Q: How do you speed up all of these circuit simulations?
    A. We can run them in parallel on multiple CPUs or cores (300 to 1000 in use now).

    Q: Do your tools run in the cloud as a service?
    A: The cloud looks interesting to us, stay tuned.

    Q: What is different with your Advanced PVT Verification?
    A: Our tool provides fast speed, SPICE accuracy and is scalable.

    The number of corners is rising dramatically with each new generation of process technology and this tool quickly finds the worst-cast PVT corners for your specific design.

    Q: Can you prove that this tool finds the worst-case corner every time?
    A: Not exactly, but it’s within a percent or so of the worst case PVT corner.

    Demo: Fast PVT (Beta)

    I saw an OpAmp example where:

    • 3,645 PVT corner combinations

      • Run Fast PVT corner extractions (quickest to find failures)
      • Fast PVT corner verification (more accurate to find worst case PVT corner)
    • More simulations than corner extractions, more accuracy too (20X speed up over exhaustive simulation)

      • -Looking at DC gain, phase margin, Unity Gain Bandwidth, Idc, Noise (compares prediction versus simulated)
      • Fast PVT corners

    Q: Can you create so much SPICE data that it fills up the hard disk?
    A: It’s smart enough to keep the results small in size, results can also be compressed.

    Demo: DesignSense (where to work on a design to fix failing corners)

    • Sensitivity Analysis, perturbation for all devices in design
    • Independent Sweeps (individual devices)
    • Combination Sweeps (groups of devices together)
    • Visualize the sensitivity of device values across your worst-case PVT corners (previously extracted or simulated)
    • Device combination parameters can be plotted versus spec

    Q: Is this an optimization tool?
    A: No, it tells you sensitivity in your design. You can use Variation Designer along with an Optimizer to get better designs
    sooner. Optimizers take much time to setup correctly and efficiently, it’s quicker to look at DesignSense results, make a judgement, tweak sizes.

    Q: Who are using these new tools?
    A: STARC has recently adopted Solido tools. They are using Variation Designer to find worst cases, and then improve design in as little as 7 hours.

    Q: How long would it take to optimize my OpAmp using DesignSense and PVT?
    A: You would get optimized results within a work day.

    Q: What’s the learning curve for Variation Designer?
    A: It’s easy to get started out of the box within a day or two. Running Fast PVT has an easy learning curve. Running High-Sigma MC takes longer to learn. There are help buttons in context of every dialog that you use.

    Q: How often do you release your software?
    A: As needed, about 3-4 times per year for point releases. Minor releases as needed for hot fixes.

    Six-Sigma Analysis and Design: 6 sigma analysis at 3 sigma costs (time)

    • Capacity? About a 1,000 parameters is practical (5 parameters per device, 200 devices in design)
    • – MC: 1,000,000 samples run in 8 days, 0 failures to spec
    • – HSMC: 1,000,000 samples run (then focus on the tail), 531 samples simulated (10 minutes 15 seconds)
    • – HSMC (5 sigma): 100M samples (after 400 samples then focus on tail), automatically stops, 738 samples simulated (2 hour 14 minutes), 156 failures
    • – Memory Designers love using this tool (Qualcomm used this on a memory bit cell design, Synopsys AMS dinner at DAC – 100 HSPICE licenses)
    • – Now that you found the 156 failures in HSMC then run DesignSense to make the design pass all these conditions

    Advanced MC Analysis (MC+) – Fast (2x to 10x faster run times, can extract statistical corners at a target yield)

    Demo of MC+

    • Choose the number of samples desired, Tasks: Verify Design to 3 sigma target
    • Same OpAmp design used (folded gain, boosting Op Amp, about 100 to 150 devices)
    • Visualize the design results
    • After 23 samples it shows that target yield of 3 sigma cannot be reached (How do you fix this?)
    • Statistical Corner Extraction run. Found 3 sigma corners in only 87 more simulations.
    • Graphical display of sensitivity of all devices and impact on specs

    Summary
    Transistor-level IC designers responsible for analog, IO, memory and standard cells should check out the methodology offered by Solido to find which process corners affect their designs the most, then tweak their designs to be more robust. You continue to use familiar SPICE or Fast SPICE circuit simulators but in a new, more intelligent method than brute-force monte-carlo and get results in a fraction of the time.

    A product video demonstration is available HERE.

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