WP_Term Object
(
    [term_id] => 74
    [name] => ProPlus Design Solutions
    [slug] => proplus-design-solutions
    [term_group] => 0
    [term_taxonomy_id] => 74
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 6
    [filter] => raw
    [cat_ID] => 74
    [category_count] => 6
    [category_description] => 
    [cat_name] => ProPlus Design Solutions
    [category_nicename] => proplus-design-solutions
    [category_parent] => 14433
    [is_post] => 1
)

Process Development, CAD and Circuit Design

Process Development, CAD and Circuit Design
by Daniel Payne on 04-29-2016 at 7:00 am

Working at Intel as a circuit designer I clearly remember how there were three distinct groups: Process Development, CAD and Circuit Design. Each of the groups sat in a different part of the building in Aloha Oregon, we had different job titles, different degrees, spoke with different acronyms and yet we all had to work together somehow to ensure success for our company. There is one company that does span all three of these groups over the past 20 years, and that’s ProPlus. I just watched their latest archived webinar on a new tool for process and device evaluation, so wanted to blog about what I learned.

The CTO of ProPlus is Dr. Bruce McGaughy, he was the presenter in this webinar and we’ve met at DAC over the years to get an update on what’s new. SoC designers today have many foundries to choose from, and each foundry has multiple process nodes where each node may have many variants, so sifting through all of this complexity is a challenge as the Process Design Kits (PDKs) are always changing.

In the days of 180nm process nodes we were using BSIM 3 models for transistor behavior and they used dozens of parameters, however now at the 16nm node we’re using BSIM-CMG models which can have thousands of parameters in each model. Transistors can use macro-models and custom found models, which add to the complexity.

CAD engineers can manage the relationship with the foundry and cope with the PDK files and versions, then the design teams can use the models to run SPICE circuit simulations, monte carlo analysis and other tools for variation analysis. How do you manage all of the revisions inherent in this cycle?

A New Tool
ProPlus has created a new tool dubbed MEPro to help cope with these issues, so here’s what goes into that tool and how it helps in five areas.

Using the PDK model library as the key input you can now explore, compare and even verify the soundness of the models. Designers are assisted because they can understand and explore the process design space. The five ways to look at any process with this tool are:

  • Browse your library files using familiar icons for folders and files
  • Review the process specification sheet to see how it matches your requirements
  • Look at device-level behavior curves
  • See the statistical variation of process parameters
  • Look at circuit simulation results using each process variant

A first-time user of MEPro can invoke the tool, load a PDK library, then click OK to run 1,212 plots showing device performance based on pre-defined templates, all in under 1 minutes by using the built-in Fast SPICE tool NanoSpice. Trying to do the same thing with your own scripts, assembling the plots and presenting the data would likely take days to weeks of effort. The templates may be updated by using a GUI, and then you can save or share any of your projects.

Traditional design books are static documents, while using MEPro you can create all the data used in a design book very quickly and interactively, providing more insight.

One application for MEPro is model exploration by using custom templates that have been configured to your specific needs. One example of customized templates showed how the tool could produce five different types of data: Process Spec Sheet, analog device curves, memory device curves, digital device curves and even custom analysis curves.

Analog designers can explore device characteristics, matching and statistical behavior of a process. Layout Dependent Effects (LDE) can often be a bit mysterious to the designer, so MEPro helps you by visualizing the value of SA graphically. Process variations like multiple Vt choices can be shown graphically for measurements like Idsat as a scatter or linear plot. You can plugin any transistor-level circuit to your template, browse your netlist, then get quick SPICE simulation results shown graphically in one environment.

Users can benchmark and compare two different processes like 28HP and 28HPM, as the tool graphically shows PMOS and NMOS transistor curves. There’s no need for manual data collection, or using Excel for comparisons.

Let’s say that your process model from the foundry has been updated, how do you know the impact on your designs after this revision? Using MEPro you can quickly find out how your most sensitive circuits are affected by a new PDK revision.

Models can actually be verified with MEPro in terms of:

  • Accuracy checking – model versus silicon measurements
  • Quality checking – are there any kinks, glitches, crossover or continuity issues
  • Behavior checking – curves are monotonic, peaks, symmetry, range checking

In summary, you can approach the task of comparing, validating or evaluating PDK models manually or with an automated flow like in MEPro. The time savings with the automated flow approach look impressive. Bridging the gap between foundries and fabless design users is now made easier. Designers can now more readily understand any process, get better margin out of their designs, or even ask the foundry to tweak the process for their specific design.

Dr. Lianfeng Yang then did a live product demonstration to show how intuitive MEPro is to use, running on his laptop.

Watch the entire 59 minute webinar online here.