WP_Term Object
(
    [term_id] => 74
    [name] => Primarius
    [slug] => primarius
    [term_group] => 0
    [term_taxonomy_id] => 74
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 7
    [filter] => raw
    [cat_ID] => 74
    [category_count] => 7
    [category_description] => 
    [cat_name] => Primarius
    [category_nicename] => primarius
    [category_parent] => 157
)
            
Primarius Banner
WP_Term Object
(
    [term_id] => 74
    [name] => Primarius
    [slug] => primarius
    [term_group] => 0
    [term_taxonomy_id] => 74
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 7
    [filter] => raw
    [cat_ID] => 74
    [category_count] => 7
    [category_description] => 
    [cat_name] => Primarius
    [category_nicename] => primarius
    [category_parent] => 157
)

Webinar: A Tool for Process and Device Evaluation

Webinar: A Tool for Process and Device Evaluation
by Tom Simon on 03-24-2016 at 12:00 pm

Not only are foundries continuing to introduce processes at new advanced nodes, they are frequently updating or adding processes at existing nodes. There are many examples that illustrate this well. TSMC now has 16FF, 16FF+ and now 16FFC. They are also announcing 10nm and 7nm processes. In addition, they are going back to older nodes and adding ULP processes for IoT and RF designs.


Then there are other foundries that offer technically competitive processes. With all of this you have a large array of choices for a company contemplating the start of a design project. Operating voltages, leakage, switching speed, device characteristics and many other factors contribute to the final judgment on what process is best for a particular project. For many teams, collecting and comparing information on process trade offs and benefits becomes a huge exercise involving scripts, lots of spice runs, reams of reports, spreadsheets and some amount of guess work.

ProPlus, a leader in circuit simulation, has set about to change the way foundry processes and their PDK’s are evaluated. They have announced their Model Exploration and Platform Benchmark (MEPro) product to help improve the procedure and outcomes of foundry and process selection. MEPro can also help validate libraries and make sure that design errors are not made that eat up margins.

Once a design is started, MEPro offers useful features to ensure that optimal devices are selected for circuit needs. It comes with a large number of built in tests which can be run at the click of a button and the output is displayed in graphical form. It can also help designers plan for process corners.

ProPlus is well positioned to offer a product like this. They already offer a wide range of products dealing with semiconductor simulation, yield, and library development. They have a track record of offering high capacity, high performance solutions. ProPlus will be hosting a one-hour webinar that will go into greater detail on the capabilities and usage of MEPro for evaluating design processes.

The webinar will be held on March 31 at 11AM PDT. The presenter will be ProPlus CTO Bruce McGaughy, who will present a number of case studies, and also will include a demo of MEPro. This webinar is intended for circuit design teams that are using multiple process platforms from one or more foundries. Also process development and modeling engineers will find this session very informative.

Here is the list of topics:

  • Browsing advanced model libraries from all leading foundries
  • Exploring device characteristics and performance to assist designs
  • Evaluating process platform performance with device/circuit targets
  • Benchmarking process platforms from different foundries or nodes
  • Monitoring process revisions and evaluate the impact to circuit designs

To sign up for this session, use this link. This should be a very informative session.

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.