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Optimizing high performance packages calls for multidisciplinary 3D modeling

Optimizing high performance packages calls for multidisciplinary 3D modeling
by Tom Simon on 10-16-2019 at 10:00 am
Categories: Dassault Systemes, EDA

For all the time we spend thinking and talking about silicon design, it’s easy to forget just how important package design is. Semiconductor packages have evolved over the years from very basic containers for ICs into very specialized and highly engineered elements of finished electronic systems. They play an important role … Read More

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Embeddable FPGA Fabric on TSMC 7nm

Embeddable FPGA Fabric on TSMC 7nm
by Tom Simon on 12-14-2018 at 7:00 am
Categories: Achronix, AI, FPGA

With their current line-up of embeddable and discrete FPGA products, Achronix has made a big impact on their markets. They started with their Speedster FPGA standard products, and then essentially created a brand-new market for embeddable FPGA IP cores. They have just announced a new generation of their Speedcore embeddable… Read More

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Making AI Silicon Smart with PVT Monitoring

Making AI Silicon Smart with PVT Monitoring
by Tom Simon on 11-26-2018 at 7:00 am
Categories: AI, IP, Moortec

PVT – depending on what field you are in those three letters may mean totally different things. In my undergraduate field of study, chemistry, PVT meant Pressure, Volume & Temperature. Many of you probably remember PV=nRT, the dreaded ideal gas law. However, anybody working in semiconductors knows that PVT stands … Read More

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A Smart Way for Chips to Deal with PVT Issues

A Smart Way for Chips to Deal with PVT Issues
by Tom Simon on 10-30-2018 at 7:00 am
Categories: IP, Moortec
4 Comments

We have all become so used to ‘smart’ things that perhaps in a way we have forgotten what it was like before many of the things we use day to day had sensors and microprocessors to help them respond to their environment. Cars are an excellent example. It used to be commonplace to run down your battery by leaving your lights on. Now cars … Read More

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Webinar: NetSpeed is about to change the way SOCs are designed

Webinar: NetSpeed is about to change the way SOCs are designed
by Tom Simon on 08-20-2018 at 12:00 pm
Categories: AI, EDA, Events, IP, NetSpeed Systems
2 Comments

A large part of the effort in designing SOCs has shifted to the integration of their constituent IP blocks. Many IP blocks used in SOCs come as ready to use components and the real work has become making them work together. Network on Chip (NoC) has been a huge help in this task, handling the interconnections between blocks and planning… Read More

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Netspeed and NSITEXE talk about automotive design trends at 55DAC

Netspeed and NSITEXE talk about automotive design trends at 55DAC
by Tom Simon on 08-02-2018 at 12:00 pm
Categories: Automotive, EDA, Events, IP, NetSpeed Systems

DAC is where both sides of the design equation come together for discussion and learning. This is what makes attending DAC discussion panels so interesting; you are going to hear from providers of tools, methodologies and IP as well as those who need to use them to deliver working solutions. There are few places where the interplay… Read More

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The lofty rise of the lowly FPGA

The lofty rise of the lowly FPGA
by Tom Simon on 01-10-2018 at 7:00 am
Categories: Achronix, FPGA, IP
4 Comments

FPGA programmable logic has served in many capacities since it was introduced back in the early 80’s. Recently, with designers looking for innovative ways to boost system performance, FPGA’s have moved front and center. This initiative has taken on new urgency with the slowing down of process node based performance gains. The… Read More

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HBM offers SOC’s dense and fast memory options

HBM offers SOC’s dense and fast memory options
by Tom Simon on 08-22-2017 at 7:00 am
Categories: IP, Synopsys

Dual in-line memory modules (DIMM’s ) with double data rate synchronous dynamic random access memory (DDR SDRAM) have been around since before we were worried about Y2K. Over the intervening years this format for provisioning memory has evolved from supporting DDR around 1995, to DDR1 in 2000, DDR2 in 2003, DDR4 in 2007 and DDR4… Read More

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How to nail your PPA tradeoffs

How to nail your PPA tradeoffs
by Beth Martin on 11-03-2016 at 4:00 pm
Categories: EDA, Mentor, a Siemens Business

Image RemovedHow do you ensure your design has been optimized for power, performance, and area? I posed this question to Mentor’s Group Director of Marketing, Sudhakar Jilla and product specialist Mark Le. They said that finding the PPA sweet spot is still often done by trial and error – basically serial experiments with various… Read More

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Webinar: A Tool for Process and Device Evaluation

Webinar: A Tool for Process and Device Evaluation
by Tom Simon on 03-24-2016 at 12:00 pm
Categories: EDA, ProPlus Design Solutions

Not only are foundries continuing to introduce processes at new advanced nodes, they are frequently updating or adding processes at existing nodes. There are many examples that illustrate this well. TSMC now has 16FF, 16FF+ and now 16FFC. They are also announcing 10nm and 7nm processes. In addition, they are going back to older… Read More