RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)
Semiconductor Expert Forum

Posted on

Semicon West

Semicon West
by Paul McLellan on 07-11-2012 at 7:08 pm
Categories: ESD Alliance, Semiconductor Services

I have been spending some time at Semicon West at the Moscone center the last couple of days. Since it was only a month ago that I was there for DAC, the first contrast is the size of the show. DAC didn’t fill Moscone South. Semicon fills Moscone South, and North, and the corridor between. And Moscone West on the other side of 4th street. Admittedly there is a co-located solar show but that is not a large fraction.

The big news of the show was Intel/ASML’s announcement that Intel is putting a lot of money into ASML for EUV (see below) and 45cm (18″) wafer technology. They were even one of the speakers at a fascinating session I attended.

I spent all morning today at a series of presentations about lithography. I blogged recently about how wafer prices going up faster than transistor densities (the scariest graph I’ve seen recently) which is essentially a graph and a story all about lithography, when you look under the hood.

Right now, continuing to use 193nm light and immersion lithography, everyone seems confident we can build 14nm chips (and smaller). But whether we can build them economically is the big question. At 20/22nm we have to double pattern the 1X layers (the higher levels of metal are on coarser grids and so don’t require it). We may have to triple pattern the first layer of metal since we really want both vertical and horizontal segments. Double patterning requires that you do some things twice and so costs more (although not twice as much). It also requires two masks so NRE is higher too, pushing up the fixed costs of taping out a design and manufacturing the first wafer.

There are three technologies that are in some level of development, and there were presentations about all of them. I will blog about each of them in more detail in the coming few days. But the executive summary is as follows:

Extreme Ultra-Violet (EUV) is shorter wavelength light (14nm or so). At that wavelength the light can’t get through lenses (or even air) so we have to switch to reflective optics and reflective masks. We don’t yet have good ways to generate the light at high enough power but a lot of work is being done. We don’t yet have photoresist that is responsive enough. We can’t build defect-free mask blanks (and never will be able to). The big advantage is that we don’t need double patterning so only one mask per layer. But unless the throughput is high enough that isn’t a big enough advantage.

Next is DWEB, Direct Write Electron Beam. This is even better on the mask front. None of them. More like an old CRT TV used to write on the phosphor, this scans an electron beam across the photoresist and scans the design. The challenge again is getting throughput up, and having responsive enough photo resist. Plus the data handling is a challenge with thousands of beams writing simultaneously across a whole wafer (this isn’t reticle/stepper type technology).

OK, so if lithography can’t hack it, how about we do something really spacey. How about we do directed self-assembly (DSA). This is something that a few academics have been looking at but suddenly a few years ago industry started to look at seriously. If you mix two substances that don’t mix (like oil and water) but that polymerize (so not oil and water, more like polystyrene) then if you just mix them and put them on a wafer you get a random pattern like a fingerprint. But if you first put down some guidance (hence “directed” self assembly) such as tracks on the wafer at 80nm spacing (which is easy today) and put the mixture in between, then instead of just forming random patterns, it lines up into nice 14nm tracks of alternating polymers. And if you build a trench and put some of the mixture in with the right ratio, it will form a few tiny holes. This is a long way from a chip, of course. But building lines and holes is the basis of chips. Then immersion lithography was considered out there not that long ago.

TL;DR EUV, DWEB or DSA

Posted on

Atrenta Technology Forum, Japan

Atrenta Technology Forum, Japan
by Paul McLellan on 07-11-2012 at 6:32 pm
Categories: EDA

The 1st Atrenta Technology Forum in Japan (well, it used to be the user group meeting, so it’s only the first in a very technical sense) is next week on July 19th from 1pm until 5.15pm. It will be held in the Shin-Yokohama Kokusai Hotel (how to access it here).

In the unlikely event that non-Japanese are reading this blog, here’s the story about Shin-Yokohama (“shin” means new in Japanese. And Chinese as it happens: Hsinchu). When they built the first of what people in the US call bullet trains and are prosaically called shinkansen (new line) in Japan, it was impractical to route it through Yokohama station, so they built a brand new station in the middle of rural fields outside Yokohama and that was Shin-Yokohama Station. That was in the early 1960s. Since then a whole new town, Shin-Yokohama has grown up around it.

Here is the agenda for the meeting:

  • 13.00-13.30 Registration
  • 13.30 to 14.00 Semiconductor market and design trends. Atrenta Japan
  • 14.00 to 14.30 TSMC quality assesment with DMP 3D graphics IPcore. Digital Media Profesionals.
  • 14.30 to 14.45 What’s SpyGlass Advanced Lint. Atrenta Japan.
  • 14.45 to 15.15 Tips on asynchronous design and case study with SpyGlass family. Nippon System Ware Co
  • 15.15 to 16.00 Break and demo
  • 16.00 to 16.15 What’s SpyGlass Physical Base, Atrenta Japan.
  • 16.15 to 16.30 SpyGlass Physical case study. Renasas Electronic Corporation.
  • 16.30 to 16.45 Atrenta Update. Atrenta Japan.
  • 16.45 to 17.15 Update for 2011 STARC Design Style Guide

For more information including how to register to attend (in Japanese) is here.

Posted on

Using Synopsys Analysis Tools for AMS Design

Using Synopsys Analysis Tools for AMS Design
by Daniel Payne on 07-11-2012 at 12:05 pm
Categories: EDA, Synopsys

I attended the Synopsys webinar today for a tool called Custom Explorer Ultra (CXU). Product details on the Synopsys web site are here. The CXU tool would be used by AMS designers that want to setup, control and view results from simulators like HSPICE, CustomSim or VCS on transistor-level and AMS designs. Continue reading “Using Synopsys Analysis Tools for AMS Design”

Posted on

Enabling 3D-IC Integration

Enabling 3D-IC Integration
by Daniel Nenni on 07-10-2012 at 9:00 pm
Categories: EDA, Synopsys

stevesmith80x95

As 2D device scaling becomes impractical, 3D-IC integration is emerging as the natural evolution of semiconductor technology; it is the convergence of performance, power and functionality. Some of the benefits of 3D-IC, such as increasing complexity, improved performance, reducing power consumption and decreasing footprints, are proven and readily understood. Other reported benefits, such as improving time-to-market, lowering risk and lowering cost, still need to be realized before 3D-ICs become a commercially viable alternative to traditional 2D architectures. The availability of Synopsys’ silicon-proven tools and IP is an important contribution to deploying 3D-IC integration technology in the semiconductor industry.

Web event: Enabling 3D-IC Integration
Date: July 18, 2012
Time:10:00 AM PDT

Duration: 45 minutes + Q&A

In this webinar, a guest speaker from Xilinx will introduce the challenges of designing for large capacity and performance and how Xilinx is innovating using Stacked Silicon Interconnect technology to deliver higher levels of integration and flexibility in their FPGA products

Speakers:


Steve Smith
Senior Director, 3D-IC Strategy and Marketing, Synopsys

Steve Smith is currently responsible for Synopsys’ 3D-IC strategy and marketing. He has been with Synopsys for 15 years, having served in various functional verification and design implementation marketing roles. He has worked in the EDA and computer industries for more than 30 years in a variety of senior positions including marketing, applications engineering and software development.


Shankar Lakka
Director of IC Design, Full-Chip FPGA Integration Group, Xilinx

Shankar Lakka is the Director of IC Design in the Full-chip FPGA Integration Group at Xilinx. He has been at Xilinx for more than 16 years, and has held various positions in the CPLD and FPGA divisions and led multiple projects across multiple sites. Shankar recently led the design and full-chip integration of Xilinx SSI devices. He holds 14 U.S. patents.

Posted on

SNUG in Asia, US East Coast

SNUG in Asia, US East Coast
by Paul McLellan on 07-10-2012 at 8:05 pm
Categories: EDA, Synopsys

If you are in Asia then the Synopsys user group SNUG is coming up, soon in Japan and next month in China. Actually if you are in India I’m afraid you already missed it last month, just after DAC.

SNUG Japan is on 12th July in a couple of days time from 10am until 8pm in Tokyo.

In China there are 3 between August 14th and 21st

  • Beijing 北京
  • Shanghai 上海
  • Shenzhen 深圳

Details (in Chinese) here.

Also slipped in there is SNUG Singapore on August 17th. Details (English) here.

SNUG Taiwan is August 28th to 29th in Hsinchu. Details (English) here.

Then in September, the East Coast of North America has its turn:

  • Boston on September 6th. Details here.
  • Ottowa on September 10th. Details here.
  • Austin (OK, not really East Coast) on September 28th. Details here.

Posted on

Formal Going Mainstream

Formal Going Mainstream
by Paul McLellan on 07-10-2012 at 7:29 pm
Categories: EDA
3 Comments

In Mike Muller’s keynote at DAC he wanted to make formal approaches an integral part of writing RTL. After all, formal captures design intent and then, at least much of the time, can verify whether the RTL written actually matches that intent. Today, formal is not used that way and is typically something served “on the side” by specialist formal verification experts. It is still very valuable and regularly finds issues, especially corner cases, that simulation has missed. However, by letting the design engineers get away without having to document their intent it risks missing problems, since the formal experts inevitably have to deduce some of the intent from the RTL they are verifying, which is obviously a circular loop with potential for letting bugs escape into the wild.

The big EDA companies all have a formal solution of some sort, but they are unlikely to be the ones spearheading this. They all have simulators and simulation verification environments too, and will quite happily sell you as many licenses as you want. Indeed, if a few dozen formal licenses turn out to substitute for a server farm with a bazillion simulation licenses, it is not necessarily even good business for them to encourage the transition.

Jasper, however, only has a formal product line. If you use a lot of simulation as an alternative they don’t participate in that business. Of course simulation is not going away and Jasper’s approach is to combine metrics from formal verification with metrics from simulation-based verification to accelerate verification closure. In particular, there is never any point in running simulation to partially verify some aspect of a design that formal has already proven; it’s just a waste of computer time.

The metrics for formal verification come in two flavors. Firstly, how complete the coverage is based on the properties and the stimuli. Secondly, how successful JasperGold (or whatever formal tool you are using) is at proving those properties, which may be fully proven or a bounded proof (or it finds a counterexample which obviously doesn’t contribute to verification closure directly, but exposes an issue which must be fixed). This is all then integrated into a coverage database to include unreachable targets that do not need to be verified, along with coverage information from formal analysis that do not need to be re-verified using simulation.

The first way to use this approach is to establish the completeness of the formal testbench. In particular, analyzing:

  • Dead code
  • Branch coverage
  • Statement coverage
  • Expression coverage

After the formal analysis, properties may be completely proven or only have a bounded proof. This means that only part of the reachable state-space was analyzed and that no violation was detected there. For example, all states within K cycles of the reset were examined and no violation was detected. Obviously this means that problems might occur after K cycles.

This approach allows confidence that the verification is not over-constrained (relying on an external property that still has to be proved) and allows proven (and perhaps bounded proven) aspects of the design to be eliminated from the simulation verification plan.

This information can then be combined with information in a simulation coverage database such as UCDB to merge all the coverage metrics into a single verification coverage metric that combines formal and simulation approaches.

These features in JasperGold will be released to beta during the second half of this year with production either late this year or in the first half of next year.

Posted on

Intel Opens a New Front with ASML

Intel Opens a New Front with ASML
by Ed McKernan on 07-10-2012 at 4:00 pm
Categories: Foundries, Intel Foundry, TSMC

Behind great humor often lies irony. In the midst of a struggle by the European Union to extract $1.3B from Intel in an ages old Anti-Trust case, the latter makes a strategic move to embolden the Dutch firm ASML to accelerate the development of 450mm and EUV and thus save a continental jewel. What now say EU? When disfunction and bankruptcy abound, beware the need of sovereigns to extract not pints but gallons of blood. Intel sees an end game at hand, not today but in just a couple of years and it plays into its plans to win all of mobile: including Apple and Samsung. They parry the EU assault with a massive $4B investment and prepare to watch the poker players ante up or fold.

Intel Always Fights a Multi-front war knowing that it eventually wears down the enemy. Please, please we don’t speak of enemies unless we are in the realm of politics! However, one should be aware that without TSMC there is no Qualcomm, nVidia, AMD, Broadcom, Marvell and the rest of the ARM camp (especially ARM). And what of Apple and Samsung, the two leaders of the mobile Tsunami who will have 80%+ of the Smartphone and Tablet market by the New Year? They will have a choice to make in which the first one who blinks will have the opportunity to be years ahead of the other.

It is simple mathematics. Assume, conservatively that Intel is two years ahead of TSMC. Now presume Intel, conservatively launches 450mm two years ahead of TSMC, then it is like a 4 year lead in process technology. Now input your die sizes and run the cost models. It is daunting having to stare up at the Matterhorn before the climb begins.

We have learned in the past 6 months that Smartphones and Tablets are demanding leading edge process technology (Qualcomm sold out this year on 28nm 4G LTE chips). This was the one doubt that I had as to whether Qualcomm, nvidia and the rest of the ARM camp were safe in the foundries at an n-1 node while Intel played catch up with a true low power processor and baseband functionality. Intel can now force the game forward and even Apple will now have to consider how wise it is to hang back in older processes. Some amount of their processors will need to step up to the leading edge for cost and performance reasons.

The news articles from yesterday stated that ASML was open to additional investments from other foundries (i.e. TSMC and Samsung). I can see Samsung stepping up. TSMC is an extension of Qualcomm, Broadcom, nVidia and others. They will likely have to devise new long-term agreements from their partners that requires them to pony up dollars for the ASML investment. Or alternatively does Qualcomm write a check to ASML?Does Apple?

The maneuvers lately point to every survivor going vertical, however now we are looking at two separate vertical models. There is the device vertical model with LCD screens, NAND Flash, enclosures etc.. that Apple and Samsung are very adept at. In last weeks blog I mentioned how Intel was funding Taiwanese panel makers to guarantee supply for ultrabook manufacturers (likely at the expense of AMD and nVidia). Now we have Intel letting the world know that being a MAN in the semiconductor industry requires owning more than just fabs. Real Men must now invest in the semiconductor R&D tool chain. The Question that Wall St. should ask is the following: What is the total value that will derive 4-5 years down the line from an investment in ASML’s R&D?

FULL DISCLOSURE: I am Long AAPL, INTC, QCOM, ALTR

Posted on

SPICE Timing Correlation for IC Place and Route

SPICE Timing Correlation for IC Place and Route
by Daniel Payne on 07-10-2012 at 10:35 am
Categories: EDA

SPICE circuit simulation is used for transistor-level analysis while Place and Route tools are typically used to connect cells and blocks of an SoC, so why would there be a connection between these two EDA tools?

I read a press release today from ATopTech and Berkeley Design Automation that talked about how SPICE and P&R are connected, so I contacted Eric Thune of ATopTech to learn more. Eric has worked at: Apache Design Solutions, I2 Technologies, Synchronicity, Synopsys and TI. Continue reading “SPICE Timing Correlation for IC Place and Route”

Posted on

High-Productivity Analog Verification and Debug

High-Productivity Analog Verification and Debug
by Daniel Nenni on 07-08-2012 at 10:40 pm
Categories: EDA, Synopsys

See how Synopsys’ advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS. CustomExplorer Ultra is a comprehensive simulation and debug environment for analog and mixed-signal design verification.

Web event: High-Productivity Analog Verification and Debug with CustomSim and CustomExplorer Ultra
Date: July 11, 2012
Time:10:00 AM PDT

Duration: 45 minutes + Q&A

REGISTRATION

This webinar demonstrates an advanced verification methodology using CustomExplorer Ultra with CustomSim and CustomSim-VCS that enables highly-productive verification and debug of analog and mixed-signal designs. CustomSim and CustomSim-VCS provide fast simulation engines while CustomExplorer Ultra is a complete verification environment for managing simulation corner and Monte Carlo setup, a flexible simulator interface, multiple testbenches, and interactive cross-probing with popular design environments, such as Galaxy Custom Designer and Virtuoso ADE for fast circuit debugging.

Speakers:

Duncan McDonald
Product Marketing Manager, Synopsys

Duncan has more than 20 years of experience in EDA, holding positions in engineering, sales, and marketing all related to analog and mixed-signal design. Duncan is the author of 3 U.S. patents and holds degrees from UC Berkeley and the University of Santa Clara.

Posted on

DAC 2012 Cheerleader Controversy!

DAC 2012 Cheerleader Controversy!
by Daniel Nenni on 07-08-2012 at 9:00 pm
Categories: EDA, Events

First, I must say that I’m biased. I like Cheerleaders, they are lots of fun, I even married one. Second, I’m not a fan of Peggy Aycinena. She has been on her EDA feminist rant for years now and I have been targeted multiple times. My solution has been to ignore her and any publication that supports her but this time she has gone too far.

It first started when Paul McLellan posted a blog on SemiWiki about the 49er Cheerleaders appearing at DAC 2012. What a great idea! The blog was deleted shortly thereafter and I was told by Paul that as it turns out the 49er Cheerleaders will not be attending DAC 2012. Bummer I thought. Even my wife, who attended DAC 2012, was disappointed.

Then I read an article by Mike Demler:

As the industry continues to shrink, can EDA bring sexy back?

Mike is a great guy, I’m a fan of his site, he is very credible:

DAC organizers made some initial attempts to liven up the proceedings, by signing up a few of the San Francisco 49er cheerleaders to wake up attendees before an 8:30 AM keynote address, on the second day of the conference. The cheerleaders, who regularly appear before crowds (including many families) of 70,000 fans at every 49er home game, also are known for their charitable work, and for their careers and education beyond the football field. Nevertheless, according to sources who would only speak off the record, when a female EDA blogger launched a personal protest of the cheerleaders, contacting EDAC Board members and DAC organizers, they cancelled the appearance. Attempts to get a statement from the DAC Executive Committee have gone without a response. Gold Rush management has also declined to comment.

After reading this, I felt sure Peggy was behind it but could not confirm and Paul McLellan was not talking. Paul is the official DAC webmaster so I understand his tight lips. I also understand the decision by the DAC people to cancel to avoid controversy.

Next comes John Cooley’s article:

Peggy bans 49er cheerleaders, Gabe wants Denali party cancelled

I do read John, don’t always agree with him, but certainly respect the work he has done on DeepChip:

I can’t believe this. The DAC Executive Committee caved into to the angry feminazi rants of Granny Peggy Aycinena????? WTF? Just because Peggy wouldn’t have appreciated these cheerleaders, a good 90% of the heterosexual male population at this DAC would have! WTF???

Okay, John is being crude here but I agree with his point. I don’t like a moral majority of one person making decisions on what is and is not appropriate for an entire crowd.I also don’t appreciate the negative label Peggy attaches to the 49er Cheerleaders. They are athletes, goodwill ambassadors, and they deserve better(I bold this because it is the main point of this blog).

Gabe Moretti also did an article on this (according to John Cooley) but I don’t read his site Gabe on EDA and it did not come up on Google. Maybe he thought better than to get on Peggy’s bad boy list and deleted it. Or maybe Gabe’s site is not search engine friendly. Probably both.

Peggy’s response to all this did come up on Google to which I’m reading for the first time:

Cooley: Ignore the men behind the curtain by Peggy Aycinena

This rant is so fractured I don’t even know what to cut and paste so you will just have to read it yourself. She goes “eye for an eye” with John attacking him personally and with increased venom. Included is a list of people she has pissed off and I’m on it and this is why.

Last year Paul McLellan did an article on SemiWiki: Semiconductor Virtual Model Platforms which included a picture of a female model (nothing racy). Peggy posted a rant against Paul, me, and SemiWiki so we changed the pic to what you see today. That rant was also removed after Paul bought her lunch to smooth things over. Even better, Peggy once called some of the DAC hostesses (booth babes) prostitutes. That article was removed as have most of her other rants. This latest one will probably be removed so I saved a copy just in case because it really is quite funny in a disturbing sort of way.

This was my 29[SUP]th[/SUP] DAC so I have seen the evolution first hand. In fact, I was pleasantly surprised when DAC allowed alcohol on the show floor, which apparently Peggy is okay with, for now anyway. My opinion: We are adults and can make personal choices as we see fit. It would have been nice to have been allowed the choice of attending the 49er Cheerleader DAC session or not. Next year hopefully an actual majority will prevail and we will see Cheerleaders serving beer!