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Apache/Ansys presents: 3DIC thermal, transmission lines, low frequency analysis

Apache/Ansys presents: 3DIC thermal, transmission lines, low frequency analysis
by Paul McLellan on 12-16-2012 at 10:00 pm

Late in January it is DesignCon at the Santa Clara convention center from January 28th-31st. Details are here.

On Tuesday from 11.05 to 11.45 Apache and Ansys will be presenting on Thermal Co-analysis of 3D IC/packages/system. This is being presented by a whole team of people: Stephen Pan, senior product specialist at ANSYS; Norman Chang, VP product development at Apache; Mark Qi Ma, a product engineer at Apache; Gokul Shankaran, a product specialist at ANSYS;Product Specialist, ANSYS; and Manoj Nagulapally, R&D manager at ANSYS.

The title of the paper makes it pretty clear what they will be presenting. Thermal management in 3D-IC designs is critical because the heat can’t easily get out from in the heart of a 3D stack of die. We are used to having to model temperature effects on a single die, but in a stack a hot spot on one die can affect the performance of the die above and below. And, of course, the performance has an affect on the temperature.

Accurate temperature maps on chips have impacts on chip reliability and performance such as EM limits, IR maps, and power distribution. Chip, package, board, and system are all thermally coupled, but with very different length scales. While it is still a challenge to include the details of all the levels in one thermal-analysis model using current technology, an accurate and practical co-analysis flow is presented to help manage thermal problems on 3D-ICs. Apache/ANSYS will describe a methodology in power-thermal co-analysis of 3D-IC packages through power-temperature iterative loops at the chip-package level and power-thermal BC iterative loops involving chip, package, and system (CPS).

Then from 2.50 to 3.30 that same day (Tuesday) Ansys, Intel and the University of South Carolina present Analytic Solutions for Periodically Loaded Transmission Line Modeling. This paper is presented by Paul Huray from University of Southern Carolina, Priva Pathmanathan from Intel and Steve Pytel, the Signal Integrity Product Manager for ANSYS.

Next day, on Wednesday from 11.05 to 11.45 ANSYS presents A Reverse Nyquist Approach to Understanding the Importance of Low-Frequency Information in Scattering Matrices. The paper is presented by Daniel Dvorscak and Michale Tsuk of ANSYS.

High-speed applications require high-frequency (20 GHz+) S-parameter models. While high bandwidth is important, it is also critical to model the behavior accurately at low frequency. When using S-parameter models in circuit simulation, the lack of proper low-frequency content can result in inaccurate results due to the simulator’s lacking enough information to recapture physical properties of the model, such as insertion delay, inter-symbol interference, or the lower knee frequency of discrete passive components. This session will cover the pitfalls of low-frequency undersampling, as well as how to use the duality of time and frequency for predicting the appropriate frequency sampling required when generating individual as well as concatenating models.


TSMC 28nm and 20nm Update Q4 2012

TSMC 28nm and 20nm Update Q4 2012
by Daniel Nenni on 12-16-2012 at 7:00 pm

The big news in Taiwan last week was another increase in TSMC capital expenditures to $9B in 2013. That number could grow however. Last year TSMC CAPEX was set at $6B and ended up at $8.3B due to rapid 28nm capacity expansion and an accelerated 20nm program. 2013 will be all about FinFETs and manufacturing Apple SoCs so $9B may not cover it.

Taiwan weather was very nice last week, for me anyway. Cooler than normal, cool enough for me to wear a suit and tie, which I very rarely do. It is so rare that people joked and took pictures. And thank you to the Hsinchu Royal Hotel for upgrading me to a suite. You never know when you need a second bathroom in your hotel room.

In 2012 TSMC sales will grow a whopping 19%! TSMC revenue for 2013 is expected to grow 15-20% which is a conservative estimate in my opinion. TSMC 28nm will continue to break process node records and the mobile market will continue to drive economic growth. The semiconductor industry should also do well in 2013 with a predicted 5% growth versus a 3% contraction in 2012.

Speaking of 28nm, TSMC made significant progress in both yield and performance this quarter so we will see even more good 28nm die in 2013 and they will be faster. I give 100% credit to the gate-last implementation of HKMG. Interesting to note, TSMC actually started 28nm research using gate-first HKMG but changed to gate-last due to yield and manufacturing issues. Fortunately TSMC has the advantage of high volume production experience using a broad set of applications. Not just CPUs or GPUs, but FPGAs, SoCs, and dozens of other design types from more than one thousand customers.

IBM on the other hand does not have that breadth of fabless semiconductor customer experience so they went with a gate-first approach at 28nm leaving common platform partners GLOBALFOUNDRIES and Samsung way behind the manufacturing yield and performance curve. TSMC owns the 28nm node and that is why they will have another big revenue year in 2013. TSM stock at $20 in 2013! Believe it!

20nm will be a much more interesting node in regards to competition however. After learning the gate-first lesson, IBM is following TSMC with a gate-last HKMG implementation at 20nm. Unfortunately the added difficulty of 20nm double patterning and lithography challenges, which have yet to be solved at a production level, is causing delays. The fabless semiconductor ecosystem is working around the clock on this and I honestly expect a hockey stick 20nm production curve once this has been solved. Crowdsourcing at its finest!

The other big news was the Intel 22nm SoC process announcement at IEDM last week. I was very vocal about Intel not understanding the SoC business when they jumped into the foundry mix last year. This is a big first step but Intel still has a long way to go. I will do a much more detailed analysis in my next blog and you will see what I mean. Let me apologize in advance to the Intel PR people as I take some wind from their over blown sails.

While I enjoy my monthly trips to Taiwan it sure is good to be home. Absence does make the heart grow fonder.


Novocell team finishes record-breaking year with record number of new customers

Novocell team finishes record-breaking year with record number of new customers
by Eric Esteve on 12-14-2012 at 8:10 am

In this pretty shaky NVM IP market, where articles frequently mention legal battles rather than product features, it seems interesting to take a look at this Newsletter from Novocell Semiconductor starting with these words: “As the Christmas carols and festive music floods the airwaves (and the shopping areas) here in western Pennsylvania and the threat of cold and snow looms, the cheery band of engineers at Novocell are finding themselves overcome with the holiday spirit…”

This is a nice way to start a Newsletter, but you also can find some post about very interesting topics. Like this one about the legacy nodes, where we can discover that customer project increase at nodes from 90nm and above:

Rumors of the demise of legacy nodes have been greatly exaggerated;

2012 customer project work and interest increases at nodes from 90nm to 350nm!

During the past 6 months, we have been seeing a noticeable increase in inquiries, quotes, and project wins for customer projects at nodes from 130nm, 180nm, 250nm and that old standby, 350nm.

Reading the industry press would give the impression that the world has moved to 28 and 40nm processes, and that a vast majority of the microelectronics/SoC industry is preparing to rollout on 20nm next year and on 14nm finFET as soon as TSMC’s new plant doors open in 2015…
… to be continued in the newsletter

If you didn’t knew, you will learn why Novocell’s Smartbit-family of OTP, the only anti-fuse vendor providing OTP at the larger process nodes, provides the highest level of foundry and process independence available.
Very interesting to notice, Novocell has decided to propose a new type of license, that you usually would see in the Software of RTL IP market:

Novocell introduces new “Evaluation Period” License

As more and more firms have come knocking to inquire about antifuse OTP in general, and advantages of our unique Smartbit technology in specific, we have encountered a large number of firms who have had experience with EEPROM and conventional ROM, but have not worked with memory quite like ours.

Perhaps like you, they are used to getting surprises downstream in projects: additional chip area needs for redundant bits and error correction circuitry based on reliability requirements; Or they commonly have been burned by other technologies’ integration difficulties or late-breaking news of needs for charge pumps, control circuitry, or other “gotcha’s”.

To help ease these concerns, Novocell has introduced an Evaluation License, that provides your team from 6-9 months to evaluate the Novocell IP macro of interest at a cost reduced to cover support and IP updates, and allows for conversion to a standard IP license upon move to production.

Did you know that Novocell had close a strong technology partnership with major silicon foundries, like IBM, and that Novocell has completed the final validation step and has been approved as a IBM Foundry Business Partner, along with recognition of the foundational Novobits OTPproduct line as a Ready for IBM Technology?

Then, You should have a look at the newsletter!

Eric Esteve from IPNEST



Apache Presents: ESD analysis

Apache Presents: ESD analysis
by Paul McLellan on 12-13-2012 at 1:15 am

The 26th Conference on VLSI Design will be in Pune, India from January 5th to 10th at the Hyatt Regency. Details on the conference here. Registration here. I happened to be involved in the first of these conferences, which was held in Edinburgh where I was wrapping up my PhD. It was in the considerably less palatial surroundings of the Appleton Tower before it was modernized and was run on a shoe-string. We would have been surprised to have a time-traveler come back and tell us that the conference would still be going in 2013 and perhaps even more surprised that it would be in India.

At next month’s conference, Apache (I guess you all know it is a subsidiary of Ansys by now, don’t you) is presenting a paper jointly with nVidia

The paper is on Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Maco-level Dynamic Solutions, presented by Norman Chang and Jai Pollayil of Apache and Ting-Sheng Ku of nVidia on 9th January from 11am to 12.20pm (the dreaded presentation spot being between the audience and lunch). By the way, I love the way the sessions are called “pre-lunch”, “post-lunch” and “post-afternoon-tea”. Bit like a cricket test match (which, for Americans and others who are totally bemused by cricket, takes place over 5 days with meal breaks, makes baseball seem like a blink of an eye).

The paper examines the comprehensive ESD static/dynamic methodology that was developed for failure diagnosis and predictive simulation of improvements. This methodology focused on full-chip static and dynamic analysis including modeling of die-level metal grid, substrate grid and well diode, package effective capacitance, and pogo pin. The paper includes real-world human body model (HBM) and charged device model (CDM) applications.

The paper focuses on an integrated methodology for how a full-chip static and block-based dynamic ESD methodology provides comprehensive coverage on HBM/CDM issues, which are resistive-dominant, and the dynamic problems that require more detailed RLC and transistor-level modeling. This methodology uses PathFinder, an Apache tool that performs full-chip static analysis and constructs dynamic ESD circuits with complete parasitic models in simulation.


New HP Memristor Material Developments

New HP Memristor Material Developments
by Ed McKernan on 12-12-2012 at 10:00 pm

At the recent NCCAVS Thin Film Users Group meeting in November, HP was on the program in the person of Joshua Yang who gave a materials centric look at the status of the HP ReRAM (Memristor) program. A colleague passed on the informative set of slides presented at the meeting. Being a former process integration team leader, I was immediately struck by a couple of TEMs on the Roadmap slide during my first scan of the presentation! Joining up a few dots and tracking down the reference (a joint paper with SK Hynix at the 2012 VLSI Technology Symposium*), the TEMs are probably from the Hynix/HP collaboration and show a 54nm (half pitch?) cross bar array fabricated over larger technology node CMOS. More over atReRAM-Forum.com.

By Christie Marrian


A Comparison of SemiWiki and DeepChip

A Comparison of SemiWiki and DeepChip
by Daniel Payne on 12-12-2012 at 9:06 pm

An email update from John Cooley at DeepChip this morning prompted the bloggers here at SemiWiki to continue the discussion and point out incorrect data, so that readers realize what is really happening with our media portals as sources of timely and relevant news and opinion. I respect what John Cooley has done with DeepChip over the decades, but let’s talk about the arcane numbers of online publications a bit.

Continue reading “A Comparison of SemiWiki and DeepChip”


A Brief History of Synopsys

A Brief History of Synopsys
by Daniel Nenni on 12-12-2012 at 1:00 pm

One of the largest software companies in the world, Synopsys is a market and technology leader in the development and sale of electronic design automation (EDA) tools and semiconductor intellectual property (IP). Synopsys is also a strong supporter of local education through the Synopsys Outreach Foundation. Each year in multiple regions, the company conducts science fairs, offering funding, equipment, supplies and training to students and teachers. This fusion of technology and education, designed to spark innovation, served as the catalyst for forming the company.

As a young immigrant to the United States in the late 1970s, Dr. Aart de Geus, Synopsys’ co-founder, chairman and co-CEO, enrolled at Southern Methodist University in Dallas, and became immersed in the school’s electrical engineering program. He soon went from writing programs designed to teach the basics of electrical engineering, to hiring students to do the programming. In the process, he discovered the value of taking a technical idea, creatively building on it, and then motivating other people to do the same. This principle ultimately fueled the creation of Synopsys.

After earning his Ph.D. and gaining a wealth of CAD experience at General Electric, Dr. de Geus and a team of engineers from GE’s Microelectronics Center in Research Triangle Park, N.C. – Bill Krieger, Dave Gregory and Rick Rudell – co-founded synthesis startup Optimal Solutions in 1986.

The following year, the company moved to Mountain View, Calif., became Synopsys (for SYNthesis and OPtimization SYStems), and proceeded to commercialize automated logic synthesis via the company’s flagship Design Compiler tool. Without this foundational technology that transitioned chip design from schematic- to language-based, today’s highly complex designs – and the productivity engineers can now achieve in creating them – would not be possible. The advent of EDA enabled engineers to address scale complexity and systemic complexity simultaneously.

Over the past quarter century, Synopsys has grown from that small, one-product startup to a global leader with more than $1.7 billion in annual revenue in fiscal 2012. Early on, Synopsys established relationships with virtually all of the world’s leading chipmakers, and gained a foothold with its first products. Synopsys’ tools quickly broadened to: front-end design including simulation, timing, power and test; system level design to encompass higher levels of abstraction; and physical implementation to address place and route, extraction and increasing manufacturing awareness.

Synopsys established strategic partnerships with the leading foundries and FPGA providers, acquired some early EDA point tool providers, launched more than two dozen products, and completed its initial public offering (IPO) in 1992. Fewer than 10 years after its founding, Synopsys had achieved a run rate of $250 million.

Synopsys began donating to local communities in 1989 and formalized charitable giving in 1992 under the leadership of employee giving committees. In 1999, the Synopsys Foundation and the Synopsys Outreach Foundation were formed, making science and math education and community support initiatives part of their charter.

In the 2000s, Synopsys introduced an integrated design platform that allows customers to take a design from specification all the way through to silicon fabrication. In all of its development activities, Synopsys works closely with customers to formulate strategies and implement solutions to address the latest semiconductor advances.

Growing smarter

Over the years, the company assembled a team with diverse global backgrounds and many decades of combined semiconductor industry know-how. In 2012, Dr. Chi-Foon Chan (Synopsys’ president and chief operating officer since 1998) expanded his role and joined Dr. de Geus as co-CEO. Acknowledging the effectiveness of their longtime partnership and the breadth and complexity of Synopsys’ business, Dr. Chan will help nurture the company through its next phase of growth.

Both in-house technology innovation and strategic acquisitions have driven Synopsys’ success as the company extended beyond its core business to address emerging areas of great importance to its customers. For example, early in the 1990s, Synopsys saw the need to integrate EDA and IP. Today, IP libraries are critically important to design efforts at the chip and system level. Synopsys’ concentration on the IP space has made it the leading supplier of interface IP – essential to today’s many communications standards – and the no. 2 supplier of commercial IP overall.

Synopsys has also been highly effective in creating a successful services offering. The company’s design consultants, focused on understanding customers’ evolving technology challenges, utilize a broad portfolio of consulting and design services to help chip developers accelerate innovation and success for their design projects.

Complementary acquisitions

Synopsys has been an active acquirer of companies to round out and enhance its product portfolio. When making acquisitions, Synopsys focuses on technology that complements organic R&D growth in its core offering or broadens its capabilities beyond traditional EDA.

Synopsys executed two of the largest acquisitions in EDA history: Avant!, with its advanced implementation tools, and Magma Design Automation, whose core EDA products were highly complementary to Synopsys’ portfolio.

A number of acquisitions helped Synopsys build out its IP portfolio over the years, while also recognizing the growing importance of high-level synthesis and embedded system-level design. Early on, Synopsys also saw the trend toward advanced prototyping technology, including virtual prototyping and FPGA-based prototyping for hardware/software co-design.

As challenges associated with analog/mixed-signal (AMS) design escalated, Synopsys enhanced its portfolio with complementary technology to address various AMS design aspects.

Mask synthesis and data prep became important additions to Synopsys’ manufacturing tool offering, as did the development and support of products for the design and analysis of high-performance, cost-effective optical systems.

Each technology advancement or acquisition has built upon the developments that preceded it, adding a new layer of value to the company. Dr. de Geus has a philosophy: If something already has value, how can it be moved to the next level? It was this approach that essentially informed the discovery of how fostering talent, technology and education can yield exciting results that drive ongoing innovation. One can only imagine what future years will hold.


When ARM and CEVA team-up for “Designing a Multi-core LTE-A Modem”

When ARM and CEVA team-up for “Designing a Multi-core LTE-A Modem”
by Eric Esteve on 12-11-2012 at 4:25 am

ARM and CEVA have launched a white paper, addressing one of the hottest topics of the day: LTE-Advanced modem architecture. This very exhaustive paper, written by David Maidment (Mobile Segment Manager, ARM), Chris Turner (Senior Product Manager, ARM) and Eyal Bergman (VP Product Marketing, Baseband & Connectivity, CEVA Inc.) explains how Designing an efficient LTE-Advanced modem architecture with ARM[SUP]®[/SUP] Cortex™-R7 MPCore™ and CEVA XC4000 processors. The title is self-explaining, but having a look at the high level architecture allow to identify which core does what task. The Cortex-R7 does L1 control and L2, L3 processing, when no less than three CEVA-XC4000 DSP cores are in charge of the Layer-1 RX (XC4110 and XC4210) and TX (XC4100 on the right).

This LTE-Advanced Digital Modem Architecture is precisely described in this very comprehensive white paper, as we can see with this more detailed description, showing the AMBA AXI busses, the hardened FFT, Turbo Decoded, XC-DMA, Cipher RoHC, L1 Interrupt Controller, IFFT and DDR Controller functions.

In such a complex, multi-core design, the memory utilization and assignment is a key architecture decision. The table below summarizes both the size and the location (on chip or off chip) of the various memory blocks.

Let’s take a minute to have a look at the LTE penetration forecast for the next 5 years (in red) to be compared with the smartphone shipments (in blue). LTE adoption growth rate is impressive, and the “feeling” can be confirmed by facts (extracted from the white paper):

“The LTE (Long-Term Evolution) standard was first ratified by 3GPP in Release-8 at December 2008 and was conceived to provide wireless broadband access using an entirely packet based protocol and was the basis for the first wave of LTE equipment. LTE has now been adopted by over 347 carriers in 104 countries (Ref GSA) including such territories as USA, Japan, Korea and China to name but a few, making it the fastest adopted wireless technology in history”

And, because the SW development can not be separated anymore from the HW development, the SW mapping is completely described in the article, as we can see per the picture below:

You will find a lot more information by reading the complete white paper, you will find it here.

Eric Esteve from IPNEST


Happy Holidays

Happy Holidays
by Paul McLellan on 12-10-2012 at 3:00 pm

At times of this year, companies usually get their salespeople to submit the names and addresses of all their customers. They then get an expensive card printed and mail it out. What the recipient does is anyone’s guess, from throwing it straight in the bin to using it to decorate the office.

Atrenta decided to do something different this year, and professionally make a holiday video to wish everyone Happy Holidays. But they have customers in so many different countries, that it seemed very boring to do it only in English. So they didn’t. Enjoy (1 minute long).

Oh, and let me add my own greetings. Happy Holidays. Bonnes fetes. 圣诞节快乐。OK, that’s all the languages I can muster. Oh, I do know it in Hawaiian too, having spent Christmas there a couple of times years ago: Mele Kalikimaka.