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Cryogenic Semiconductor Designs for Quantum Computing

Cryogenic Semiconductor Designs for Quantum Computing
by Kalar Rajendiran on 01-16-2024 at 6:00 am
Categories: EDA, Quantum Computing, Siemens EDA

siemens eda quantum crygogenics newsroom 1280x720

Over the last few years, there has been an increase in news about quantum computing. Much of this news coverage has been around computing supremacy, potential threats to information security and quantum cryptography. While the field of quantum computing is still in its early stages, there are several companies who have already developed quantum computers. And these companies often leverage proprietary semiconductor fabrication technologies to build chips for their quantum computers. As such, much information about their semiconductor chips is not publicly disclosed. On top of that, media coverage tends to emphasize practical applications of quantum computing rather than the underlying semiconductor technologies. Achievements like quantum supremacy demonstrations, advancements in quantum algorithms, and industry collaborations often take precedence in news coverage over semiconductor technologies. Nonetheless, quantum computing is not possible without semiconductors that are capable of operating at temperatures near absolute zero. These cryogenic semiconductors are fundamental components of quantum computing systems and a recent announcement by Siemens EDA provides some insights into what is involved in designing these cryogenic chips.

Siemens EDA is collaborating with sureCore and Semiwise to develop quantum computing ready cryogenic CMOS chips. The technologies and solutions developed through this collaboration have the potential to redefine the boundaries of high-performance computing.

Quantum Computing and Cryogenic Chips

Quantum computing relies on quantum bits or qubits, which exhibit quantum mechanical properties such as superposition and entanglement. To maintain the delicate quantum states necessary for computation, qubits must be shielded from external disturbances, such as thermal noise and electromagnetic interference. Operating at cryogenic temperatures helps mitigate these challenges and stabilizes the quantum states, reducing errors and enhancing the reliability of quantum computations. Cryogenic chips are essential for constructing control electronics, enabling the precise manipulation and measurement of qubits.

Semiwise

Semiwise specializes in the development of advanced cryogenic CMOS circuit designs, particularly focusing on technologies that operate at temperatures near absolute zero. The company’s value proposition centers on its expertise in creating cryogenic SPICE models and simulator technology using Siemens’ Analog FastSPICE (AFS) platform. Leveraging these technologies, Semiwise contributes crucial intellectual property (IP) to sureCore, paving the way for the design of CryoCMOS control chips vital for quantum computing.

sureCore

SureCore specializes in low-power memory solutions, with a primary focus on advancing energy-efficient and high-performance integrated circuits. The company’s value proposition lies in its innovative approach to designing and delivering low-power IP cores. In developing its CryoIP product line, sureCore taps into crucial IP from Semiwise. Leveraging cutting-edge technologies, such as Siemens’ Analog FastSPICE platform and Solido™ Design Environment software, SureCore is at the forefront of developing revolutionary CryoCMOS control chips designed to operate in extreme cold conditions. SureCore’s commitment to developing robust cryogenic IP cores tailored for quantum applications positions it as a key player in the race to unlock the full potential of quantum computing while emphasizing energy efficiency and performance in semiconductor design. sureCore is rapidly progressing towards its first CryoIP tapeout, leveraging GlobalFoundries’ 22FDX® PDK.

Siemens EDA

In this announced partnership, Siemens EDA is contributing crucial elements to Semiwise and sureCore to enable the development of cryogenic semiconductor designs. Siemens brings a wealth of expertise to the table, particularly in analog/mixed-signal IC design technology, a cornerstone in the intricate landscape of quantum computing systems. The company’s Analog FastSPICE platform and Solido™ Design Environment software play pivotal roles, providing advanced tools for the design, simulation, and verification of cryogenic CMOS circuits. This enables Semiwise to build accurate and reliable cryogenic transistor models. This in turn is empowering sureCore to construct accurate and reliable analog circuits, standard cell libraries, and memory designs including SRAM, register files, and ROM.

Summary

The collaboration between Siemens, sureCore, and Semiwise marks a significant step forward in the quest for practical quantum computing. By developing cryogenic semiconductor designs capable of operating at near absolute zero temperatures, the partnership aims to overcome critical challenges in realizing the full potential of quantum computing. The technologies developed through this collaboration could reshape the landscape of quantum computing capabilities, opening doors to a broader base of innovators for unprecedented advancements in various industries.

For more information, visit

Analog FastSPICE Platform and Solido Design Environment

Semiwise

sureCore

Also Read:

The GlobalFoundries IPO March Continues

Magnetic Immunity for Embedded Magnetoresistive RAM (eMRAM)

GloFo inside Intel? Foundry Foothold and Fixerupper- Good Synergies

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How Disruptive will Chiplets be for Intel and TSMC?

How Disruptive will Chiplets be for Intel and TSMC?
by Daniel Nenni on 01-15-2024 at 10:00 am
Categories: Chiplet, Foundries, Intel Foundry, TSMC
7 Comments

UCIe Consortium

Chiplets (die stacking) is not new. The origins are deeply rooted in the semiconductor industry and represent a modular approach to designing and manufacturing integrated circuits. The concept of chiplets has been energized as a response to the recent challenges posed by the increasing complexity of semiconductor design. Here are some well documented points about the demand for chiplets:

Complexity of Integrated Circuits (ICs): As semiconductor technology advanced, the complexity of designing and manufacturing large monolithic ICs increased. This led to challenges in terms of yield, cost, skilled resources, and time-to-market.

Moore’s Law: The semiconductor industry has been following Moore’s Law, which suggests that the number of transistors on a microchip doubles approximately every two years. This relentless scaling of transistor density poses challenges for traditional monolithic designs.

Diverse Applications: Different applications require specialized components and features. Instead of creating a monolithic chip that tries to cater to all needs, chiplets allow for the creation of specialized components that can be combined in a mix-and-match fashion.

Cost and Time-to-Market Considerations: Developing a new semiconductor process technology is an expensive and time-consuming endeavor. Chiplets provide a way to leverage existing mature processes for certain components while focusing on innovation for specific functionalities. Chiplets also aid in the ramping of new process technologies since the die sizes and complexity are a fraction of a monolithic chip thus easing manufacturing and yield.

Interconnect Challenges: Traditional monolithic designs faced challenges in terms of interconnectivity as the distance between components increased. Chiplets allow for improved modularity and ease of interconnectivity.

Heterogeneous Integration: Chiplets enable the integration of different technologies, materials, and functionalities on a single package. This approach, known as heterogeneous integration, facilitates the combination of diverse components to achieve better overall performance.

Industry Collaboration: The development of chiplets often involves collaboration between different semiconductor companies and industry players. Standardization efforts, such as those led by organizations like the Universal Chiplet Interconnect Express Consortium (UCIe) for chiplet integration.

Bottom line: Chiplets emerged as a solution to address the challenges posed by the increasing complexity, cost, time-to-market, and staffing pressures in the semiconductor industry. The modular and flexible nature of chiplet-based designs allows for more efficient and customizable integration of chips, contributing to advancements in semiconductor technology, not to mention the ability to multi source die.

Intel

Intel really has capitalized on chiplets which is key to their IDM 2.0 strategy.

There are two major points:

Intel will use chiplets to deliver 5 process nodes in 4 years which is a critical milestone in the IEDM 2.0 strategy (Intel 7, 4, 3, 20A, 18A).

Intel developed the Intel 4 process for internal products using chiplets. Intel developed CPU chiplets which is much easier to do than the historically monolithic CPU chips. Chiplets can be used to ramp a process much quicker and Intel can claim success without having to do a full process for complex CPUs or GPUs. Intel can then release a new process node (Intel 3) for foundry customers which can design monolithic or chiplet based chips. Intel is also doing this for 20A and 18A thus the 5 process nodes in 4 years milestone. This accomplishment is debatable of course but I see no reason to.

Intel will use chiplets in order to outsource manufacturing (TSMC) when business dictates.

Intel signed a historical outsourcing agreement with TSMC for chiplets. This is a clear proof of concept to get us back to the multi sourcing foundry business model that we enjoyed up until the FinFET era. I do not know if Intel will continue to use TSMC beyond the N3 node but the point has been made. We are no longer bound by a single source for chip manufacturing.

Intel can use this proof of concept (using chiplets from multiple foundries and packaging them up) for foundry business opportunities where customers want the freedom of multiple foundries. Intel is the first company to do this.

TSMC

There are two major points:

With chiplets TSMC avoids the M word (monopoly).

Using chiplets customers can theoretically multi source where their die comes from. Last I heard TSMC would not package die from other foundries but if a whale like Nvidia asked them to I’m sure they would.

Chiplets will challenge TSMC and TSMC is always up for a challenge because with challenge comes innovation.

TSMC quickly responded to chiplets with their 3D Fabric comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies. The greatest challenge for chiplets today is the supporting ecosystem and that is what TSMC is all about, ecosystem.

Back to the original question “How Disruptive will Chiplets be for Intel and TSMC?” Very much so. We are in the beginning of a semiconductor manufacturing disruption that we have not seen since FinFETs. All pure-play and IDM foundries now have the opportunity to get a piece of the chips that the world depends on, absolutely.

Also Read:

2024 Big Race is TSMC N2 and Intel 18A

IEDM: What Comes After Silicon?

IEDM: TSMC Ongoing Research on a CFET Process

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation

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How Codasip Unleashed CHERI and Created a Paradigm Shift for Secured Innovation

How Codasip Unleashed CHERI and Created a Paradigm Shift for Secured Innovation
by Mike Gianfagna on 01-15-2024 at 6:00 am
Categories: Codasip, IP
1 Comment

How Codasip Unleashed CHERI and Created a Paradigm Shift for Secured Innovation

At the recent RISC-V Summit, Dr. Ron Black, CEO of Codasip unveiled a significant new capability to create a more secure environment for innovation. Rather than re-writing trillions of lines of code to solve the security problem, Ron described a much more practical approach. One that brought a research topic into mainstream deployment. The results could have far-reaching impact. You can learn about the magnitude of the data security problem and the overall approach Codasip is taking in this RISC-V summary piece. In this discussion, I will dig into some of the details that allowed this innovation to happen. The standard that was developed in the lab, and the road to production that Codasip provided.  Read on to learn how Codasip unleashed CHERI and created a paradigm shift for secure innovation.

The Beginnings of CHERI

CHERI (Capability Hardware Enhanced RISC Instructions) is a joint research project of SRI International and the University of Cambridge to revisit fundamental design choices in hardware and software to dramatically improve system security. CHERI has been supported by DARPA programs since 2010, as well as other DARPA research and transition funding.

CHERI extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization. The CHERI memory-protection features allow historically memory-unsafe programming languages such as C and C++ to be adapted to provide strong, compatible, and efficient protection against many currently widely exploited vulnerabilities. This ability to retro-fit existing systems with higher security is what makes CHERI so attractive – no need for a major re-write to enhance security.

CHERI is a hybrid capability architecture in that it can blend architectural capabilities with conventional MMU-based architectures and microarchitectures, and with conventional software stacks based on virtual memory and C/C++. This approach allows incremental deployment within existing software ecosystems, which the developers of CHERI have demonstrated through extensive hardware and software prototyping.

CHERI concepts were developed first as a modification to 64-bit MIPS and 64-bit ARMv8-A. All of these projects are of a research nature, with the goal of developing a proof-of-concept. While these efforts represent important steps to a commercial solution to the data security problem, a true “industrial strength” solution was out of reach – until recently.

Codasip Delivers a Production Implementation of CHERI for the RISC-V ISA

In mid-October, 2023, Codasip announced the 700 RISC-V processor family, expanding its offering beyond embedded processor IP to stand-alone application processors. In its own words, “bringing the world of Custom Compute to everyone.” The 700 family is a configurable and customizable set of RISC-V baseline processors. It is intended to complement Codasip’s embedded cores by offering a different starting point to accommodate the need for higher performance. And Codasip Studio delivers a streamlined design process that unleashes the potential of the 700 family.

It was against this backdrop that Codasip fundamentally changed the deployment vector for CHERI. Using Codasip Studio, built-in fine-grained memory protection was added to the 700 processor family by extending the RISC-V ISA with CHERI-based custom instructions. To enable the use of these instructions, Codasip also delivered the software environment to take advantage of CHERI technology, bringing a full software development flow to add memory protection.

And because CHERI technology can be applied selectively to critical functions, it is possible to enhance the security of existing products with a small effort, often through a simple code recompilation. This allows the huge pool of existing C/C++ software to be leveraged to create more secure systems cost-effectively. Codasip demonstrated the new CHERI-based security capability at the recent RISC-V Summit, and lead customers will get early access to the core with CHERI capabilities in the second half of 2024.

These developments hold the promise to fundamentally change the landscape regarding data security. This is clearly one to watch. There are places to learn more about this important development. Before I get to those, I’d like to cite a few examples of how CHERI could change data security. At his RISC-V keynote, Ron Black detailed some epic security breaches that have occurred over the years. You may remember some, or all of these:

  • The Heartbleed bug: Introduced in software in 2012 and disclosed in 2014. Huge impact. more than 90,000 devices still not patched in 2019. Estimated cost is over $500 million. This is one of the worst software vulnerabilities of all time.
  • BMW Telematics Control Unit bugs: In 2017, Tencent’s Keen Security found a memory corruption vulnerability in the Technical Control Unit TCU firmware. The researchers could bypass signature protection and gain root access to the TCU via remote code execution​. They could then send crafted Controller Area Network (CAN bus) messages to affect control of other electronic control units in the vehicle.
  • Netgear router hack: In a recent competition organized by the Zero Day Initiative, Claroty’s Team 82 found and exploited a vulnerability in the Netgear Nighthawk RAX30 router. The routers utilize a software protection technique called stack canaries to secure against buffer overflow attacks. The team could bypass the canary. An attacker may surveil your procedures, highjack connections, send you to malicious sites, or embed malware into your ecosystem.

The goal of this exercise was not to cause panic, but to simply point out that ALL of these vulnerabilities were preventable with Codasip CHERI technology.  And that’s why this is an important development to watch and use.

To Learn More

There is a rich library of information about CHERI here.  A press release, a technical paper, several informative blogs and the ability to request more information. I highly recommend spending some time there.  Especially of you are concerned about data security, and who isn’t?  And that’s how Codasip unleashed CHERI and created a paradigm shift for secure innovation.

Podcast EP203: A Deep Dive on the Growing Impact of Silicon Lifecycle Management with Synopsys’ Randy Fish

Podcast EP203: A Deep Dive on the Growing Impact of Silicon Lifecycle Management with Synopsys’ Randy Fish
by Daniel Nenni on 01-12-2024 at 10:00 am

Dan is joined by Randy Fish, Director of Product Line Management for the Silicon Lifecycle Management (SLM) family at Synopsys. Randy has over 30 years of experience in the EDA, IP and semiconductor industries.

In this broad view of SLM, Randy explains what is special about monitoring and optimizing embedded memories. It turns out there are a huge number of these structures in advanced designs and their performance is of critical importance.

Randy and Dan expand the discussion to include broad markets such as data center and automotive. Randy explains the breadth of the Synopsys strategy for SLM that includes many types of embedded monitoring IP, on-chip analytics and use of the cloud. The goal is to deliver optimal performance over the life of the design – an area of increasing importance.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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2024 Outlook with Anupam Bakshi of Agnisys

2024 Outlook with Anupam Bakshi of Agnisys
by Daniel Nenni on 01-12-2024 at 6:00 am
Categories: Agnisys, EDA

Agnisys Company Photo

We have worked with Agnisys for the last two years and it has been a pleasure. Anupam and his team of specification automation experts have pioneered a family of products and solutions for streamlining the generation of the required files for design, software, verification, validation, and documentation for semiconductor development directly from executable specifications. This saves your IP and chip development teams time and effort many times throughout the course of a project. Whenever a specification changes for any reason, all output files are updated, keeping all teams in sync, absolutely.

Tell us a little bit about yourself and your company.
I’m Anupam from Agnisys, a company I formed in 2007, so it’s been 16 years here. Our vision has been to eradicate wastage of time and resources in the
chip design process. Our flagship product suite is called IDesignSpec which
is useful in compiling higher level specifications into highly optimized
code for area, for power, for verification, for firmware, and the list goes
on. The tool helps establish a single source of truth in a company that
keeps everyone in sync from the start. Over the years, we have enabled
hundreds of teams and thousands of engineers to save time and money.

What was the most exciting high point of 2023 for your company?
Its hard to say because there was so much happening in 2023, never a dull
moment! But getting requests for sequences from existing and new customers was the highlight. You see, we had a sequence product in 2019 but it was early for its times. Now we see a renewed interest in sequences thanks to PSS (An Accellera standard that Agnisys helped in creating as well).

What was the biggest challenge your company faced in 2023?
There were several, but two were significant – Power optimization and Clock
Domain Crossings in large circuits. Bigger designs can’t be created with
simple old ways, a concentrated effort has to be made to ensure that power
conformance and CDC handling.

How is your company’s work addressing this biggest challenge?
We solved the challenges by enhancing the functionality of the products.

What do you think the biggest growth area for 2024 will be, and why?
I think it will be the rampant use of AI both in helping create generic
IP/SoC and specialized AI IP/SoC.

How is your company’s work addressing this growth?
We are directly using AI in the core IDesignSpec product as well as in
ancillary areas like Chatbots for help with product usage.

What conferences did you attend in 2023 and how was the traffic?
We exhibited at DAC and almost all DVCon – in US, EU, India, China, Japan.
All were well attended and we had lots of fun. We tried to have a sponsored
event at all these shows.

Will you attend conferences in 2024? Same or more?
We will probably attended more – it’s a great place to meet customers and
show our work. Also it’s a source for new ideas and direction, not to
mention an opportunity to interact with the peers in the industry.

Final comments?
We are just as excited and enthusiastic about our products and services as
we were when we started 16 years ago. We thank our customers for standing by a young startup and seeing it grow into a key EDA player.

Also Read:

An Update on IP-XACT standard 2022

The Inconvenient Truth of Clock Domain Crossings

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?

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CES 2024

CES 2024
by Bill Jewell on 01-11-2024 at 3:00 pm
Categories: AI, Automotive, Events, Semiconductor Intelligence, Semiconductor Services

CES 2024

CES 2024 is being held this week in Las Vegas, Nevada with an estimated 130,000 attendees and over 4,000 exhibitors. CES (previously Consumer Electronics Show) has been held in Las Vegas every year since 1978, except for 2021 due to COVID-19. This was my ninth CES representing Semiconductor Intelligence, with the first in 2012. CES is put on by the Consumer Technology Association (CTA). CTA is 100 years old, beginning in 1924 as the Radio Manufacturers Association. Through the years the name has been changed to Radio-Television Manufacturers Association (1950), Radio-Electronics-Television Manufacturers Association (1953), Electronics Industry Association (1957), Consumer Electronics Association (1997) and the Consumer Technology Association (2015).

A major theme of CES 2024 is AI (artificial intelligence). The CTA Tech Trends session revealed the results of a U.S. consumer survey on AI. The positives were over a third of respondents characterized AI as being innovative and futuristic. However, most respondents were extremely or very concerned about:

  • Privacy – 65%
  • Disinformation – 63%
  • Safety – 60%
  • Job Loss – 59%

Also, 74% of the respondents believed the U.S. government should regulate AI safety.

The significance of AI at CES 2024 is reflected by the number of exhibitors classifying under AI and related categories. Note that companies can be classified under more than one category.

  • Artificial Intelligence                957
  • Smart Home & Appliances        885
  • IoT/Sensors                            818
  • Vehicle Tech                            726
  • Smart Cities                            449
  • Robotics                                 395

The Las Vegas Convention Center (LVCC) was the primary space for CES 2024. The largest area was devoted to Vehicle Tech & Advanced Mobility, which occupied the entire 600 thousand square feet of the West Hall and about another 100 thousand square feet in the North Hall. The companies exhibiting included auto manufacturers (Hyundai, Kia, Mercedes-Benz, and Honda), farm and construction equipment companies (John Deere, Caterpillar, and HDHyundai) and numerous companies supplying components and systems for vehicles. Qualcomm had a large booth pushing its automotive technology.

Most of the North Hall featured the categories of Digital Health, Smart Cities & IoT Sustainability, IoT Infrastructure, and AI/Robotics. The Central Hall featured Audio Video and Gaming. The largest booths in the Central Hall were from Sony, LG Electronics, Samsung Electronics, Panasonic, and TCL Corporation.

The AI theme dominated the major electronics companies press conferences and booths. The theme of Samsung’s press conference was “AI for All”. Samsung sells over 500 million smart devices each year. The emphasis was on tying smart devices together and security. Samsung pushed its televisions as a digital hub for the smart home. It introduced a new line of TVs based on the Samsung NQ8 AI Gen3 processor. Other products introduced included a new version of its Ballie AI robot, new Galaxy Book 4 notebooks, smart refrigerators, and automotive heads-up displays. Interestingly, there was not mention of smartphones, Samsung’s largest sales category.

The numerous products featured at CES 2024 are featured on many media platforms, so I will not try to cover them here. However, there were a few products I found intriguing.

Oorion has an intelligent radar for the visually impaired which will identify and locate objects. It is available as a free app.

DeRUCCI introduced its T11 Pro smart mattress. It uses sensors and air bags to adjust for optimal sleep.

Shooter Detection Systems featured an indoor gunshot detector with acoustic and infrared sensors to identify shots fired within a building and send an alert to building security and police departments.

Caterpillar introduced an electric mining machine to eliminate exhaust emissions in mines.

Olympian Motors showcased its electric cars with retro styling. Its instrument panel uses old fashioned gauges rather than display screens.

WIRobotics demonstrated its WIM wearable mobility device to assist with walking and load carrying.

Numerous robots were on display at CES 2024. Some of the more interesting robots are:

Friendly robot
Creepy robot
Robot dog
Robot coffee maker
Robot coffee and drink server
Robot information/delivery system
Also Read:

CHIPS Act and U.S. Fabs

Semiconductors Headed Toward Strong 2024

Electronics Production Trending Up

Turnaround in Semiconductor Market

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CES 2024 and all things Cycling

CES 2024 and all things Cycling
by Daniel Payne on 01-11-2024 at 10:00 am
Categories: Events
2 Comments

UrbanCross min

From the comfort of my home office I attended CES 2024 virtually this week, and collected all the news for cyclists, and it’s mostly all about e-bikes. The total count of e-bike sales now even outnumber EV car sales worldwide, so that growth trend continues. Some 85% of all bikes sold in China are now e-bikes.

e-bikes

This single category continues to grow in revenue and units shipped, so CES is a popular place to show off the latest in bikes with electric motors, powered by batteries to ease some of the manual peddling burden for commuters, mountain bikers, and cargo bikes.

Topsecret

An urban e-bike with no hubs on the wheels.

Vanpowers

They showed two e-bike styles this year, and have features like: hub motor lock, emergency SOS, vibration detector, real-time GPS tracking, and geofencing.

  • Gravel – UrbanCross

UrbanCross, from Vanpowers

  • Mountain – GrandTeton

GrandTeton, from Vanpowers

Kugoo

An off-road, full suspension e-bike from a vendor that also has e-scooters.

T01, from Kugoo

Ultima

From France with have several e-bikes aimed at commuters.

Multipath Compact Cargo, from Ultima

URTOPIA

A CES 2024 Innovation Award honoree offering four models: Carbon 1s, Carbon 1, Chord, Chord X, Fusion. The carbon frames are unique in that the seat tube doesn’t directly connect to the bottom bracket, rather it’s merged with the seat stays. Carbon is used for the belt-drive, instead of a steel chain, and there’s a built-in display in the stem that even works with Google Maps, Apple Health and Strava, wow. ChatGPT works through Bluetooth to your phone, and there’s also WiFi and GPS. Their e-bike is activated by a ring.

Carbon 1s, fro Urtopia

Himiway

Plenty of segmentation with eight e-bikes: The C1 (kids), C3 (cargo), C5 (motorbike), D5 Pro (off road), D7 Pro (extreme off road), A7 Pro (commuter), X5 Pro (carbon), and X5 Ultra (carbon mountain bike).

C1, from Himiway

Heybike

New for this year is the Hauler model, a cargo e-bike, adding to their line of over a dozen models to choose from.

Hauler, from Heybike

Cyrusher

With almost a dozen e-bike models to choose from, one model that stands out is their fat-tire electric bike.

Hurricane, from Cyrusher

Rictor

Blurring the lines between bike and motorcycle is the K1, as it sports motorcycle tires and shocks, but then adds pedals like an e-bike.

K1, from Rictor

VinFast

With the motor in the rear hub, this DragonFly almost looks like a mini-bike, instead of an e-bike.

DragonFly, from VinFast

Korea Mobility

The KOMO hub-less e-bike from Korea looks like another commuter choice, and they are a 2024 CES Innovation Award honoree.

EH9, by KOMO

 

AIMA

An aluminum frame mountain bike with front suspension and disc brakes was shown.

MA270, from AIMA

HYPER Bike Company

One of the few brands that offers both traditional bikes and e-bikes, with 14 models of e-bikes to choose from, mostly commuter and fat-tire e-bikes.

29in Hyper E-Ride Mountain Bike, by Hyper

Daewon J&B

This South Korean company has some sketchy plans for a hub-less e-bike, so let’s wait for a real product to emerge. The look reminds me of the movie Tron from years ago.

Prototype, from Daewon J&B

MileBox

From Canada comes a cargo e-bike for carrying big loads, along with software to manage a fleet of delivery vehicles.

Movcan

This Chinese company has two off-road e-bikes, the V20 and V30, both looking like a cross between a moped and a motorcycle. Manufactured by Dongguan Shiwei Technology.

V20. from Movcan

Saneagle

With 18 models of e-bikes, this Chinese company has products for: city, commuter, fat cruiser, road, mountain.

ZNH-E-2313, from Saneagle

Greenworks

This Tennessee-based company produces products in multiple categories, and they field five e-bikes for off-road and commuting.

80V Venture Series, from Greenworks

MileBox

From Canada comes a startup that provides an e-bike for hauling cargo, along with the logistics for fleet management of deliveries.

Cargo e-bike, from MileBox

YeScooter

With eight e-bikes to choose from, this Chinese company also offers scooters.

EB23 Mountain e-bike, from YeScooter

Owlet

There are no pedals on this e-bike fro California, and the tube design is unlike any other bike on the road.

Electric Celeste, from Owlet

Kixin

Offering three models of e-bikes, this Chinese company has integrated a display for their bikes.

Q5 Mountain e-bike, from Kixin

KingSong

A hub-powered e-bike with mid-frame suspension, and adjustable height stem and seat.

KS-M3, from KingSong

Smilee

Thirteen models of e-bikes are offered by this vendor, and they have aluminum frames.

E15, from Smilee

Yadea

Two e-bike models with suspension, motorcycle light and fat tires.

Trooper 01, from Yadea

YK Chic

Three models of fat-tire e-bikes hail from this Chinese vendor.

EBA205, from YK Chic

Kopuway

A range of off-road, full-suspension e-bikes, made in China.

Attack 10, fro Kopuway

Segway

The name made famous by self-balancing two-wheel mobility, now has a new e-bike called Xafari.

Xafari, by Segway

Volta

How about a cruiser e-bike from VTA, they mostly offer scooters.

From VTA

FUELL

This step-through e-bike called the Flluid-3 touts a long range battery, suspension, fenders and a rack.

Flluid-3, from Fuell

Trainers

I’ve used indoor trainers from both Wahoo and Garmin (Tacx), where you remove the rear wheel and attach the bike to a smart trainer, then use a fitness app like Zwift to ride virtual courses.

ULTIRACER NEO

Your bike rides on rollers, while being supported by the frame so that you don’t tip over at slow speeds. This produce was a CES 2024 Innovation Award Honoree in the Digital Health category. I first used rollers in the 1970s, and there is a learning curve to stay balanced, especially at slow speeds. Once you get the hang of it, then you steer to keep on track.

It looks like this system has it’s own software, but I’ve never seen it for sale in any of my online or retail bike stores yet.

ULTIRACER NEO from Realdesigntech Co.

Sunny

It looks like a Peloton, yet this company offers 60 models of exercise bikes.

Evo-Fit, from Sunny

LifeSpan

The Ampera is a seat with pedals for desk workers that can charge your devices through a USB-C port or a 15W Qi charging plate, so not something that you put on gym clothes for a workout, rather something used in home and office for light exercise.

Ampera, by LifeSpan

Smart Accessories

Velo.ai

CoPilot is an AI-powered bike light and camera designed to keep cyclists safer on the road.

CoPilot, from Velo.ai

Livall Helmets

Commuters will be seen with the Smart Commuter helmet, as the rear light is higher up and more visible to motorists.

Smart Commuter Helmet L23, from LIVALL

In Charge

Where are you going to charge your e-bike? That’s where In Charge comes in, as they are building up an EV charger network for e-bikes and scooters.

EV charger network, from In Charge

WiPowerOne

Wireless charging for e-cargo bikes, that’s what this Chinese company has developed.

Wireless charging, from WiPowerOne

Garmin

Women can use the new HR-Fit, it’s a heart rate monitor that fits onto medium and high-support sports bras. I sure hope that swapping batteries doesn’t require using a miniature Torx screwdriver like on previous models, as the threads tend to strip out.

 

HR-Fit, from Garmin

Sennheiser

Earbuds that also track heart rate and body temperature, OK, that’s unique, but I recommend that cyclists not be distracted with earbuds while on the road for safety reasons.

Momentum Sport, by Sennheiser

MindMics

Similar to Garmin, MindMics has an earbud with heart rate monitoring feature, plus they are a CES 2024 Innovation Awards honoree.

MindMics Heart Health System

Safeware

Modern cars have airbags and they save many lives, so why not do something similar for cyclists? Safeware has a wearable airbag that looks like a vest, and they are a CES 2024 Innovation Awards Honoree.

 

Personal Mobility Airbag Vest, by Safeware

Qualcomm

The Snapdragon Digital Chassis SoCs give e-bikes connectivity, infotainment, advanced rider assistances systems (ARAS) and personalized cloud-connected digital services.

Snapdragon Digital Chassis SoCs, by Qualcomm

Valeo

Placing both the electric motor and gears inside the same gearbox is what the Cyclee from Valeo does, so no more derailleurs for an e-bike.

Cyclee, from Valeo

Bosch

The electric motor is central to all e-bikes, and that is where Bosch comes in, as they sell the drivetrain to e-bike companies, like: Riese & Muller, Gazelle, Trek, and Tern.  Editors at Wired did test rides outside of several e-bikes at Red Rocks Canyon National Conservation Area.

Active Line Plus, from Bosch

Summary

I still ride a traditional road bike, however more of my buddies are buying e-bikes for their spouses and parents. As I cycle around the Portland, Oregon area I’m seeing more e-bikes in all flavors: commuter, fat-tire, mountain, road, cargo. The e-bike revolution just keeps growing, with all of the traditional bike brands (Specialized, Trek, Cannondale, Fuji, Canyon) adding electric models, and new entrants emerge that have no bike history.

Follow my cycling adventures on Strava, or in virtual reality on Zwift (Daniel Payne, 66), better yet, let’s go for a ride together.

Related Blogs

 

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Synopsys Geared for Next Era’s Opportunity and Growth

Synopsys Geared for Next Era’s Opportunity and Growth
by Kalar Rajendiran on 01-11-2024 at 6:00 am
Categories: AI, Chiplet, EDA, Emulation, IP, Prototyping, Synopsys

SassineGhazi

As semiconductor industry folks know, Synopsys is a behemoth of a company. At $5.84B in FY2023 revenue (FY Nov-Oct), approximately 20,000 employees and a market cap of about $74B, it leads the silicon-to-systems design solutions space within the industry. From humble beginnings in 1986 as a disruptive startup, the company has grown into a skyscraper of success, revolutionizing the industry through continual innovations and expanding its value to all stakeholders. Naturally, it is big news when Synopsys changes CEO after 37 years of stewardship by the founding CEO Aart de Geus. Aart and the Synopsys Board have entrusted the company with Sassine Ghazi to lead it successfully through the next era and beyond.

Prior to his CEO role, Sassine was President and COO, responsible for leading all business units, sales and customer success, strategic alliances, marketing and communications at Synopsys. On his first day as CEO of Synopsys, Sassine communicated his enthusiasm for the unprecedented opportunity ahead, in a memo to stakeholders. Those who read the memo would fall into two broad categories. Those within the first category are the ones who implicitly trust in the astute choice of Sassine as CEO. And those within the other category are the ones who would additionally want to explore the skyscraper’s foundation and understand its structural strength for the next era’s journey.

As Sassine’s memo stated, a paradigm shift is clearly underway to deliver on the era of pervasive intelligence and interconnectedness. Riding paradigm shifts to growth is nothing new to Synopsys.

Let’s first look at how Synopsys has successfully ridden past paradigm shifts to bring more value to the industry and grow the company. We will also look at additional innovations that the company is continually investing in to help it ride the next paradigm shift that is upon the industry. Together, this review should help highlight the foundational and structural strength of the company to scale efficiently and deliver ambitious and sustainable growth.

Leveraging Paradigm Shifts is Innate to Synopsys

The following are some major shifts that Synopsys has capitalized on to grow  the company and its value to stakeholders.

“HDL Design” paradigm shift

When gates level description and netlists were the mainstream approach for designing chips, Synopsys pioneered the HDL design approach through synthesis solutions. Synopsys disrupted the market with the first timing-driven logic synthesizer and soon after established itself as a formidable player in the design synthesis segment. From that beachhead, the company expanded its innovative solutions space to address more aspects of a chip design process. Fast-forward and Synopsys quickly grew to be a comprehensive EDA solutions company.

“IP-based Design” paradigm shift

As non-modular design approach started giving way to IP-based and modular design approach, the company started investing in IP DesignWare library. The library started with basic IP but soon expanded to include higher-level IP such as processor cores, security IP, interconnects and more. Soon after, Synopsys became a significant player in the third-party IP market segment. The company becomes an EDA+IP company from its prior classification as just an EDA company.

“Network is the Computer” paradigm shift

The famous tag line “Network is the Computer” is attributed to Sun Microsystems and reflected its vision of network-centric computing paradigm, emphasizing the importance of interconnected systems and network infrastructure. In this vision, the network is the critical component, enabling collaboration, data sharing, and distributed processing. Synopsys capitalized on this paradigm shift by innovating and delivering an extensive portfolio of interconnect IP solutions. The company also delivered security and software testing solutions and became known as the Silicon to Software company.

“Multi-die Systems” paradigm shift

As Moore’s law benefits started to slow down, system performance demands started increasing in leaps and bounds. It became clear that Multi-die systems are essential to address the system demands of modern day applications. Synopsys quickly capitalized on this shift by delivering innovative solutions such as its Fusion Design Platform™ which includes the 3DIC compiler.

Synopsys’ Silicon-to-Systems Approach

As reviewed above, the company has grown from its early roots as a design synthesis company into a silicon-to-systems design solutions company. The silicon-to-systems approach in semiconductor design represents a comprehensive and integrated methodology that encompasses the entire spectrum of designing electronic systems. It addresses everything starting from fundamental building blocks of silicon devices to complete system-level integration and unified design verification through the ZeBu Server 5 solution.

Next Paradigm Shift

In the realm of Artificial Intelligence (AI), an “AI network” encompasses various meanings depending on the context in which it is used. It commonly refers to neural networks for tasks like image recognition and machine learning. Alternatively, in the context of distributed computing, AI networks may denote cloud-based systems utilizing extensive computational resources for training and deploying AI models. The term can also extend to AI-powered networks in applications, such as social networks employing algorithms for content recommendation. Additionally, it may refer to collaborative AI networks where interconnected systems work together towards common objectives or in the domain of cybersecurity, where AI is applied for threat detection and network security enhancements. The multifaceted nature of “AI network” underscores its diverse applications across various technological domains.

I’d like to coin the tag line “AI Network is the Consumer” to denote the paradigm shift that the industry is facing now. The AI Network is the consumer, so to speak, driving new architectures, design methodologies, IP and silicon proliferation. The semiconductor industry is expected to double in market value to one trillion dollars or more by the end of the decade. A significant portion of this projected growth is being attributed to this paradigm shift.

Synopsys.ai

Synopsys is increasing its investments to address its silicon-to-systems approach with heightened focus on pioneering AI in chip design. Synopsys.ai is the company’s overarching AI initiative and most recently, the company launched Synopsys.ai Copilot. – you can read about both in this SemiWiki post.

Summary

Synopsys revolutionized the process of designing semiconductors and will continue to do so. This is part of the action-oriented company culture that Aart has inculcated into the company DNA. Sassine radiates this culture with several innovative solutions having been launched under his prior leadership roles. I can vouch for Sassine’s passion for collaboration and innovation based on a couple of dinner conversations with him on various topics in technology and innovation.

Looking forward to Sassine leading Synopsys to capitalize on the next paradigm shift, deliver innovative solutions, enhance value to all stakeholders and grow the company.

Also Read:

Automated Constraints Promotion Methodology for IP to Complex SoC Designs

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

Synopsys.ai Ups the AI Ante with Copilot

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An Accellera Functional Safety Update

An Accellera Functional Safety Update
by Bernard Murphy on 01-10-2024 at 10:00 am
Categories: Accellera, Automotive, Semiconductor Services

Fusa interoperability min

In May of 2021 Accellera released a first white paper on the challenges they hope to address with their functional safety standard, together with the scope and goals they set for themselves. One major goal in this effort has been exchange and integration of functional safety data between different tools and flow and particularly between different layers of the supply chain, e.g. between IP, EDA and semiconductor suppliers. Another strongly related goal has between to ensure traceability of functional safety data for purposes of correctness, completeness, and consistency validation. More recently Accellera released a second white paper, informally describing their progress towards these goals.

Recap – why do we need a new standard?

The well-known ISO 26262 and IEC 61508 standards describe what needs to be accomplished to meet a defined level of safety but without much description of how it should be accomplished. This proves to require a significant effort in supply chains when building safe products depends critically on collaboration between different vendors in the supply chain.

The most obvious deficiency is the lack of a standard for exchanging FMEDA data (failure modes, effects, and diagnostic analysis). This data is central to understanding what failure modes have been considered and what level of coverage analysis and safety mitigations ensure against those failures. All of these are central to what an IP supplier promises, EDA tools measure, a semiconductor supplier commits to their customers and the Tier1/OEM need for their own safety analysis.

Lack of interoperability between these levels has forced supply chain players to depend on trust and natural language documentation to ensure compliance with expected requirements. Clearly a machine-interpretable standard would be superior for automated analysis. Alessandra Nardi, chair of the Accellera functional safety working group, tells me that the initial push to get a standard ratified has started with IP and semi vendors but she is expecting in time to get more feedback from Tier1s and OEM (particularly I would guess as they are also getting closer to semi design).

Goals for the second white paper

According to Alessandra, this white paper describes the approach the working group has taken to develop the data model, which becomes the foundation for the Accellera functional safety standard. This begins with formalizing the process of performing an FMEDA as a first step towards common understanding among the participants. In the second step they describe the resulting data model, reflecting the requirements of building an FMEDA. The final step will be to derive a language from the data model. This last step is currently only in sample draft in the annexes of the white paper and remains open for further development among the working group.

From my perspective the white paper is a necessarily lengthy but quite exhaustive description of requirements, between intra-layer interoperability (between different functions say in semiconductor design development) and inter-layer considerations (for example between IP and semiconductor layers). They describe in some detail the flow in developing an FMEDA and how failure modes, safety mechanisms and technology elements are mapped and connected in a representative design.

How close is this standard to release?

As mentioned above, the functional safety language is still in development though the white paper offers a sample language to illustrate how a tool or user might interact with the model. Alessandra sees the next steps as validating the data model with a wider audience (I assume, since this is now a public white paper) and finalizing the language into a language reference manual (LRM). She hopes to see that out some time in 2024.

You can read the detailed white paper HERE.

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Analog Bits Enables the Migration to 3nm and Beyond

Analog Bits Enables the Migration to 3nm and Beyond
by Mike Gianfagna on 01-10-2024 at 6:00 am
Categories: Analog Bits, IP

Analog Bits Enables the Migration to 3nm and Beyond

The world is abuzz with 3nm and 2nm technology availability. These processes offer the opportunity to pack far more on a single die than ever before. The complex digital systems contemplated will bring new AI algorithms to life and much more. But there is another side of the technology migration story.  With all that digital processing comes the need for things like I/Os, sensing, power management and high-speed comms. These are functions delivered by analog IP, and all that must be available on advanced nodes to realize the true monolithic integration opportunity. Analog IP often doesn’t work well at advanced nodes, however. This is a story of how one company isn’t just solving the problem. It is expanding the options at 3nm and beyond to create new paths for new ideas. Read on to see how Analog Bits enables the migration to 3nm and beyond.

The March to 3nm

Analog Bits has a huge catalog of IP that enables all kinds of systems. Billions of units shipped across 1,000+ deliveries since 1995 – an impressive statistic.  The company has a long track record of developing critical analog IP across all the top foundries. A little less than two years ago the company was purchased by SEMIFIVE, but the focus and direction of Analog Bits remained the same. You can get more of the backstory on SemiWiki here.

The Analog Bits IP portfolio spans clocking, sensors, I/Os, and SerDes. In the sensor area, on-die LDOs help with power efficiency and power management, a vexing problem for advanced designs. Here is a top-level summary of the portfolio, there is a lot more detail available here.

Clocking

  • PCIe clock PHY IP
  • High performance C2C PLL
  • Digital Core Power PLL
  • Wide-range, low power PLL
  • Ultra low jitter LC PLL
  • Sub-micro watt IOT class PLL
  • High reliability radiation tolerant PLL

Sensors

  • Digital Core Power
  • Bandgap Generator
  • System Power Detector
  • PVT Sensor
  • Power on Reset with Brown-Out Detect
    • Power Glitch Detector
    • ADC
    • LDO

I/Os

  • Differential clock TX/RX
  • PCIe – HCSL clock drivers
  • C2C IO’s Single Ended IO
  • Low noise/power crystal oscillators
  • Lowest Power OSC pads for IoT
  • FPGA class multi-programmable IO
  • Voltage tolerant IO buffers
  • DDR IO’s

Multi-Rate, Multi-Protocol SERDES

  • Lowest power (4pj/bit @ Gen3 & 6pj/bit @ Gen4)
  • Low latency – 3/4 UI between parallel and serial Tx/Rx
  • Smallest area – 0.1 sq.mm (Gen3) & 0.26 sq.mm (Gen4)
  • Programmable for different channel environments

Of course, all this IP must be available on 3nm to facilitate the move to that node, and Analog Bits has a strong story here. The figure below drives home the point. Analog Bits is a critical enabler for 3nm designs.

Analog Bits Foundry Coverage

What’s Next

There is plenty more in the works at Analog Bits beyond 3nm. That detail will be part of future posts. There is one rather key point worth mentioning now, however.  Back in 2021, the company announced a novel new, patented IP architecture called Pinless Technology. To minimize power distribution overhead, IP was developed that worked off the core voltage of the chip. This means there is no longer a need to route a different voltage to internal IP since the core voltage is everywhere.

While this style of IP is very useful in 3nm, it takes on a different value at the next node. As we move below 3nm to gate-all-around architectures there will be only one gate oxide thickness available to support the core voltage of the chip. Other oxide thicknesses to support higher voltages are simply no longer available.

In this scenario, the Pinless Technology invented by Analog Bits will become even more critical to migrate below 3nm as all of the pinless IP will work directly from the core voltage. I can’t wait to see how the impact of this innovation shapes the future. And that’s how Analog Bits enables the migration to 3nm and beyond.