Chiplets dominate semiconductor industry conversations right now – and after the recent Chiplet Summit, we expect the intensity to go up a couple of notches. One company name often heard is Blue Cheetah, and we had the opportunity to sit down with them recently to discuss their views and their just-announced design win at Tenstorrent. Their ideas on getting from chiplet specifications to chiplet ecosystems recall familiar industry dynamics with engineering and marketing working together in adoption cycles.

Two frequently-mentioned chiplet interconnect specs

Instead of a massive, complex, single-die SoC, chiplets are smaller pieces designed, fabbed, and tested independently, maybe in different process nodes, then packaged together in a bigger solution. In theory, chiplets would be reusable and interoperable. Designers could grab a chiplet without concern for what fabrication process made it or gory details we’ll see shortly, as long as the chiplet complies with a broadly adopted die-to-die (D2D) interconnect specification. Two specification candidates have bubbled to the top of the heap: BoW and UCIe.

Significant differences exist between these two specifications regarding their design philosophies, primarily driven by the types of chiplet use cases they aim to support. BoW focuses on optimizing disaggregated SoC designs with the most efficient die-to-die interconnect across a broad range of end product applications; achieving all of this requires a significant degree of flexibility in the specification. UCIe, on the other hand, focuses on plug-and-play interconnectivity and primarily aims to streamline interoperability between chiplets from any supplier.

There are some commonalities. UCIe and BoW define clock-forwarded, single-ended parallel links; this basic architecture has quickly arisen as the dominant approach for die-to-die interconnects (compared to short-reach serial link or SerDes-based approaches, which are typically differential with an embedded clock). Here are abbreviated descriptions of the two specifications – both of which have definitions suitable for either standard (organic laminate) or advanced packaging technologies:

• UCIe, Universal Chiplet Interconnect Express, defining 1) a PHY layer with unit element modules whose shoreline footprint, arrangement rules, and basic structure (such as the number of signals per module) are defined based on package type, 2) a D2D adapter coordinating link states, retries, power management, and more, and 3) a protocol layer supporting CXL and PCIe traffic.
• BoW defines PHY unit elements as 8- or 16-bit “slices” that can be flexibly combined and arranged to meet a given design’s bandwidth/footprint needs. Rules specify the arrangement of these slices, but the shoreline occupied by each slice, how many slices are stacked (increasing the shoreline bandwidth density, but typically requiring additional routing resources in the package), and whether/how many sideband resources to include are parameters that chiplet / chiplet interconnect designers can tailor to their needs. BoW further defines a link and transaction layer that provides error protection (via forward error correction), flow control, packetization, and, most importantly, mechanisms enabling any on-die bus/network-on-chip (NoC) protocol (and the specific versions/variants thereof) for transport by the die-to-die subsystem (link layer + PHY).

Blue Cheetah recognized early on that building efficient yet robust parallel die-to-die interfaces would require a particular set of circuit optimizations and a high degree of configurability to match the targets of any given chiplet product/design. They set out to develop a clean-sheet architecture for power, performance, area, and robustness-optimized links. Proprietary generator technology provides rapid configurability of their IP for customizing solutions to application requirements, including packaging type, data rate, orientation, I/O configuration, bus protocols/protocol variants, and more.

The decision to create efficient, configurable interconnect solutions readily adaptable for BoW or UCIe is now paying off. “We believe we have more D2D interconnect designs in flight than any other company right now,” says John Lupienski, VP of Product Engineering at Blue Cheetah. “We’re often connecting between multiple chiplet partners, which gives us an advantage in fostering collaboration.”

Accelerating adoption with chiplet ecosystems

Lupienski suggests three distinct chiplet use cases that explain what is happening in the market. The first is single vendor die disaggregation, breaking a (putatively monolithic) SoC into chiplet designs, concentrating on incremental value add where needed. Moving to a next-generation part may involve replacing only some subset of the chiplets and modifying the package. However, by definition, these are walled gardens where that one vendor controls all chiplets and all aspects of their design. (HBM memories are a notable exception in the otherwise single vendor model since they source from memory manufacturers and, as of today, are the sole exemplar of a “plug and play” chiplet.)

The use case often most discussed and implicitly or explicitly envisioned is a fluid market where firms design chiplets that interoperate flawlessly with any other vendors’ chiplets and are available to anyone. But in practice, a third use case is taking shape: chiplet ecosystems where multiple vendors jointly plan and execute chiplet product roadmaps. In contrast to the plug-and-play vision, these ecosystem chiplets are developed with more targeted scope/functionality and (typically) in partnership with other vendors participating within the same ecosystem.

Tenstorrent (helmed by Jim Keller, who has architected and/or led many highly influential processor/SoC designs) is setting up just such an ecosystem and has selected Blue Cheetah to help make it happen. SoC designers typically have an intimate understanding of how design decisions related to factors like floorplanning, subsystem partitioning, and on-die bus/NoC protocols will influence monolithic designs but might not yet have the experience to know what to consider when chiplets enter the mix.

Blue Cheetah has deep expertise and roots in chiplets. Their team includes Sehat Sutardja – credited with introducing chiplets in his 2015 ISSCC keynote – and Weili Dai as Blue Cheetah’s founding investors. Elad Alon, the company’s CEO and co-founder, is the technical lead of the BoW working group and has worked with many of the companies pioneering chiplets and chiplet ecosystems. Blue Cheetah knows what works, where the pitfalls exist, and how to help Tenstorrent and its ecosystem partners navigate AI and RISC-V chiplet design.

Navigating chiplet technology and economics

Customizable, standards-based D2D interconnects with fair-market licensing from Blue Cheetah in multiple ecosystems should make chiplets attractive to more firms. “Smaller chiplet firms going it alone face technology and economic risks while searching for critical mass,” adds Ronen Shoham, VP of Product Management at Blue Cheetah. “We’re helping create multiple ecosystems with companies including DreamBig Semiconductor, FLC Technology Group, Ventana Microsystems, and, as recently announced, Tenstorrent. The approach allows vendors to focus on capturing their core innovations as a chiplet and source other components from third parties whose expertise lies in those other areas.”

Navigators fill vital roles in technology adoption. It’s the right time for a push from those with real-world chiplet experience – we look forward to hearing more from Blue Cheetah.

See more about the Tenstorrent / Blue Cheetah chiplet ecosystem:
Tenstorrent Selects Blue Cheetah Chiplet Interconnect IP for Its AI and RISC-V Solutions

For more information on Blue Cheetah technology, please visit:
https://www.bcanalog.com/