CEVA Dolphin Weninar SemiWiki 800x100 260419 (1)
Semiconductor Expert Forum

Posted on

CEO Interview with Dinesh Bettadapur of Irresistible Materials

CEO Interview with Dinesh Bettadapur of Irresistible Materials
by Daniel Nenni on 03-12-2025 at 10:00 am
Categories: CEO Interviews

D. Bettadapur photo IM

Dinesh Bettadapur serves as the Chief Executive Officer of Irresistible Materials Ltd. Dinesh has over 20 years of executive management experience in the semiconductor industries and has held significant leadership roles encompassing general management, P&L management, sales, business development, strategic alliances, and operations. He has worked at industry leaders such as ASML, Intel, and Lam Research as well as multiple Silicon Valley startups and led them toward a significant degree of business growth including 3 successful exits.

Tell us about your company?

Irresistible Materials is an innovative electronic materials company that has developed a novel EUV resist material to help meet the unique and significant challenges of EUV lithography. It was founded in 2010 as a spinoff from the University of Birmingham and has developed other production worthy materials such as spin-on carbon for hardmasks and e-beam resists. But we are now purely focused on the development and commercialization of our high-performance EUV resist, which is called Multi-Trigger Resist (MTR™) and represents a new class of resist material.

Our MTR platform has been designed from the ground up specifically for EUV lithography, and addresses the limitations of legacy resist materials. It is up to two times faster than competing resists, which has the potential to result in annual cost-of-ownership (CoO) savings of approximately US$10-15 million per EUV scanner operating in a production fab.

Our team is a multi-disciplinary team comprised of world-class technologists with significant industry experience and strong academic background in multiple disciplines, including chemical engineering, lithography, material science, and synthetic chemistry.

What is the vision and strategy for the company?

Our vision is to be the pre-eminent supplier of EUV resist materials to the semiconductor industry through the market adoption of our innovative MTR photoresist platform. Our strategy is to collaborate closely with our customers across the industry’s leading integrated device manufacturers (IDMs) and foundries and offer customized resist materials to address their unique needs. In addition, we intend to strengthen our existing partnerships with key players in the ecosystem while also establishing a set of new partnerships. We are also taking a solution-oriented approach to ensure that our resist material becomes a plug-play material within the overall EUV lithography process.

What problems are you solving?

We are addressing the unique challenges and requirements of EUV lithography (both low NA and High NA). Traditional photoresists like chemically amplified resists (CAR) and metal oxide resists (MOR) cannot fully meet the requirements for higher resolution, low defectivity, and improved throughput. The need for specialized EUV photoresists will only become greater as chip manufacturers push the limits of EUV lithography to further reduce the size of chip feature sizes. Specifically, we are developing novel formulations of our resist material that can meet the key requirements of absorbance, defectivity, etch resistance, line width roughness (LWR), resolution, and sensitivity. There are multiple tradeoffs that have to be made in order to balance all of these requirements in order to generate optimum resist formulation.

What application areas are your strongest?

Our EUV resist material is highly applicable across both logic and memory devices as well as patterned layers corresponding to FEOL and BEOL processes (lines & spaces, contact holes, pillars, etc.).

What does the competitive landscape look like and how do you differentiate?

Our main competitors are those offering CAR and MOR resists. Our MTR technology is a new approach that combines the best of both worlds with additional unique features, which has the potential to offer the highest levels of performance. It uses a catalytic mechanism based on a photoacid generator similar to a CAR and is an organic compound, which makes it compatible with existing track solutions. But unlike a CAR, it is a controlled catalytic reaction based on unique proprietary molecules, which significantly limits or eliminates the acid diffusion resulting in high sensitivity and low LWR. Similar to MOR, it is a small molecule with high opacity, which delivers high resolution. But unlike a MOR, it is non-metallic and avoids metal contamination issues in the fab. Above and beyond all of this, it is a faster resist compared to both CAR and MOR and therefore offers the potential for significant CoO savings in a production fab. Finally, it is PFAS/PFOS-free, which makes it very environmentally friendly.

What new features/technology are you working on?

Broadly speaking, there are two categories of features and capabilities we are working on. The first category is related to improved formulations that can meet the specific short-term needs of customers. Examples of these are higher resolution (tighter pitches), lower linewidth roughness (LWR), and minimizing defectivity.

The other category is related to developing brand new formulations that can address medium-term and long-term industry needs. Examples of these are better delay tolerance, improved process compatibility, and higher absorption/depth of focus (particularly for high-NA EUV).

How do customers normally engage with your company?

Customers will typically ask us to provide a resist sample for testing based on a set of target performance requirements (e.g., resolution, LWR, sensitivity), operating conditions (e.g., bake temperature, post exposure delay) and the target pattern (e.g., lines and spaces, contact holes, pillars). We will then come up with an appropriate custom formulation, which is aimed at meeting their target requirements and perform internal testing before delivering it to the customer. Based on their testing, the customer may ask us to tweak the formulation for further optimization of one or more parameters. Once the customer is satisfied that our formulation meets their key requirements, they will move on to the next phase of material qualification which can eventually lead to a specific material becoming selected as a process of record (POR) material in preparation for high volume manufacturing (HVM).

Contact Irresistible Materials 

Also Read:

CEO Interview with Pierre-Yves Lesaicherre of Finwave CEO

CEO Interview with Matt Desch of Iridium

CEO Interview with Mike Noonen of Swave Photonics

Posted on

RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs

RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs
by Jonah McLeod on 03-12-2025 at 6:00 am
Categories: IP, RISC-V

Security Article Intro ART

Because of its open and modular nature, RISC-V has faced recognizable security challenges stemming from fragmentation, performance inefficiencies, and inherent vulnerabilities. Fragmentation across implementations leads to inconsistencies, making it difficult to enforce uniform security measures. Performance inefficiencies can introduce timing side-channel attacks, where attackers exploit execution time variations to extract sensitive data. Additionally, security vulnerabilities such as Jump-Oriented Programming (JOP) attacks and buffer overflow exploits have demonstrated RISC-V-based systems weaknesses. Addressing these risks has been a crucial focus in the ongoing development of the RISC-V Privileged Specification and supporting architectural innovations.

Recent Architectural Innovations

RISC-V’s privileged specification has faced challenges related to fragmentation, performance inefficiencies, and security vulnerabilities—factors that impact OS support, virtualization, and memory protection. However, recent progress in the RISC-V Privileged Specification has addressed many of these issues, bringing it closer to the robustness of proprietary ISAs like ARM and x86. In parallel, new architectural innovations are further strengthening RISC-V’s capabilities by introducing improvements in memory management, scheduling, and execution efficiency.

As of March 6, 2025, the RISC-V Privileged Architecture Specification version 1.13 has successfully completed its public review process and has been ratified. The 30-day public review period, which started on September 3, 2024, and concluded on October 1, 2024, allowed stakeholders to provide feedback and suggest improvements. Following this review, the specification underwent necessary revisions and was officially ratified. This ratification marks a significant milestone in addressing previous challenges related to fragmentation and security vulnerabilities within the RISC-V ecosystem. With a more stable foundation for operating system support, virtualization, and memory protection, the updated specification enhances RISC-V’s position in modern computing.

Connections Between v1.13 and Recent Patented Innovations

The RISC-V Privileged Architecture Specification v1.13 introduces refinements to privilege levels, memory protection, hypervisor support, and exception handling to strengthen security and performance. One of the most significant refinements in v1.13 is improvements to Hypervisor Mode (H-Mode), which enables more efficient virtual machine (VM) scheduling and reduces execution delays in privileged mode. A related patented innovation, Time-Based Scheduling for Extended Instructions, enhances this feature by optimizing how privileged instructions are scheduled, ultimately reducing context-switch latency. The direct connection between these two advancements is clear: while v1.13 provides the foundation for better hypervisor management; time-based scheduling ensures that hypervisor instructions execute more efficiently. A hypervisor running on a v1.13-compliant RISC-V processor would benefit from reduced instruction stalls and improved VM performance, allowing for smoother virtualization workloads.

Another area where v1.13 and recent innovations align is in memory protection. The specification expands Physical Memory Protection (PMP) and refines virtual memory management to improve access security. Together, these improvements ensure that while v1.13 enforces stricter security policies for memory access, load prediction ensures that privileged memory operations execute efficiently within those constraints. This is particularly important for real-time operating system (OS) environments and security-sensitive applications, where low-latency memory access is crucial to performance and stability.

Additionally, v1.13 introduces refinements to Machine Mode (M-Mode) and Supervisor Mode (S-Mode) execution, making privileged execution more predictable and structured. These updates align with another patented innovation, Out-of-Order Execution for Loop Instructions, which allows the CPU to process system-critical loops more efficiently. The v1.13 spec defines the rules for privileged execution, while out-of-order execution enhances performance within those guidelines. A v1.13-compliant OS kernel running on a CPU that implements out-of-order execution will experience faster privilege mode loops, reducing interrupt handling delays and improving overall system efficiency.

Enhancing RISC-V Performance with Architectural Innovations

Beyond the advancements in the privileged specification, recent patented innovations are further strengthening the RISC-V ecosystem. These enhancements improve memory efficiency, scheduling, and overall execution performance, providing the level of system protection currently enjoyed by proprietary ISA offerings. One such advancement is Time-Based Scheduling for Extended Instructions, which optimizes execution timing for complex privileged instructions. This mechanism ensures smoother operating system performance and reduces bottlenecks in system-level task execution. By lowering the latency in context switching between guest virtual machines, hypervisors can operate more efficiently, leading to better virtualization performance.

The RISC-V Privileged Specification defines a hierarchical privilege model that supports different execution environments. The figure below illustrates the layering of these privilege levels, including OS, SBI, and hypervisor support.

The RISC-V Privileged Specification defines a hierarchical privilege model that supports different execution environments. The figure below illustrates the layering of these privilege levels, including OS, SBI, and hypervisor support.

The introduction of Out-of-Order Execution for Loop Instructions has also significantly improved OS-level and hypervisor performance. This enhancement allows loop instructions to execute non-sequentially, making privileged task handling more efficient. Context switching and interrupt processing benefit greatly from this approach, as it minimizes execution stalls and increases hypervisor responsiveness.

Conclusion

By combining the ratification of the RISC-V Privileged Specification version 1.13 with architectural innovations in memory management and execution efficiency, RISC-V is making significant strides in overcoming past limitations. These advancements position it as a more competitive alternative to proprietary ISAs, paving the way for wider adoption in high-performance computing, cloud infrastructure, and secure enterprise environments.

Also Read:

Harnessing Modular Vector Processing for Scalable, Power-Efficient AI Acceleration

An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2

Relationships with IP Vendors

Posted on

CEO Interview with Pierre-Yves Lesaicherre of Finwave Semiconductor

CEO Interview with Pierre-Yves Lesaicherre of Finwave Semiconductor
by Daniel Nenni on 03-11-2025 at 10:00 am
Categories: CEO Interviews

Pierre Yves

Tell us a little bit about yourself and your company. 
I am the CEO of Finwave Semiconductor and joined the company in June 2023. I have close to 40 years of experience in the semiconductor industry, and I have worked in France, Japan and the United States. I have been in Silicon Valley for the last 27 years. After 14 years at Philips Semiconductors and NXP, rising up to the executive level, I was the CEO of Lumileds, one of the leading LED companies, for 5 years, and then the CEO of Nanometrics, a Nasdaq-listed semiconductor equipment company, for 2 years.

Finwave Semiconductor is a fabless semiconductor company, born out of MIT research, developing and commercializing proprietary GaN-on-Si technology for the RF communications market. Working with foundry partners in the U.S. and Taiwan, and utilizing the Finwave proprietary epitaxial structure, process technology and device architectures, we manufacture and commercialize high-power RF switches and RF power amplifiers for the cellular handset, telecom infrastructure and aerospace and defense markets, among others.

What was the most exciting high point of 2024 for your company?

The key highlight for Finwave Semiconductor in 2024 was the signing of a strategic technology development and licensing agreement with GlobalFoundries (GF), the world’s leading specialty foundry with a rich history of RF leadership. This partnership merges Finwave’s cutting-edge GaN-on-Si technology with GF’s US-based high-volume manufacturing capabilities and long legacy of RF innovation. The collaboration is focused on optimizing and scaling Finwave’s innovative enhancement-mode (E-mode) MISHEMT technology to volume production at GF’s 200mm semiconductor manufacturing facility in Burlington, Vermont. Finwave’s advanced 200mm GaN-on-Si E-mode MISHEMT platform, which was presented in a technical paper at the CS Mantech industry conference in May 2024, offers exceptional RF performance, delivering excellent gain and efficiency at sub-5V voltages, while ensuring high uniformity across 200mm wafers. Leveraging Finwave’s technology, GF’s comprehensive 90RFGaN platform will deliver high-power density and efficiency, enabling high-performance, optimized devices that save on footprint and cost. This partnership presents a compelling solution for high-efficiency power amplifiers in applications where traditional GaAs and Si technologies fall short, including new higher frequency 5G FR2/FR3 bands, 6G and mmWave amplifiers, and high-power Wi-Fi 7 systems, where superior range and efficiency are critical.

What are the biggest challenges you are seeing in the industry?
As a startup company introducing products in a new and innovative technology (GaN-on-Si), the biggest challenge we face is the willingness of customers to accept these new solutions. Many potential customers for our technology and products tend to prefer using proven technologies, even with inferior performance, rather than adopt our innovative technology and higher performance products. We are partnering with distributors to market our innovative products to as many customers as possible and are starting to gain traction. The partnership we announced last year with GlobalFoundries has created more visibility for Finwave Semiconductor and for GaN-on Si as the promising technology for RF power amplifiers going forward, and our efforts are starting to bear fruit.

How is your company’s work addressing this biggest challenge? 

With the evolution of RF communications systems to higher frequencies for Wifi-7 or 6G communications, there is a need for new solutions to replace several existing semiconductor technologies that are running out of steam as required frequencies increase to the 6 – 20 GHz range. With our 200mm GaN-on-Si low-voltage E-mode MISHEMT platform, we are developing the next generation of RF power amplifiers to replace GaAs HBTs, with a solution that can operate at higher frequencies, with higher power density and efficiency and higher linearity.

In the RF switch market, we are introducing high-power RF switches in the 10-40 W range, with very fast switching and settling times in the hundredths of nanoseconds, broadband operation and significant lower cost that GaN-on SiC solutions, for example.

What do you think the biggest growth area for 2025 will be, and why?
In the RF communications space, architectures are continuing to evolve. We see the adoption of multiple antennas in telecom infrastructure as a very favorable development, and with the power requirements for RF power amplifiers coming down, this should accelerate the adoption of GaN-on Si at the expense of much more expensive GaN-on-SiC solutions, that are more suitable for very high-power applications. With spending increasing in the aerospace and defense markets, we see the need for high-power RF switches increasing in application such as drones, radars and satellites.

How is your company’s work addressing this growth? 
Since the first products we are bringing to market are our GaN-on-Si high-power RF switches, this is where we will experience the highest growth in 2025. We are working with a well-known distributor to market these products to a large array of customers in the telecom infrastructure and aerospace and defense markets. For one of our potential space customers, we recently demonstrated very good radiation hardness performance of our high-power RF switches, which saw no degradation in performance following exposure to a high level of radiation.

The second area of growth for Finwave Semiconductor in 2025 will be the introduction of our first high voltage GaN-on-Si RF power amplifiers for infrastructure applications.

What conferences did you attend in 2024 and how was the traffic?
Finwave Semiconductor participated in Mobile World Congress (MWC) in Barcelona in February 2024 and we were also present at the International Microwave Symposium (IMS) in Washington, DC, in June 2024. We had a very busy MWC last year, with meetings with customers, potential partners, suppliers, the press and industry analysts. With the sampling of our first high-power RF switches, IMS was more focused on potential customers and partners. Traffic was very good at our booth, and we had very fruitful discussions with many interested parties.

Will you attend conferences in 2025? Same or more?
We will attend the same conferences this year, MWC in Barcelona in March 2025 and IMS in San Francisco in June 2025. At MWC 25, we will give progress updates on the transfer of our technology for handset Power Amplifiers to GlobalFoundries, as well as provide an update on the performance and availability of our first RF switches.

How do customers engage with your company?
Today, most of our customers engage with Finwave directly, either by meeting with us at conferences, through mutual contacts or by contacting us through our web site (https://finwavesemi.com). With the signing of a worldwide distribution agreement with one the leading RF distributors, we expect that customers will increasingly engage with our distribution partner, who has offices and sales representatives around the world.

Any final comments?
With our first products being qualified and released for sale, 2025 will be a very exciting year for Finwave Semiconductor. After more than 10 years of technology development, the company is evolving from a technology-focused company to a product and customer centric company, focusing on releasing products to market, engaging with customers and growing revenues.

Also Read:

CEO Interview with Matt Desch of Iridium

CEO Interview with Mike Noonen of Swave Photonics

CEO Interview with Pradyumna (Prady) Gupta of Infinita Lab

Posted on

Accellera at DVCon 2025 Updates and Behavioral Coverage

Accellera at DVCon 2025 Updates and Behavioral Coverage
by Bernard Murphy on 03-11-2025 at 6:00 am
Categories: Accellera, Semiconductor Services

image

As usual I check in on Accellera activities each year at DVCon. Lu Dai (chair) gave an opening talk at the Accellera lunch, with contributions from other speakers on a few topics. In the afternoon I heard an update on PSS 3.0. What follows is a quick summary with my own musings on behavioral coverage.

Notable non-PSS topics

Karsten Einwich received the Accellera Technical Excellence award for his contributions to SystemC AMS. Interesting to me because an upcoming Innovation blog is based on a paper using SystemC AMS. Pulling AMS verification closer to mainstream verification is a popular theme these days and SystemC AMS adds a complementary system-centric angle.

The Federated Simulation Standard Working Group released a white paper and continues to look for more contributors/participants to help develop ideas. I’m excited to learn more as this evolves, given the ambitious scope of that coupled multi-domain simulation goal, folding in system-wide electronics (aircraft, cars, etc) together with mechanical, fluid dynamics and many other factors that full system OEMs must consider.

The UVM-MS group announced their 1.0 release, aiming to move us closer to a unified verification standard across digital and analog components. This is a very important step, given the increasing contribution analog is making in modern systems, from PLLs and power management, to sensing, to RF.

PSS 3.0

I consider myself fairly technical, though these days primarily in understanding why something is important and the broad strokes of how it is accomplished. I attended the PSS workshop at DVCon knowing quite a bit of the detail would go over my head but in hope that I would pick up a little insight and color. Unfortunately, and perhaps unsurprisingly I wasn’t even a little bit in their target audience. This was very much a hands-on session for practicing PSS users. I can’t blame them. But it did get me thinking more about a cornerstone feature introduced in the 3.0 release – behavioral coverage.

I write quite a bit these days on system verification, as in a big subsystem or SoC, not so much yet on (functional) verification for multi-chiplet systems because published material there is still very thin. However one inescapable fact holds: the bigger the design you need to verify, the more challenging it becomes to develop any sense of verification completeness. Which comes down to coverage, not just “how much testing is enough” but also “what kind of testing is needed”.

Code coverage tells you that you touched every line of code in your RTL. Property checks test for specific state conditions you know you must hit (or not hit). PSS sequences start to probe some paths through the design – initialize an interface, read some data from the input, write that data to the DMA, etc.

But how do you define coverage at the system level? Testing single thread paths through the design is a necessary baseline, but insufficient to account for the concurrency which delivers the main advantage of hardware over software implementations. IO, memory and cache controllers all aim to manage traffic between multiple hosts and multiple targets. As concurrency increases, competition for resources rises adding new complications: latency induced errors, deadlocks, incomplete initialization, prematurely reset flags, memory consistency errors, etc., etc.

Which hints at the kinds of coverage you need to be able to express. Take the memory consistency problem through caching as just one example. You want to check that you have covered all cases where two (or more) threads have successively accessed a cache line through all permutations of read/write and cache flags. If you find this cover has not been exercised, you can bias PSS test generation to make sure it will be exercised. Now extend the same line of thinking to IO subsystem coverage, DDR subsystem coverage, safety and security coverage, anything that spans across the design. A sufficiently expressive way to represent system-level concepts of concurrency-aware coverage is essential to support these needs.

For the more technically able, you can read the detailed spec HERE.

Also Read:

Accellera 2024 End of Year Update

SystemC Update 2024

Notes from DVCon Europe 2024

Posted on

CEO Interview with Matt Desch of Iridium

CEO Interview with Matt Desch of Iridium
by Daniel Nenni on 03-10-2025 at 10:00 am
Categories: CEO Interviews

Matt Desch Headshot

Matt Desch is the Chief Executive Officer of Iridium Communications Inc., the only satellite communications company that offers truly global voice and data coverage. He has more than 40 years of experience in telecommunications management, and more than 30 years in the global wireless industry. Joining Iridium in 2006, Desch has been responsible for leading the innovation and growth of Iridium, which includes taking the company public on Nasdaq (IRDM) in 2009, completing the financing and development of Iridium® NEXT, the company’s $3 billion investment in upgrading the Iridium network with powerful new satellites, and launching Iridium Certus®, a multi-service broadband platform enabled by the upgraded constellation.

Tell us about your company?

Iridium is the “OG” LEO satellite company. We’ve been providing critical connectivity to the farthest regions of the world for over 25 years and are still the only mobile voice and data satellite communications network that spans the entire globe. People may know us if they’ve used a satellite phone, but our primary business these days is enabling reliable connections through services like Internet of Things (IoT) that connect people, ships, aircraft and other assets to and from anywhere, in real time. Together with our ecosystem of over 500 partner companies, Iridium delivers an innovative and rich portfolio of reliable solutions for markets that require truly global communications.

What problems are you solving?

Whether it’s in the air, on land, or at sea, Iridium’s satellite network provides weather-resilient, reliable connectivity when and where it matters most. Iridium is first and foremost a safety service. Our unique network and our position in the radio frequency band allow us to serve many markets that struggle to adequately communicate with far away Geostationary (GEO) satellites, or where cellular towers do not reach. Due to the fixed nature of GEO satellites, signal blockages between a user and satellite can easily occur, whereas Iridium’s LEO satellites that are interconnected to each other in space enable uninterrupted communication anywhere in the world – even for ships sailing at high latitudes, adventurers in remote regions, or transoceanic planes far from land.

Our technology continues to get smaller and easier to deploy, such that it’s now able to be in programmed into chips that go directly into consumer devices like smart phones, smart watches and other small devices. Additionally, we are revolutionizing the Position, Navigation and Timing (PNT) field with a solution that protects GPS from jamming and spoofing and provides digital timing signals inside buildings. Our satellite network also tracks airplanes and helps to improve air traffic control across the oceans and many other places.

What application areas are your strongest?

Iridium is the solution for anything that needs reliable two-way connectivity. Cell phone towers – after almost 40 years in operation – only cover about 15% of the worlds surface. People and assets to be managed or tracked stray well beyond that coverage, and Iridium has become the choice for connecting the other 85% of the world, particularly for critical applications and where safety is paramount. You’ll find our technology utilized in all kinds of industries, including maritime, aviation, agriculture, energy, transportation, science and exploration, autonomous systems, first responders and government/military uses. We’re also seeing increasing interest from the automotive sector and everyday consumer devices.

What keeps your customers up at night?

Most of our customers are up at night, because that’s often when disasters strike! Because our network is so reliable, it is mandated in all kinds of safety applications both in the cockpits of airlines and helms of ships and is used to provide first responders with a connection in remote places of the world when it’s needed most. We are proud to provide safety of life services with high reliability, which can alleviate such concerns to our customers.

What does the competitive landscape look like and how do you differentiate?

Iridium’s satellite network and business is quite unique in the satellite industry. For example, Starlink is an exciting new service that focuses on broadband connections, while Iridium focuses on connections to people and assets. We scale down very effectively to very small devices that can even run on battery power, and thanks to our unique spectrum, we operate in any kind of weather and anywhere in the world.

There is also lot of buzz in the industry around D2D (Direct to Device) and NB-IoT. Iridium is positioning our new D2D service as complementary to many of these new emerging services.  Many companies seeking to provide D2D services are still seeking out spectrum and funding and need to launch their satellite networks or need to replenish their satellites frequently to stay in service. Iridium does not face any of these hurdles. Our network is completely global and fully operational – we have a dedicated, global spectrum allocation and already provide millions of customers with uninterrupted and dependable service in every environment. Additionally, our fully programmable network allows us to update our satellites in space to comply with 3GPP standards. Once we turn the switch on, Iridium’s NTN service will be fully operational and truly global from day one. This makes Iridium the ideal solution for chipmakers, MNOs, and customers.

What new features/technology are you working on?

Satellite communications has traditionally been proprietary amongst the various carriers, but that’s starting to change rapidly. Iridium is implementing the 5G narrowband IoT standard connections that are being adopted by smartphone and IoT processing companies to make it even easier for cellular customers to roam onto our network when they’re outside cell coverage. We’re also adapting our Satellite Time and Location® (STL®) service by shrinking it down to a single chip to make it even easier to deploy in cellular base stations, data centers, and other critical infrastructure that depends on GPS timing signals. This gives Iridium the edge to become the de facto global alternate PNT technology to augment other GNSS systems and protect users from the effects of jamming or spoofing.

Additionally, we launched our next generation satellite IoT device – the Iridium Certus™ 9704 Module and Development Kit. This new module is the smallest and most powerful created by Iridium and is ideal for creating new satellite IoT applications, including what we’ve dubbed satellite Artificial Intelligence of Things (AIoT) that require real-time data analysis, analytics and automated decision-making. The Iridium Certus 9704 delivers data, picture, and audio messages for industrial IoT, machine-to-machine applications, and remote personnel use cases – providing two-way IoT services anywhere in the world. It can help our partners make fast and reliable connections to a broad array of applications like predictive maintenance, diagnostics, telemetry monitoring, remote asset tracking, and command and control for uncrewed aircraft, vehicles and vessels.

How do customers normally engage with your company?

As a wholesale operator, we go to market through licensed technology and distribution partnerships. We’re always looking for new channels to market and new technology suppliers to embed our network into their customers’ applications. To learn more, visit: www.iridium.com

Also Read:

CEO Interview with Mike Noonen of Swave Photonics

CEO Interview with Pradyumna (Prady) Gupta of Infinita Lab

Executive Interview: Steve Howington of the Protective, Marine & High Performance Flooring Division of Sherwin-Williams

Posted on

Speeding Up Physical Design Verification for AMS Designs

Speeding Up Physical Design Verification for AMS Designs
by Daniel Payne on 03-10-2025 at 6:00 am
Categories: EDA, Siemens EDA

mismatch min

Custom and analog/mixed-signal IC designs have some unique IP and symmetry checking requirements for physical design. Waiting until the end of the IC layout process to verify IP instances for correctness or proper symmetry will cause project delays, so an approach to perform earlier physical verification makes more sense. I’ll share what I learned from reading a recent technical paper from Siemens on the Calibre Pattern Matching tool.

IP reuse is common for SoC design, but what if your IP block has a placement error like the one shown below in a memory cell array?

Symmetry of layout for many analog and mixed-signal designs is critical to achieve the specifications and for reliable operation. Doing manual symmetry checking with measurement tools is a slow and error-prone process. Applying cell mirroring or cloning are great design techniques but still needs to be validated. Circuit symmetry requirements could necessitate that new rule checks be created and may take too much development time.

Calibre Pattern Matching

There’s a tool from Siemens called Calibre Pattern Matching with new capabilities designed for early-stage physical verification of layout. Here’s the flow for when to run the tool.

Shift-left verification with Calibre Pattern Matching

Layout engineers can now verify layout symmetry interactively, saving time by using Calibre Pattern Matching with Calibre RealTime, all without coding specialized rules or resorting to measuring manually. Here’s what interactive symmetry checking looks like in the Cadence Virtuoso layout editor.

Symmetry Checking

When an IP block is instantiated in a layout the placement or alignment issues can be automatically caught with Calibre Pattern Matching, as shown next where two IP instances are verified and one is a 100% match, but the second instance has, what looks like, two metal routes crossing over it resulting in two XOR differences.

IP Mismatch

Your layout designers can ensure that critical IP blocks are placed consistently and verified early in the design. To find a particular layout pattern through a project, the designer can use the “Find Pattern” feature by selecting a layout area, then the Calibre Pattern Matching tool goes to work, all without any coding.

Find Pattern feature

Layout verification errors can overwhelm a designer, so there’s a feature to organize and manage verification data through the Results DataBases (RDB) Classifier, using layout context and groups for similar results, so that repetitive errors like cell arrays are quickly identified.

Example

An unnamed customer had issues with an IC showing audio distortion, and by using Calibre Pattern Matching they were able to quickly find symmetry violations. Manual measurements and cell mirroring weren’t sufficient to find these violations. Early identification improved design quality and reduced layout rework. IP placements were verified early in the design, instead of late, saving time. Less time was required for physical verification, so a shift-left approach really worked.

Summary

Custom and analog mixed-signal designs are complex to layout and can take much engineering time to meet the specifications. By using a methodology of early IP placement verification and interactive symmetry checking, designers can more quickly find and fix issues, cutting down time to market.

Read the technical paper online, Shift Left with Calibre Pattern Matching: Trust in design practices but verify early and frequently.

Related Blogs

Podcast EP277: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design with Rick Bye

Podcast EP277: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design with Rick Bye
by Daniel Nenni on 03-07-2025 at 10:00 am

Dan is joined by Rick Bye, director of product management and marketing at Arteris with responsibility for the FlexNoC family of non-coherent Network-on-Chip IP products. Rick joined Arteris from Arm where he was a senior product manager in the Client Line of Business, responsible for a demonstration SoC and compression IP. Rick has extensive product management and marketing experience in semiconductors and embedded software, having enjoyed roles at Texas Instruments, Broadcom, Silicon Labs, NXP and Foundries.io (now Qualcomm).

Dan explores the capabilities and impact of the new Arteris FlexGen Smart NoC IP with Rick. This revolutionary product uses cutting-edge AI heuristics and machine learning to automate NoC generation. Rick explains this technology allows the development of optimized NoC architectures in minutes to hours without the need for a NoC design expert. Current approaches require substantial NoC expertise and can take days to weeks.

Rick reviews the broad range of applications which benefit from the use of an optimized NoC. Essentially all advanced designs can utilize this technology to reduce time to market while optimizing latency, power and performance with less expert resources. Rick gets into the details of how Arteris FlexGen Smart NoC IP delivers these significant improvements.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Posted on

S2C: Empowering Smarter Futures with Arm-Based Solutions

S2C: Empowering Smarter Futures with Arm-Based Solutions
by Daniel Nenni on 03-07-2025 at 8:00 am
Categories: Arm, EDA, Emulation, IP, Prototyping, S2C EDA

S2c EDA ARM 2025

The tech world is sprinting toward a future where your fridge orders groceries, your car avoids traffic before you hit it, and security cameras don’t just watch—they understand. But behind these innovations lies a messy truth: building the brains for these smart systems is complicated.

Fresh off the 2024 Arm Tech Symposia circuit in Asia-Pacific, S2C is making waves with ready-to-deploy solutions for Smart Vision IoT and next-gen automotive tech. Let’s unpack how they’re helping developers cut through the noise and ship smarter products faster.

Smart Vision IoT: No More Reinventing the Wheel

Picture this: You’re designing a smart camera for retail stores. It needs to count customers, recognize loyal shoppers, and alert staff about empty shelves—all while sipping battery life. Sounds cool, right? Now imagine doing this from scratch in a market where every device has wildly different needs.

That’s where S2C’s Arm-Based Smart Vision Reference Design swoops in. Built on Arm’s rock-solid IP and S2C’s highly expandable prototyping system, this platform is like a Lego set for IoT innovators. Developers get pre-verified IPs that ditch months of grunt work, plus power-efficient performance for gadgets that never sleep. And here’s the kicker: FPGA prototyping lets teams test software before the chip even exists. No more crossing fingers during crunch time.

At the Arm Tech Symposia, S2C showcased two demos. One turned raw H.264 video into buttery-smooth playback, while another used AI to spot humans in live footage—think “smart surveillance meets Minority Report.” The message? Stop building foundations. Start stacking your genius on top of theirs.

Cars Are Computers Now. Let’s Treat Them That Way.

Your car’s codebase is now longer than War and Peace… times a million. Software-defined vehicles are turning dashboards into app stores and safety systems into AI co-pilots. But with great code comes great complexity. Automakers need tools to prototype, test, and iterate faster than a Tesla hitting Ludicrous Mode.

S2C’s answer? An Arm-Based Hybrid MCU Prototyping Platform that’s part sandbox, part crystal ball. It blends S2C’s Prodigy logic systems with Arm’s Cortex-R52+ processors—think of it as a playground for tomorrow’s car brains. Engineers can migrate from the traditional distributed processing architecture and simulate multi-domain controllers, and test new software, all before committing to hardware.

Why This Collab Feels Like Cheat Codes for Developers

S2C and Arm aren’t just selling widgets—they’re handing out shortcuts. With over 600 global customers already using S2C’s platforms, this partnership packs three big punches:

  • Speed: Skip the “plumbing phase”with pre-validated designs.
  • Freedom: Bake in your IP without starting from zero.
  • Trust: Lean on Arm’s certifications (SystemReady™, PSA Certified) and S2C’s street cred.

As Zhao Yongchao from Arm China puts it: “S2C’s partnership with Arm China enables us to address the unique challenges of the IoT and automotive industries. With their leadership in EDA and prototyping, S2C is well-positioned to help clients innovate and meet the growing demands for smarter, more efficient solutions.”

The Takeaway? Future-Proofing Is Now a Plug-in

The race to innovate isn’t slowing down—but S2C  just gave developers a jetpack. Whether you’re crafting AI-powered cameras or reimagining how cars think, their platforms slice through complexity like a hot knife through butter.

So here’s the real question: What could you build if someone else handled the heavy lifting?

Ready to turn your “someday” ideas into “shipped yesterday”? Let’s chat about how S2C can fast-track your next breakthrough with Arm-based solutions.

Craving more tech insights? Follow us for updates on IoT, automotive innovation, and the tools rewriting the rules of design.

Speak to an Expert

Also Read:

Accelerating FPGA-Based SoC Prototyping

Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping

Evolution of Prototyping in EDA

Posted on

CEO Interview with Mike Noonen of Swave Photonics

CEO Interview with Mike Noonen of Swave Photonics
by Daniel Nenni on 03-07-2025 at 6:00 am
Categories: CEO Interviews

Mike Noonen

Mike Noonen is CEO of Swave Photonics and has 30 years of experience leading technology businesses resulting in two IPOs and multiple acquisitions. Most recently he was the CEO of MixComm acquired by Sivers Semiconductor in early 2022.

Noonen was the Chairman and co-founder of Silicon Catalyst, the world’s first semiconductor incubator and EE Times 2015 Start-up of the Year. He has advised and led turnarounds at numerous innovative private and public companies such as Ambiq Micro, SiFive, Silego (acquired by Dialog Semiconductor), Mythic, Kilopass, Adapteva and Rambus.

In 2013 he was elected to the Global Semiconductor Alliance Board of Directors. Noonen holds multiple patents in the areas of Internet telephony and video communications.

Tell us about your company?

Swave Photonics is a fabless semiconductor company that designs Holographic eXtended Reality (HXR) chipsets with proprietary diffractive photonics technology. Using proven non-volatile Phase Change Materials (PCM) on a standard CMOS semiconductor process, Swave’s HXR technology creates high-resolution 3D images for Augmented Reality (AR) glasses and other applications. The HXR chip with 100s of millions to billions of these nano-pixels is illuminated by a low-power laser light source. The resulting images accurately portray an image’s depth in comparison to its surroundings, providing a natural and immersive viewing experience. Swave will deliver a reality-first user experience that integrates seamlessly with the physical world.

What problems are you solving?

Swave addresses the limitations of traditional AR form factors and displays. Its proprietary technology steers and sculpts lightwaves to achieve true holography. This allows the human brain and eyes to visually process the image naturally, solving the Vergence-Accommodation Conflict (VAC) — the phenomena in existing AR options that causes headaches, nausea and fatigue. Swave’s HXR technology does not require a waveguide, reducing size, weight, and cost, and greatly improving overall efficiency allowing for all-day use.  By using holography, Swave is able to handle prescription lens compatibility in software making it easy to provide optical correction for those that need it without requiring lens inserts or other cumbersome solutions.

What application areas are your strongest?

Swave’s first application area is in AR, with a focus on enabling compact, lightweight smartglasses that offer all-day battery life and prescription compatibility. Its HXR chip is the first spatial light modulator specifically designed for digital holography and AI-powered spatial computing. This groundbreaking technology provides a reality-first user experience where digital elements seamlessly interact with and complement the physical world. While the initial focus is on AR glasses, the applications for Swave’s HXR technology extend across a wide range of industries, including healthcare, manufacturing, logistics, retail, communication, gaming, education, automotive and aerospace.

What keeps your customers up at night?

Customers are challenged with creating AR solutions that are functional and stylish and don’t sacrifice performance or comfort. Current spatial computing experiences often rely on bulky and uncomfortable form factors, which isolate users and deliver unnatural or predominantly digital experiences. Customers are concerned with finding a technology that enables lightweight, attractive form factors while maintaining high performance and extended battery life.

What does the competitive landscape look like and how do you differentiate?

The competitive landscape for spatial computing is challenging, with many companies working to overcome the limitations of current AR and XR technologies. Swave’s HXR technology stands out and differentiates itself for several reasons:

  • True holography: Swave achieves true 3D holography with up to 64 gigapixels, providing high quality, immersive images that accurately depict depth and context.

  • All-day use:  Swave’s highly efficient holographic technology enables all-day use through light-steering to ensure all the light is used where it’s needed without throwing any away, it’s bistable pixels don’t require refresh until the image actually changes, and it doesn’t require inefficient waveguide technology

  • Form factor: Unlike traditional solutions that rely on bulky and complex optics, Swave’s HXR eliminates the need for waveguides, varifocal lenses, and stereoscopy enabling glasses that look similar to those you already wear.

  • DynamicDepth: Swave’s patented DynamicDepth technology allows images to be portrayed at life-like distances.

What new features/technology are you working on?

Swave is actively working on advancing its HXR technology to bring it closer to commercialization.

Swave’s technology also has the potential to extend beyond smartglasses. Future applications include heads-up displays (HUDs) for automotive use that offer drivers an augmented and immersive visual experience that enhances safety and usability. In the long term, Swave aims to create immersive holographic displays that do not require glasses, paving the way for a revolutionary shift in how we interact with digital information.

How do customers normally engage with your company?

The company is now taking orders for HXR development kits. These development kits include hardware and software that allow companies to design, prototype, and test new AR hardware and form factors using Swave’s cutting-edge chipset, offering a streamlined and efficient pathway for companies to bring their products to the market. The Swave team also engages with new customers and provides demonstrations at industry events.

Also Read:

CEO Interview: With Fabrizio Del Maffeo of Axelera AI

CEO Interview with Pradyumna (Prady) Gupta of Infinita Lab

Executive Interview: Steve Howington of the Protective, Marine & High Performance Flooring Division of Sherwin-Williams

Posted on

DVCon 2025: AI and the Future of Verification Take Center Stage

DVCon 2025: AI and the Future of Verification Take Center Stage
by Lauro Rizzatti on 03-06-2025 at 10:00 am
Categories: AI, EDA, Events, Siemens EDA, Synopsys

DVCon 2025

The 2025 Design and Verification Conference (DVCon) was a four-day event packed with insightful discussions, cutting-edge technology showcases, and thought-provoking debates. The conference agenda included a rich mix of tutorial sessions, a keynote presentation, a panel discussion, and an exhibit hall with Electronic Design Automation (EDA) vendors demonstrating their latest tools and engaging with customers.

AI Dominates the Discussion

A dominant theme throughout the event was Artificial Intelligence (AI), which was featured in over 60 technical papers, 18 technical posters, a dedicated keynote, and a high-profile panel discussion. The tutorial sessions included real-world customer case studies and pioneering university research, demonstrating how AI is reshaping verification methodologies and challenging traditional workflows.

Prime Time for Hardware-Assisted Verification

Hardware-Assisted verification (HAV) was also a prominent topic in technical sessions, keynote and panel. As AI drives innovation across virtually all industries, from industrial, to agriculture, banking, medicine, automotive, mobile, and more, the verification engineers are grappling with the complexity of increasingly sophisticated AI processing hardware. The surge in AI-specific accelerators, custom chips, and groundbreaking computing architectures has amplified verification challenges, pushing traditional software-based verification methods to their limits.

In response, hardware-assisted verification (HAV) platforms have become a cornerstone of modern verification strategies. Their ability to manage massive workloads, expedite test cycles, facilitate shift-left methodologies, and provide comprehensive system-level validation and debugging is increasingly vital. The surge in user interest, demonstrated by the strong attendance at conference technical sessions, underscores this trend. With the continued advancement of AI hardware, the necessity for HAV solutions will only intensify, cementing their position in guaranteeing the performance, accuracy, and reliability of next-generation computing systems.

The Rise of Portable Stimulus Technology

Following AI and HAV, portable stimulus technology emerged as another significant subject of interest. This methodology, now adopted by multiple companies, was explored in-depth, with discussions on internally developed frameworks and EDA vendor-driven solutions. Attendees witnessed how the industry is increasingly leveraging portable stimulus to improve test coverage and verification efficiency.

Other Key Topics

Beyond AI, HAV and portable stimulus, DVCon also highlighted significant advancements in:

  • UVM Deployment Case Studies: The industry continues to refine and expand the Universal Verification Methodology (UVM) framework, with companies sharing their successes and lessons learned.
  • A Broad Spectrum of Verification Topics: From formal verification techniques to new methodologies in functional safety and security, DVCon showcased a diverse array of technical advancements in design verification.
Keynote: The AI-Driven Revolution in Chip Design and the Rise of the AI Factory

The much-anticipated keynote, “AI Factories Will Drive the Re-invention of Chip Design, Verification, and Optimization,” delivered by Ravi Subramanian, Chief Product Management Officer and leader of the Product Management & Markets Group (PMG) at Synopsys, and Artour Levin, Vice President of AI Silicon at Microsoft, provided a compelling analysis of how artificial intelligence is fundamentally reshaping the semiconductor industry.

The speakers emphasized that AI is no longer just an enabler of innovation, rather, it has become the driving force behind a radical transformation in chip design and verification. This shift is fueled by the relentless expansion of large language models (LLMs) and their insatiable demand for high-performance AI accelerators. Ravi framed the magnitude of this evolution by comparing Moore’s Law, which historically predicted the doubling of transistor density approximately every 18 months, to the explosive growth in LLM parameters, which now double—or even quadruple—within just three to six months.

The presentation featured detailed charts and striking data points that underscored the seismic changes underway. These insights illustrated the mounting complexity in verification, design optimization, and system-level architecture, highlighting how the industry is contending with an era where traditional methodologies are losing steam. The increasing demand for processing throughput presents one of the biggest engineering challenges, as AI workloads continue to scale exponentially. At the same time, memory bandwidth and capacity are struggling to keep pace with the ever-growing model sizes that demand faster access and larger storage capabilities. The tsunami of data required for AI training and inference is estimated to double the total amount of data traversing the Internet each year, adding pressure to an already strained infrastructure.

Another critical issue is interconnect bandwidth, which has become a major bottleneck as AI workloads require ultra-high-speed data movement between compute nodes.

The challenge of energy efficiency looms large, as the industry strives to balance performance gains with power constraints for sustainable scaling. Artour emphasized, “Managing power while scaling performance is critical. If power isn’t controlled, deploying these chips in data centers becomes infeasible. The industry must figure out ways to exponentially grow compute, memory bandwidth, and interconnect efficiency while keeping power consumption sustainable.” He further noted, “Historically, software entered the chip development cycle late, but AI accelerators are fundamentally software accelerators. This shift requires software modeling to begin at the architectural phase. Understanding workloads early enables more efficient hardware design, optimizing transistors and silicon resources to maximize performance while at minimizing power. Additionally, today’s software stacks are highly complex. Waiting for silicon to develop software is no longer viable, pre-silicon software development is essential, adding another layer of design challenges.”

Compounding these technical challenges is the massive financial burden of developing next-generation AI hardware. The capital expenditure (CapEx) required to sustain innovation in this space is reaching unprecedented levels, forcing companies to make strategic, long-term investments in infrastructure.

Ravi summed up the momentous shift by declaring that we are on the cusp of a new industrial revolution, one defined not by traditional manufacturing but by AI-powered computation at an unprecedented scale. The AI Factory, a paradigm where AI not only designs chips but optimizes, verifies, and accelerates the next generation of semiconductor breakthroughs, is no longer a vision for the future. It is happening now.

With AI taking center stage in the reinvention of chip design, verification engineers, system architects, and semiconductor companies must adapt to a landscape that is evolving faster than ever before. The keynote left attendees with a powerful message: embracing AI is no longer optional, it is essential for those looking to stay ahead in the age of AI-driven silicon innovation.

Panel: Are AI Chips Harder to Verify?

One of the conference highlights was the panel discussion titled “Are AI Chips Harder to Verify?”

Moderated by Moshe Zalcberg, CEO of Veriest Solutions, the discussion brought together a distinguished panel of industry experts: Harry Foster, Chief Scientist, Verification at Siemens EDA; Ahmad Ammar, Technical Lead, AI, Infrastructure, and Methodology (AIM) at AMD; Stuart Lindsay, Principal Hardware EDA Methodology Engineer at Groq; Shuqing Zhao, Formal Verification Lead at Meta; and Shahriar Seyedhosseini, Generalist Engineer at MatX.

The panel unanimously acknowledged the substantial hurdles in verifying AI chips, but their detailed analysis revealed nuanced perspectives.

Harry Foster (Siemens EDA) highlighted a crucial divergence from traditional SoC verification. He emphasized that AI architectures operate on probabilistic principles, contrasting sharply with the deterministic nature of conventional designs. This shift implies that AI chips aim for “approximate correctness” within acceptable thresholds, rather than strict pass/fail outcomes, thereby necessitating a fundamental recalibration of verification methodologies. How, he questioned, do you effectively verify a system that inherently operates on non-deterministic principles?

The discussion debated the limitations of existing EDA tools. While these tools have significantly advanced the verification of traditional chips through formal verification, simulation, and emulation, they struggle to adapt to the dynamic and adaptive behavior of AI accelerators. These accelerators, driven by constantly evolving learning models, diverse data distributions, and statistical inference, present a moving target for verification.

Ahmad Ammar brought attention to the scale of deployment, emphasizing that AI chips are typically deployed in massive clusters to handle demanding AI workloads. He pinpointed the difficulty of adapting those massive workloads onto individual chips or small subsets to achieve realistic verification.

Stuart Lindsay focused on the complexities of AI chip data paths, where the flow of data is not static but dynamically changes based on the parameter values being processed. This variability, coupled with mixed-precision operations where precision levels shift throughout the pipeline, adds significant complexity to modeling and prediction. Furthermore, the dynamic evolution of system states and the presence of feedback loops further complicate the verification process.

Shuqing Zhao championed the role of formal verification in AI chip validation, while acknowledging the need for adaptation to handle the probabilistic and approximation-driven nature of AI workloads.

The panel collectively recognized the imperative of adopting a “divide and conquer” strategy to manage the sheer complexity of AI chip verification.

A final, provocative question from DVCon Panel Chair Ambar Sarkar asked the panelists to rate the difficulty of AI chip verification on a scale of 0 to 100% (0 being traditional chips, 100% being twice as hard), and proposed his own estimate at just 5%. The panelists’ responses varied, reflecting their diverse perspectives. While most leaned towards the higher end of the scale, acknowledging the increased difficulty, Shahriar Seyedhosseini offered a contrasting view. He pointed out that, unlike general-purpose processors, AI workloads are statically compiled, which simplifies fine-tuning and coverage. This, he argued, offsets some of the added complexity, limiting the verification challenge to only 5% more than that of a traditional SoC. He also noted that AI chip verification is, in many ways, more enjoyable.

The panel concluded with a resounding acknowledgment that the increasing complexity of AI accelerators necessitates a fundamental rethinking of hardware verification. The industry must adapt and innovate to ensure the performance and correctness of these critical components in the evolving landscape of AI-driven computing.

Conclusion

DVCon 2025 delivered a comprehensive look at the future of design verification, with AI at the forefront of innovation. As verification engineers navigate new challenges in AI hardware, portable stimulus, and hardware-assisted verification, DVCon continues to be the premier platform for knowledge sharing and industry collaboration.

Also Read:

Synopsys Expands Hardware-Assisted Verification Portfolio to Address Growing Chip Complexity

How Synopsys Enables Gen AI on the Edge

What is Different About Synopsys’ Comprehensive, Scalable Solution for Fast Heterogeneous Integration