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January 4, 2015July 18, 2025

Prototyping Kits to Accelerate IP Development & Integration into SoCs

Prototyping Kits to Accelerate IP Development & Integration into SoCs
by Pawan Fangaria on 01-04-2015 at 10:00 am
Categories: EDA, IP, Synopsys

With growing SoC size, complexity, software and hardware content in it and shrinking time-to-market, the SoC design completion in time has become increasingly dependent on IP which need to be sourced (internally or externally), customized according to the design need and integrated together into the SoC. While IP providers can provide best optimized IP with good configurability and flexibility, its integration into SoC is not a straight forward task; it needs significant amount of work to consider various configurations, negotiate with significant amount of legacy design, adhere to frequent changes in standards and protocols, optimize, prototype and validate it in an SoC context before its integration into the SoC. How to do it when the final SoC is not yet available?

That’s the beauty of EDA vendors getting into the shoes of IP providers to provide complete automation to make an IP ready to be integrated into an SoC as fast as possible. While Synopsys, over a couple of years, has built a strong IP portfolio, it is now marching into accelerating the IP integration into SoC through several of its programs under “IP Accelerated Initiative”. Synopsys is providing DesignWareIP Prototyping Kits for several IP titles to accelerate designers’ IP prototyping, software development, and integration into SoCs. A Kit specific to an IP comes with proven reference design that can be used to explore design trade-offs with specific configurations of the IP, optimize the IP and validate it with fast iterative flow. The same design can be set as a target for early software bring-up, debug and test.

Above is an IP Prototyping Kit for USB 3.0 Device Controller. The Kits, in general, include Synopsys’ HAPS-DX FPGA based prototyping system with proven reference design, pre-configured IP, necessary SoC integration logic, PHY daughter board, simulation testbench, reference drivers and application examples along with either a connection to host PC (running the target OS) or DesignWare ARC processor based 32-bit software development platform running Linux. Assisted with Synopsys’ coreConsultantIP configuration tool, ProtoCompiler DX development and debug tool, and several scripts, designers can instantly modify and optimize the IP configuration, develop drivers and other software and accelerate integration of the IP into the target SoC.

The USB 3.0 Kit has been observed to be working excellently in customer’s design environment. It accelerates driver and software development early for customers to advance their schedule for FPGA validation by several weeks.

There is an example of a DDR IP Subsystem consisting of memory controller, communication ports, PHY block and so on, each of which requires configuration at hardware and software levels to ultimately define permissible functionality, range of registers, and connectivity characteristics and so on. While an FPGA image rebuild or even simulation (that involves OS setup, loading, initialization, accessing proper communication busses and debugging) for any hardware change can take several hours to days, the IP Prototyping Kit can accelerate iteration cycles by providing IP reference designs in a tested environment that allows fast exploration of different configurations through hardware-aware development tools. Look herefor more details on the Kit for “DDR uMCTL2 and Gen2 multiPHY with ARC Software Development Platform”.

Today, Synopsys provides DesignWare IP Prototyping Kits for multiple interface protocols including USB 3.0, SSIC, PCI Express 3.0 and 2.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI 2.0, and JEDEC UFS. Through these Kits, the designers need not spend much time in learning about the internals of IP and other details. A Kit provides ready environment for designers to implement an IP in an SoC context instantly, thus boosting their productivity which helps them in meeting challenging time-to-market.

Secure Microprocessors the Andes Way

Secure Microprocessors the Andes Way
by Paul McLellan on 01-04-2015 at 7:00 am
Categories: Andes Technology, IP

Microprocessor vendors such as Andes have been saying for some time that security requires extensive hardware support. In particular, embedded processors in intelligent sensors inside IoT chips are now popular targets for hackers, who find it easy to change the program code and system parameters to alter the operation of the sensor or to use the system for their own purposes. Every time a major breach occurs, like the recent infiltration of Sony, the message that security cannot be left in software only becomes stronger.

There are different levels of hardware support for security. At the lowest level, the encryption keys need to be kept in hardware and the access carefully controlled. But there are a lot of other more subtle ways to attack a microprocessor-based system.

One point of vulnerability to hackers in an embedded system is the JTAG interface. An attacker able to put the system into debug mode has complete control of the system with complete access to the CPU’s registers, program memory and another memory in the system. To provide protection of embedded software and program data while keeping the debugging capability, Andes secure debugging feature requires pass code validation. Anyone accessing JTAG port must provide a pass code, which can be provided in a static or dynamic form. A static pass code is stored in non-volatile memory in the chip. Anyone attempting to access the JTAG interface must provide the stored code. The other alternative is storing the pass code on a remote server and anyone accessing the JTAG port must acquire the pass code from the server.

Another point of vulnerability in an embedded system is the memory interface brought out to the pins on the packaged part to access external memory. By probing the interface pins with a logic analyzer, attackers can capture all the traffic passing between external memory and the embedded CPU. To secure the memory interface, the Andes secure MPU scrambles the data and/or address thus displaying random information to a logic analyzer probe and making it impossible to copy the memory contents without the encryption key.

A third technique used to hack into embedded designs is differential power analysis. This is a technique developed by Cryptography Research and works by looking at the power consumption of the system cycle-by-cycle and by looking at small differences in repetitive operations (such as DES encryption) to try and deduce, for example, the key. It is especially important to protect against in smart cards, which are used in credit and debit cards in most of the world (and probably coming soon in the US). The Andes solution is to randomize the power profile to eliminate the repetitive patterns, thus making the CPU less vulnerable to this type of hacking. One technique used to achieve this result includes a hardware random-bit generator that randomizes the internal clock signal. Another technique is to use a hardware random-bit generator to schedule per instruction cycle between two or more threads of execution that run on the MPU’s register sets.

Of course security is a sort of war in which the attacks never get weaker. Andes continues to enhance their microprocessor solutions to keep their security strong.

Update: Who will manufacture the Apple A9?

Update: Who will manufacture the Apple A9?
by Daniel Nenni on 01-04-2015 at 12:00 am
Categories: Foundries, GlobalFoundries, TSMC

Last August I presented possible scenarios for the manufacturing of the Apple A9 processor. Quite a bit has changed since then so I think it is worth revisiting. There has also been quite a lot of misinformation in the press which is now pretty much a daily thing. Attending the IEDM conference last month really was a stark difference than what “The Google” has to offer people who are looking for answers in all the wrong places. Seriously, the chasm between the two sides (semiconductor professionals and non-professionals) really is quite large.

Also Read: Who will Manufacture Apple’s Next SoC?

As we all know Apple has disrupted many different industries with innovative technology and aggressive business practices, the semiconductor industry included. Apple is now one of the largest and most innovative fabless semiconductor companies and becoming part of their supply chain is bringing a whole new level of competition amongst the fabless semiconductor ecosystem. Let’s start with last year’s blog Samsung ♥ GLOBALFOUNDRIES.

You have to ask yourself why Samsung REALLY did this deal with GF? One theory, which I firmly believe, is to get the Apple SoC business back from TSMC. Apple amongst many others (myself included) really wants GF to be successful for the greater good of the pure-play foundry business. Take a look at the last paragraph I wrote:

An interesting thing: On one side of the briefing table was Ana Hunter, Vice President of GLOBALFOUNDRIES, formerly Vice President Foundry, Samsung Semiconductors. On the other side was Kelvin Low, Senior Director, Foundry Marketing Samsung, formerly Director Product Marketing, GLOBALFOUNDRIES. It’s a small world after all.

Ana Hunter was instrumental in the foundry relationship between Samsung and Apple so who better to bring Apple to GF? Since the GF 14nm is a copy exact version of the Samsung 14nm, Apple has two manufacturing sources for the A9. And from what I learned at IEDM, both are now yielding in time for the next iPhone launch (September 2015). The Apple A9X (higher performance version) is still slated for TSMC 16FF+. This chip will go into tablets but may also be seen in laptops and possibly a high performance version of the iPhone making it a much higher volume chip than originally expected.

Yes I know Barron’s is still repeating that the foundries have not figured out FinFETs leaving the door wide open for Intel blah blah blah… absolute nonsense:

“Could Intel (INTC) be in a position to be Apple’s (AAPL) savior? That intriguing bit comes from Drexel Hamilton’s chip analyst Rick Whittington, from a note on Micron. In passing, Whittington notes problems had by Taiwan Semiconductor (TSM) and Samsung Electronics (005930KS) trying to produce 3-D transistors. Intel has mastered 3-D transistors, and so, writes Whittington “btw, very good for Intel if neither Samsung or TSM can do FinFET this next year; puts them in line to supply Apple’s internal foundry needs; more likely TSM/Samsung operate FinFET under very low yield output, keeping capacity tight.”

Yet another analyst pretending to be a semiconductor professional…..

Again, Samsung, GlobalFoundries, and TSMC are now yielding FinFETs with high volume production starting in Q2 2015. The next versions of iPhones and iPads will be FinFET based, absolutely.

January 3, 2015

Is the Internet of Things just a toy?

Is the Internet of Things just a toy?
by Bill Boldt on 01-03-2015 at 5:00 pm
Categories: Foundries, IoT

The Internet of Things (IoT) is arguably the most hyped concept since the pre-crash dot-com euphoria. You may recall some of the phrases from back then such as “the new economy,” “new paradigm,” “get large or get lost,” “consumer-driven navigation,” “tailored web experience,” “it’s different now,” among countless other media fabrications.

The IoT is the new media darling. In fact, it has been dubbed everything from the fifth wave of computing, to the third wave of the Internet, to the next big thing, to the next mega-trend, to the largest device market in the world, to the biggest efficiency booster/cost reduction technology. You get the picture.

Now, the question is whether or not the IoT will indeed be more real than just hype, as is the case with any media powered feeding frenzy. Let’s start by looking at the numbers.

Respected market researchers and giant networking companies are predicting gigantic numbers of connected devices to the tune of 20 to 50 billion units of installed base by 2020 or 2025, with some estimates even going higher. With numbers like that coming from the world’s most-followed, reputable sources, it won’t be long before high roller investors start placing enormous bets on who will be the winners of the IoT game; a game that will be make Vegas action look like a game of marbles. The IoT casino is now open.

There is really big money at stake because IoT represents a perfect storm of opportunity for venture capitalists and bold corporate acquirers — that is because many believe that half the successful IoT companies don’t even exist yet. Conditions don’t get much more attractive than that when it comes to risk capital.

Here’s a hot tip: Only bet on the companies offering systems that articulate a clear strategy that put strong security (especially authentication) as a top priority. This tip is derived from the observations of Dr. Vint Cerf (the acknowledged creator of the Internet) who declared that the IoT will require strong authentication. And, he’s right. Note well that the strongest authentication comes from hardware-based cryptographic key storage because hardware key storage beats software-based key storage every time. Inexpensive and easy-to-use integrated circuit devices already exist to do just that. The media should grasp that but don’t seem to get it yet.
The dirty little secret of the constantly-connected era is that without security, the IoT will just be a toy that consumers, governments, and corporations cannot take seriously. What good is a system of billions of interconnected things sensing and sending data (often through the cloud) that can be intercepted, corrupted, and spoofed? Not very much. IoT growth is dependent upon security.

Charting the Growth
The graphs below show estimated unit shipments and the resulting installed base of IoT devices. What has also been called out in each chart are devices with on-board security, mainly hardware-based security, and those that do not have built in hardware security. Most market estimates out there tend to show the growth of the IoT in terms of installed bases, growing to many billions by 2020. Typically speaking, you will see a chart like the one below, but without the divisions between secure and insecure nodes.This is a case of the devil being in the details, because installed base charts can be very misleading. Data jockeys such as market researchers and statisticians know very well that installed base is a tricky way to present data. Fair warning: Beware of drawing conclusions from installed base charts only.

The IoT case is a perfect example of how to hide the important information, because even if you remove the secure nodes, the chart still looks like there will be enormous growth. However, that masks the fact that growth will plateau without the secure nodes being a part of the picture. It is a an illusion caused by the fact that the early days of the IoT will build a base of significant numbers, but the volume shipments will fall off quickly as users reject insecure solutions precisely because they are insecure.

The installed base IoT chart is analogous to chart of automobiles in the time of Henry Ford showing the installed base of black cars (remember Model Ts came in any color as long as it was black). That would show that black cars were the overwhelming color and it would be impossible from that chart to conclude anything other than they always would be. Obviously, such a chart would mask the market changes that in fact happened and the inflection points as to when the changes happened. Masking is exactly what the IoT installed base chart does.

It fails to show that the inflection point towards secure nodes that is starting right now, which is a shift that will happen quickly. Reason being, the need for security is becoming clear (just ask Sony, Target, Home Depot, JP Morgan, and Iranian nuclear scientists about that). As aforementioned, inexpensive hardware-based devices are available now that can provide strong security to IoT nodes.

The unit shipment slide is what tells the real story. And, that is that security is becoming a requirement of IoT if growth is to be sustainable. Simply stated: Without real security, the IoT will falter.

Security Maters
Security matters because users must trust that the nodes are who they say the are (i.e. are authentic). Additionally, confidentiality of the data is important to keep unauthorized third parties from getting the data and misusing it. Also, without data integrity mechanisms there is no way to ensure that the data have not been tampered with or corrupted. All three of these matter. A lot.

However, with all the press that the IoT receives and all the tremendous predictions of giga-volumes, you just don’t hear much other than passing comments about security. Security should, in fact, be the prerequisite of any article, discussion, or plan for IoT-based anything. Talking about the Internet of Things without addressing the security question (with specifics) is like talking about scuba diving without mentioning water.

Security gets short shrift even though it is pivotal to the IoT’s existence (and important to literally everyone in the digital universe, including the readers of this article). One main reason is that the meaning of security is not really well understood. As a result, engineers, executives, investors, and researchers alike have been mainly whistling past the graveyard hoping that their digital interests will not be attacked too badly. However, with the increasing frequency, variety, and creativity of security breaches and especially with the advent of breach-based litigation, the danger is increasing and finally more attention is getting paid. It is not hard to envision ambulance-chaser legal firms moving from class action suits regarding asbestos, medical devices, and pharmaceuticals to seeking data-breach damage rewards. In actuality, this has already started. You can almost hear the cloying ads already.

Security Defined

There are two important and fundamental questions about security and the IoT:

1. What is IoT security?
2. How do you implement it now?

To address the first item, the best way to understand it is to break it down into the three pillars of security, which are confidentiality, data integrity, and authentication (ironically referred to as “CIA”). The second inquiry is related directly to the first because implementing security is a function of how well you address the three pillars.

It is critical to address security right now because because putting insecure systems into the world is just asking for trouble. There is no time to wait. Assembling a network or product dependent on a network that is filled with vulnerabilities is bad practice. The good news is that thanks to cryptographic engine integrated circuits with hardware-based secure key storage powerful solutions are clear and present.

Crypto Engines
Crypto engines refer to a dedicated integrated circuit devices that handle crypto functions such as hashing, sign-verify (e.g. ECDSA), key agreement (e.g. ECDH), authentication (symmetric or asymmetric), encryption/decryption, message authentication coding (MAC), run crypto algorithms (e.g. elliptic curve cryptography, AES, SHA), and perform many other functions. The other critical part of the equation that makes crypto engines so valuable is their ability to store cryptographic keys in ultra-secure hardware. (The CTO of a major home networking company recently described storing cryptographic keys in software being like storing a key in a wet paper bag.)

Providing the exact type of security needed for the IoT to grow is what crypto engines like CryptoAuthentication solutions are all about. They make security both easy and cost effective. The amazing thing is that crypto engine devices were invented before the IoT even existed. Now they are arguably the ideal catalyst to drive IoT growth when they are added to the other fundamental elements of the IoT. So, it should be clear that there are now four elements to a serious IoT node:

1. Intelligence (microprocessors)
2. Communications (Wi-Fi, Bluetooth, etc.)
3. Sensors
4. Security

These four items will be the recurring theme of IoT nodes. The story from here will be which communications standards are supported, the level of integration, how security is handled (standards and methods), performance, speed, power, size, etc., not if security is there or not.

Long story short: While some sort of IoT is possible without security, without security it would really just a toy.

Bill Boldt, Sr. Marketing Manager, Crypto Products Atmel Corporation

January 3, 2015

IEDM: FD-SOI Down to 10nm

IEDM: FD-SOI Down to 10nm
by Paul McLellan on 01-03-2015 at 1:48 pm
Categories: FD-SOI, Foundries, STMicroelectronics

The big picture is that planar semiconductor transistors don’t really work below 20nm. The reason is that the gate does a poor job of controlling the channel since too much channel is too far from the gate and so there is a lot of leakage even when the transistor is nominally off. So the channel needs to be made thinner. One way to do this is to make it into a thin fin and wrap the gate around it. That is what Intel, IBM and TSMC have all done and I reported on their papers at IEDM last month.

See IEDM: TSMC, Intel and IBM 14/16nm Processes

The other alternative is to build the channel as a thin layer on an insulating wafer (SOI). This is the approach that has been pioneered by ST Microelectronics and its partners. They also presented at IEDM in a paper entitled FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10um Node. The paper has a long list of authors from ST, CEA-LETI, IBM, Soitec, and Albany Nano Tech.

Planar fully depleted silicon-on-insulator (FDSOI) technology represents an important device architecture for continued CMOS scaling. Its advantages include excellent short-channel electrostatics, un-doped channels and effective back bias for performance boost and leakage lowering. Moreover, FDSOI is fabricated using a more conventional, lower-cost process than more complex FinFET architectures. Researchers from STMicroelectronics and the IBM Technology Development Alliance discussed the successful implementation of strained FDSOI devices with gate lengths, spacers & buried oxide (BOX) dimensions compatible with design rules of the 10nm technology node.

Two additional enabling elements for scaling FDSOI devices to the 10nm node were reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also will report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 μA/μm for NFET at Ioff=1 nA/um, and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 μA/μm at Ioff=1 nA/um.

Facts Support New Emergence in Semiconductor Landscape

Facts Support New Emergence in Semiconductor Landscape
by Pawan Fangaria on 01-03-2015 at 9:00 am
Categories: EDA, Foundries, General, IoT, IP, Mobile

As we left an exciting year 2014 which is poised to record 7+ % increase in semiconductor revenue (~ $338 B) compared to 2013 (~ $315 B) and entered into another promising year 2015 for semiconductors, I looked back over the year bygone and collected inferences from some of the major important events which clearly convey how 2015 can be pivotal to provide momentum to some of the newer areas ushering semiconductor landscape into newer territories. Although we hear about many hot topics on our way, but few make it to the finishing line; that’s a reason I tried to assimilate things in the complete ecosystem, see how they have performed in the past and how they connect together to ascertain real completion to finish lines for some of the larger goals in the industry.

Before I get into details, to sum up there are a few areas which will see maximum activities and they can provide enough thrust to transform semiconductor industry to newer heights – these are IoT (Internet-of-Things), I would say internet of everything market, smartphone market and system level EDA (we may call it ESL) including IP to support those markets. Well these are not new things I am talking about; we have seen these on our way. What is interesting is that when I looked at how things have progressed so far, they convince me that there is a great momentum, technically as well as businesswise, pushing these three areas to finishing lines. They are going to transform semiconductor industry into newer growth zone for at least next decade. Let’s see how things are folding into these three major dimensions which are interrelated.

On the macroeconomic front, with a few consecutive years of consistent, nominally increasing semiconductor revenue (in 2013 it was 5+ % increase compared to 2012) on top of significant investment in newer technology and process nodes, we can safely assume that we are on the side of growth curve in semiconductors.

The businesses responds according to macroeconomic scenario after taking into account the forward earning cues. Consolidation and expansion are typical of businesses in particular areas based on their life cycle stages. When the semiconductor economy was in decline or trying to come out of recession, we saw mega consolidation in existing EDA and design spaces including foundries (we have seen GLOBALFOUNDRIESacquiring IBM’s foundry business even in 2014) and semiconductor equipment arena. Now we are seeing business leaders expanding in newer areas such as IoT related technologies, IP and system level EDA that includes system prototyping, verification and reliability. Smartphone market remained in the middle with large scale consolidation as well as new entrants eyeing to capture the remaining low-price-point market. Below I will talk about both businesses as well as technical angles for each of these three areas – smartphone, IoT and system level EDA (including IP).

Smartphone – Lenovobought Google’s Motorolaunit, Microsoftbought Nokia; those are towards consolidation. We see a major expansion side too with Xiaomi, OnePlus, Huawei, Gionee, Google Android1 phones and many others. The smartphone market will keep on seeing major revenues. The technical angle to this is that smartphone will play a pivotal role in the expansion of IoT devices in several sectors including personal, home, social, industrial, health, automotive, and so on. Most of the IoT devices will be controlled through smartphones, and therefore the companies who provide best IoT enabled smartphones will be the winners.

IoT – This is a major expansion space at different levels – enterprise, medium and low scales. Google bought Nest Labsthat provides home automation technologies such as thermostat and smoke detection; CEVAacquired RivieraWavesthat specializes in IP for connectivity with smartphones through WiFi and red-hot Bluetooth; MegaChipsacquired SiTimethat has 80% share in MEMS timing solution; NXPis to complement its IoT portfolio with Quintic’sassets and IP related to wearable and Bluetooth Low Energy (BTLE) business; Qualcommis buying CSR(a pioneer in Bluetooth wireless technology to connect devices to smartphones) to expand in technology for connected appliances; earlier Qualcomm bought Wilocity, which makes WiFi products for home internet routers and appliances that connect to the web. Qualcomm also developed an open source platform, AllJoyn for connected devices to work together.

This is not all, there are major activities going on in this space in several companies, either in-house or through acquisitions. We are going to see major technological moves to solve security issues, large data management (storage, filtering, secured transmission, access, privacy, and so on), communication protocols, standardization in software, o/s, devices optimized on several parameters and so on.

System level EDA – Last year has seen EDA leaders getting into ESL related and system level reliability, verification, optimization, and application areas with renewed fervor. Cadencebought Forteto strengthen HLS solution and Jasperto expand complex system verification solution. Mentorwent on to further expand its automotive section, acquired Mecel Picea AUTOSAR Development Suite from Mecel AB; acquired XS Embedded GmbH, a leader in creation of automotive system architectures and hardware reference platforms. Mentor strategically eyed on system reliability space, acquired Nimbic, a leader in 3D full-wave electromagnetic simulation solutions that provides signal integrity, power integrity and EMI analysis for systems on scalable cloud compute platform. To strengthen SoC design and verification flows further, Mentor acquired Certus ASIC Prototyping Debug Solution that addresses challenges in FPGA prototyping. Also Mentor acquired Berkeley Design Automation to advance nanometer AMS verification. Synopsysis not behind in acquisitions, it acquired Target Compiler Technologies that strengthens its ARC Designware family by enabling design and programming of ASIPs (Application Specific Instruction-set Processors).

Synopsys and Cadence have already made strong portfolios in IP. While providing system level automation for SoCs, it’s strategic advantage for them to have IP portfolios. Cadence went ahead buying high speed interface IP assets from TranSwitch. ARM, being an IP leader, went ahead acquiring Duolog to strengthen its IP configuration and integration capabilities addressing increasing SoC complexities and sub-system functional verification.

There are many other activities happening around the world in IP, system level automation, and connectivity between things and internet. It’s clear, EDA and IP providers are vying to fill the gap between chip design and system design by providing robust and reliable IP and seamless automation for prototyping, optimization and integration of SoCs; the design houses are striving towards providing complete and secure systems of connected devices; smartphone makers will be gearing up to catalyze the IoT phenomenon by enabling connections between devices and the web through their smartphones; and foundries are already on their march towards providing light weight, low power, high performance devices suitable for IoT.

Let’s watch for more trends evolving in this direction in this year. Wishing the semiconductor community an exciting 2015!!

WLAN Design Optimization at Lantiq

WLAN Design Optimization at Lantiq
by Daniel Payne on 01-02-2015 at 7:00 am
Categories: EDA, MunEDA

Right now I’m typing on my MacBook Pro computer connected to the Internet through WiFi, thanks to the electronics in both my laptop and WiFi router. I kind of take WiFi for granted because it is so ubiquitous throughout my daily life, yet there are IC designers at companies like Lantiq Semiconductorthat have to design and optimize for WLAN specifications like 802.11ac by designing RFIC devices. Last month at the MunEDAUser Group meeting in Munich I attended a presentation by Daniel Lopez-Diaz, a senior engineer in the RF design group at Lantiq.

Lantiq was founded over 20 years ago and has grown into a successful fabless company with 800 people, focusing on high-speed broadband, connected home, home automation and voice products. Here’s the big picture showing how everything fits together:

They have a reference board used in WiFi router products with just a handful of highly integrated components:

EASY362 V1.1 Reference Board

The WLAN chip supports the 802.11ac standard, operates on a 5G frequency band, and has RF bandwidths of: 20MHz, 40MHz, 80MHz and 160MHz. These requirements translate into a transmitter with a Power Spectral Density (PSD) that looks like:

Power Spectral Density

Another important spec is the minimum performance as the Error Vector Magnitude (EVM), also called the Relative Constellation Error (RCE) – measured in units of dB:

Error Vector Magnitude (EVM)

The RFIC design team needed to verify the performance over a range of Process, Voltage and Temperature (PVT) conditions to ensure that the WLAN chip would be robust and yield well. Combinations of intra-die and inter-die variation could result in unrealistic process parameters. The approach used by the team was to create an iterative sign-off process using EDA tools from MunEDA called WiCkeD.

Iterative Design Flow

A simplified RF block diagram is shown below with the Transmit Mixer portion highlighted for analysis.

Simplified RF Block Diagram

The Transmit Mixer block has two main specifications:

Conversion Gain (CG) of -3dB, typical
1 db Compression Point (P1dB) of 7 dBm, minimum

At the first design review it was shown that the specifications were not quite met:

[TABLE] style=”width: 500px”
|-
| Case
| Process
| Voltage
| Temperature
| CG
| P1dB
|-
| Initial
| TT
| 1.26V
|
| -2.22 dB
| 10.17 dBm
|-
| Slow
| SS
| 1.2V
| 110 C
| -4.18 dB
| 10.2 dBm
|-
| Fast
| FF
| 1.32V
| 10 C
| -1.62 dB
| 10.77 dBm
|-

Further analysis using Worst Case Distance results instead of corners for Conversion Gain and 1 db Compression Point showed:

[TABLE] style=”width: 500px”
|-
| Case
| Voltage
| Temperature
| CG
| P1dB
|-
| Fast
| 1.32V
| 10 C
| -1.63 dB
| 12.09 dBm
|-
| Slow
| 1.2V
| 10 C
| -4.292 dB
| .5705 dBm
|-

Engineers quickly spotted that with Worst Case Distance analysis the result for P1DB was out of spec, so it meant three possible choices:

[LIST=1]

Re-center the design to meet the spec

Re-size the transistors to meet the spec

Relax the specifications

Conclusions

RF design optimization for a WLAN chip is possible by using a Worst Case Distance approach as found in the WiCkeD tool from MunEDA. Designs can be analyzed for robustness prior to tape-out.

January 1, 2015

IEDM Advanced CMOS Technology Platform Session

IEDM Advanced CMOS Technology Platform Session
by Scotten Jones on 01-01-2015 at 7:00 am
Categories: Foundries, Intel Foundry, TSMC

First I want recognize that IEDM once again provided all of the attendees with the proceedings as soon as we arrived at the conference, in fact the proceeding included every year of IEDM back to 1955. This is how a conference should be run! Anyone who read my blog about the SPIE Advanced Lithography Conference will know how frustrating I found SPIE not making the proceeding available until months after the conference. SPIE really needs to fix that! Being able to read the papers before a session and then review them again after the session is really helpful.

There were three papers in the Advanced CMOS Technology Platform session that really caught my attention this year.

TSMC
First up was TSMC presenting their 16FF+ technology. The process presented this year provides a 15% speed improvement at the same power or a 30% power improvement at the same speed versus the 16FF process presented at IEDM last year. All of the critical dimensions disclosed for this process are the same as 2013 (48nm fin, 90nm gate and 64nm M1 pitches). The level of performance improvement TSMC has achieved is more in-line with what you would see for a new node and to achieve this level of improvement while maintaining the same critical dimensions is really an achievement. Unfortunately from my perspective the paper only discussed the results and didn’t provide any details on how they were achieved other than to say they focused on reducing capacitance. Still the results are impressive!

Intel
The next paper that really caught my attention was the Intel paper on their 14nm technology. Intel’s 14nm technology is the densest 16nm/14nm class process currently available with 42nm fin, 70nm gate and 52nm metal pitches. The gate pitch x metal pitch metric is 0.51x the 22nm technology, IDsat is 15% better for NMOS and 41% better for PMOS. Active power is 30% better than 22nm with 10x better tddb and less Vt variation.

Once again there wasn’t a lot of detail presented about the process but there were a few interesting disclosures:
[LIST=1]

The process uses solid source doping to dope under the fins. My belief is that the STI trenches between the fins are filled with doped glass that is then etched back to the bottom of the fin and then annealed to out-diffuse the dopants. I would expect both p and n doped glasses would be required. I have come up with one integration scheme that does this without additional masks but it would result in topography at the bottom of the wells. I think it is more likely one additional mask would be needed.

Air gaps are used on two of the interconnect layers. Data was presented for delay improvements for metal 4 – 17% and metal 6 – 14%. Interestingly my understanding is that analysis of actual Intel products in the field has found the air gaps on layers 5 and 7. During the presentation it was also disclosed that a mask is needed for each air gap. After the paper someone asked how this is done and author declined to comment. Based on cross sections and the one mask per air gap disclosure it seems likely that this is the process Intel described in 2010.

I was surprised when it was first disclosed that this process has 13 metal layers. Intel used 6 metal layers at 180nm (aluminum) and 130nm (copper), 7 layers at 90nm, 8 layers at 65nm and 9 layers at 44nm, 32nm and 22nm. I was expecting 10 metal layers at 14nm. I think what has happened here is that Intel has moved to SADP for critical metals layers and SADP really only produces gridded lines and spaces for a 1D layout. This has likely required additional metal layers versus previous 2D metal layers.

During the presentation Intel briefly displayed the pitches for all the metal layers. Unfortunately it wasn’t up long enough for me to copy down the numbers and unlike many attendees I respect the no photography rule. The pitches are also not in the paper. I have seen measured pitches on products in the field but I can’t share them yet. I will say that I saw a report on EE Times that the process has 8 layers of 52nm minim pitch metal, it actually has 5 layers of minimum pitch metal.

Intel has previously stated that the 14nm process wafer cost is 29% higher than the 22nm wafer cost. I have a really hard time reconciling that number with all the added masks at 14nm. First there are 8 mask layers required for the additional 4 metal layers, then 2 mask layers for the 2 air gap layers and likely 1 mask layer for the under fin doping. Then there are 1 additional cut mask for fins (2 versus 1 for 22nm), 1 cut mask each at contact and M0 and 10 cut masks for metals M1 through M5. In all I see an approximately 50% increase in both masks and process complexity.

IBM
The final paper I wanted to comment on from the session is the IBM paper on their 14nm technology. Where Intel and TSMC produce FinFETs on bulk wafers IBM produces FinFETs on SOI. The use of SOI enables IBM to integrate eDRAM on the same wafer with only 2 masks (my estimate). eDRAM is much more area efficient for cache than SRAM and with the huge cache sizes required for processors and SOCs eDRAM can save a lot of die area. I believe the IBM eDRAM process only requires 1 mask to form the trench DRAM capacitor and 1 additional mask for a thick gate oxide for the access transistors. The IBM process definitely leads in the complexity category with 15 metal layers and the eDRAM. This process is likely targeted at IBMs internal processors used for high end servers where processor cost is really not much of a consideration. The process pitches are 42nm for fin, 80nm for gate and 64nm for metal. IBM gave the most process details of the three papers with a block level process flow, always a favorite of mine. This is a very impressive high performance process.

Comparison and conclusions
The following table compares the density for the three processes.

[TABLE] align=”center” border=”1″
|-
| style=”width: 133px” |
| style=”width: 120px; text-align: center” | IBM
| style=”width: 114px; text-align: center” | Intel
| style=”width: 108px; text-align: center” | TSMC
|-
| style=”width: 133px” | Gate (CPP)
| style=”width: 120px; text-align: center” | 80nm
| style=”width: 114px; text-align: center” | 70nm
| style=”width: 108px; text-align: center” | 90nm
|-
| style=”width: 133px” | Metal
| style=”width: 120px; text-align: center” | 64nm
| style=”width: 114px; text-align: center” | 52nm
| style=”width: 108px; text-align: center” | 64nm
|-
| style=”width: 133px” | Gate x Metal
| style=”width: 120px; text-align: center” | 5,120nm2
| style=”width: 114px; text-align: center” | 3,640nm2
| style=”width: 108px; text-align: center” | 5,760nm2
|-

A few final observations from this session:
[LIST=1]

To my mind Moore’s law is alive and well not only technologically but I also believe these processes deliver cost per transistor reductions as well. For some of the foundry processes cost reduction is modest at 16nm/14nm because they maintained the same BEOL as previous generations but moving forward to 10nm I expect to see significant cost reductions with a return to full scaling.

Intel has the densest process when measured by the gate x metal pitch metric. What isn’t clear is how an Intel die size would compare to an IBM die size for a die with a large cache. Intel’s SRAM is 0.0588um2 whereas IBM’s eDRAM cell is 0.0174um2 providing a significant potential area saving for cache.

December 31, 2014August 22, 2024

GlobalFoundries did NOT Pull the Emergency Brake!

GlobalFoundries did NOT Pull the Emergency Brake!
by Daniel Nenni on 12-31-2014 at 10:00 am
Categories: Foundries, GlobalFoundries

Barron’s again published an unsubstantiated semicondutor rumor that is making the rounds. It all started with a Christmas day blog by Robert Maire who is a long time semiconductor analyst. Please note that he is not a semiconductor professional (someone who actually works in the industry) but he certainly does know people who do. According to LinkedIn Robert and I have quite a few connections in common and those connections are semiconductor professionals.

SoCs should invest in a strong cache position

SoCs should invest in a strong cache position
by Don Dingee on 12-30-2014 at 4:00 pm
Categories: EDA

Like most technology firms, Apple has been home to many successes, and some spectacular defeats. One failure was Project Aquarius. At the dawn of the RISC era, before ARM architecture was “discovered” in Cupertino, engineers were hunkered over a Cray X-MP/48. The objective was to design Apple’s own quad core RISC processor to speed up the Macintosh.

As if designing an instruction set, execution units, and pipeline is not hard enough, getting four cores to work together is more than simply a matter of cloning and connecting. Continue reading “SoCs should invest in a strong cache position”