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Simply the Highest Performing Cortex-M MCU

Simply the Highest Performing Cortex-M MCU
by Eric Esteve on 02-22-2015 at 11:30 am
Categories: Arm, Foundries

If you target high growth markets like wearable (Sport Watches, Fitness Bands, Wearable medical) industrial (mPOS, Telematics, etc.) or Smart Appliances, you expect using a power efficient MCU delivering high DMIPs count. We are talking about systems requiring a low Bill of Material (BoM) both in term of cost and devices count. Using a MCU (microController) and not a MPU (microProcessor) allows minimizing the power consumption as such device like the SAM-S70 run at the 300 MHz range, not the GigaHertz, while delivering 1500 CoreMark. In fact, it’s the Industry’s highest performing Cortex-M MCUs, but the device is still a microcontroller, offering multiple interface peripherals and the related control capabilities, like 10/100 Ethernet MAC, HS USB port (including PHY), up to 8 UARTs, two SPI, three I2C, SDIOs and even interfaces with Atmel WiFi and ZigBee companion IC.

This brand new SAM S/E/V 70 32-bit MCU is just filling the gap between the 32-bit MPU families based on Cortex A5 ARM processor core delivering up to 850 DMIPS and the other 32-bit MCU based on ARM Cortex M. Why developing a new MCU instead of using one of this high performance MPU? Simplicity is the first reason, as the MCU does not require using an operating system (OS) like Linux or else. Using a simple RTOS or even a scheduler will be enough. Using a powerful MCU help to match increasing application requirements, like:

  • Network Layers processing (gateway IoT)
  • Higher Data Transfer Rates
  • Better Audio and Image Processing to support standard evolution
  • Graphical User Interface
  • Last but not least: Security with AES-256, Integrity Check Monitor (SHA), TRNG and Memory Scrambling

Building MCU architecture probably requires more human intelligence to fulfill all these needs in a smaller and cheaper piece of Silicon than for a MPU! Just look at the SAM S70 block diagram:

The memory configuration is a good example. Close to the CPU, implementing 16k Bytes Instruction and 16k Bytes Data caches is well-known practice. On top of the cache, the MCU can access Tightly Coupled Memories (TCM) through a controller running at CPU speed, or 300 MHz. These TCM are part of (up to) 384 Kbytes of SRAM, implemented by 16 Kbytes blocks and this SRAM can also be accessed through a 150 MHz bus matrix by most of the peripheral functions, either directly through a DMA (HS USB or Camera interface), either through a peripheral bridge.

The best MCU architecture should provide the maximum flexibility: a MCU is not an ASSP but a general purpose device, targeting a wide range of applications. The customer benefit from flexibility when partitioning the SRAM into System RAM, Instruction TCM and Data TCM as you can see below:

As you can see, the raw CPU performance efficiency can be increased by smart memory architecture. But, in term of embedded Flash memory, we come back to a basic rule: the most eFlash is available on-chip, the easier and the safer will be the programming. The SAM S70 (or E70) family offers 512 Kbytes, 1 MB or 2 MB of eFlash… and this is a strong differentiator with the direct competitor offering only up to 1 MB of eFlash. Nothing magic here as the SAM S70 is processed on 65nm when the competition is lagging on 90nm. Targeting a most advanced node is good for embedding more Flash, it’s also good for CPU performance (300 MHz delivering 1500 DMIPS, obviously better than 200 MHz) and it’s finally very positive in term of power consumption.

In fact Atmel has built a four mode strategy to minimize overall power consumption:

  • Backup mode (VDDIO only) with low power regulators for SRAM retention
  • Wait mode: all clocks and functions are stopped except some peripherals can be configured to wake up the system and Flash can be put in deep power down mode
  • Sleep mode: the processor is stopped while all other functions can be kept running
  • Active mode

If you think about IoT, the SAM S70 is suited to support IoT Gateway application, but this is only one of the many potential usages of this device able to support wearable (medical or sport), industrial or Automotive (in this case it will be the SAM V70 MCU, offering EMAC and dual CAN capability on top of S70).

Product line presentation on Atmel portal: SAM

or:
http://www.atmel.com/products/microcontrollers/arm/sam-s.aspx

From Eric Esteve from IPNEST

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Analyzing Power Nets Early and Often, a New White Paper

Analyzing Power Nets Early and Often, a New White Paper
by Paul McLellan on 02-22-2015 at 7:00 am
Categories: EDA, Silicon Frontline

One of the big challenges in designing ICs today is designing a robust power net capable of delivering necessary current levels to all areas of the die. Getting it wrong can, of course, lead to circuit failures that range from non-functional silicon, through intermittent performance and functional problems, to early EM-driven failures. Designers carefully perform accurate power net analysis before tapeout. However, finding problems this late in the design cycle can result in schedule slips if anything more than a trivial fix is required.

Large SoCs have complex and widely-distributed power nets, but since most of them are constructed by automated place and route they tend to have fewer late issues. They also are less amenable to early analysis since every time the design is re-placed pretty much everything changes. Furthermore, with 10 or more layers of metal, some of which are very low resistance, the problem is just not so acute.

But analog/mixed-signal ICs, memories and image sensors have many fewer layers of metal, and sometimes these are narrower (by design necessity) and of lower quality (higher resistance) materials. In addition, often these designs use complex non-orthogonal routing of power nets, which can complicate extraction and analysis for some verification tools. Obviously, eventually the power has to get down to the transistors and as a result power often has to be distributed at least partially on low levels of metal. But these low levels of metal are narrower and so resistance is more of an issue.

This is where Silicon Frontline’s P2P (which stands for “point to point”) comes in. It allows for extremely fast analysis of power nets very early in the design. It can even start to give preliminary analysis before the layout is complete. It does an accurate calculation of the resistance between any two points or groups of points (hence the name) with various resistance-map displays that allow the designer to quickly zoom into the issues where the resistance is very high (just look for the bright red regions in a sea of blue).

The tool is very easy to configure, very fast and has essentially unlimited capacity. Where the tool really shines is on analog/mixed-signal, memories, image sensors and other designs where the power nets, because of their complexity and all-angle shapes, often require manual intervention. The resistance mapping mode of P2P can be used on incomplete layouts, or during layout development in the architecture and partitioning stage of design. And then, when the design is complete and P2P resistance mapping has been used to ensure that all power nets are low resistance and any simple problems have been fixed, the designer can perform detailed IR drop and electromigration (EM) analysis with a good candidate design. If all resistances are low then IR drop will be low (or lower) by definition and typically EM is less of an issue too, since low resistance metal tends to be wider.

A new white paper is now available that covers P2P in detail including an example of its use to track down some errors in the design and take a power network from a resistance of 30 ohms, way too high, down to a resistance of just over 3 ohms in a matter of minutes.

The white paper can be downloaded here.

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IoT Sensor Node Designs Call for Highly Integrated Flows

IoT Sensor Node Designs Call for Highly Integrated Flows
by Tom Simon on 02-21-2015 at 7:00 pm
Categories: Arm, Cadence, Coventor, EDA, IoT, Mobile, TSMC

Applications for IoT sensors are becoming more sophisticated, especially for industrial usage. Building optimal sensors for different applications requires multi-domain design, optimization and verification flows. The sensor devices are usually MEMS, and as such have electrical properties that need to be tailored to the analog circuitry they are connected to. Many MEMS devices are not completely passive: they often have drive systems to keep them in their most linear range of operation. For example an accelerometer will have two comb capacitors, one is for sensing, the other is to control the proof mass.

Cadence, Coventor and ARM recently held a webinar that showed how many important considerations in designing an industrial IoT sensor node can be addressed. The full session is available here.

In these designs the analog circuity needs to be designed and optimized at the same time as the MEMS structures. Chris Welham, Worldwide Applications Engineering Manager at Coventor, points out in the webinar that Coventor offers their MEMS+ product as a vehicle for building 3D design of MEMS elements in conjunction with circuit design tools. The key to making this effective is that after the MEMS designer creates a device, they can export it to Cadence, where it is represented as a parametric simulation model, symbol and PCell. The parameters exposed to the circuit designer are specified when the MEMS+ model is generated. This means that the circuit designer can alter specific parameters of the MEMS device easily and independently. In the webinar Cadence showed how Virtuoso ADE GXL can be used to concurrently optimize the circuit and MEMS parameters to meet the system design spec. The PCell that is produced by MEMS+ produces the necessary layout for mask generation.

IoT sensors need to be compact, rugged and have battery life considerations. These needs often drive the specific packaging configuration for the various SOC’s and MEMS chips in the unit. Designers can utilize BGA, bond wires and TSV’s in an assortment of configurations that can include stacked die with silicon interposer. In the webinar Ian Dennison, Solutions Group Director at Cadence, shows examples of each of the 3D-IC approach alternatives and highlights design and verification aspects of each.

For designs with bond wires, stacked die present special challenges. Manufacturing and coupling noise considerations play a major role in wire placement and shape. Cadence SIP allows wire profiles to be defined and then viewed in 3D. The webinar showed several examples where wire profiles need to be configured to provide adequate clearances to avoid things like overhanging shelves or neighboring wires.

TSV’s offer many advantages over bond wires, but working with them adds complexity to the chip design process. First off, on the plus side, TSV’s reduce overall system cost. On-chip they save routing resources that would otherwise be needed to get signals to the chip boundary and they lower parasitic capacitance and inductance. However the chip floorplan must account for their location. In the webinar Cadence discussed how Encounter and Virtuoso let designers work with TSV’s.

Tim Menasveta, CPU Product Manager at ARM went last but covered the critical aspects of how creating a sensor hub in the IoT sendor device can help the IoT senor meet its many design requirements. Without a hub, all the raw sensors would be transmitting to the aggregation point continuously. This wastes power and bandwidth. Instead with a local processor the IoT sensor node can decide when and what data should be sent. Additionally sensor fusion is extremely important. Many of us are familiar with the necessity of combining the raw inputs from a gyroscope and accelerometer to obtain accurate real world results. Also temperature is an important input for most sensor interpretation. Sensor fusion is useful for dealing vibration or effects of nearby iron objects when calibrating a compass.

The new Cortex-M7 boasts an improved DSP and floating point unit when compared to its predecessor the Cortex-M4. The M7 is ideal for bare metal code. The M8 is more suitable for higher level OS’s. There is also an optional double precision floating point unit available for the M7. To facilitate development of designs using the Cortex-M7, Cadence and ARM have collaborated on an implementation reference methodology built on TSMC’s 40LP process. This design uses Physical IP by the ARM Physical IP Division. It is a low power design that has support for power gating.

The webinar pulled together a wide range of technology, all of which is necessary for putting together leading edge IoT sensor based designs. For a more in depth review of the technology,I suggest following the link at viewing it.

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The PTAB Inter Partes Review process: Danger, Will Robinson

The PTAB Inter Partes Review process: Danger, Will Robinson
by Scott Griffith on 02-21-2015 at 7:00 am
Categories: IP

Companies with significant investment in their patent portfolios have recently faced a harsh reality: their intellectual property has become a collection of paper with large targets on them. Taking aim is the US Patent and Trademark Office’s Patent Trials and Appeal Board (PTAB), and recent figures on dismissed claims shows that the Board’s aim is not only true, but often deadly.

Since the September 2012 onset of the Leahy-Smith America Invents Act (AIA), the PTAB has earned a troubling reputation of being a “death squad” for patents that come under its review.

In the article “Inter Partes Review Initial Filings of Paramount Importance: What Is Clear After Two Years of Inter Partes Review under the AIA”, Michael McNamara and Patrick Driscoll of Mintz Levin extracted some jarring statistics from the first 24 months of IPR proceedings. Here is what the raw data of PTAB actions as of 9/4/14 showed. Of 11,046 claims in 348 petitions presented:

· 5,045 claims were challenged, 6,001 not challenged
· 3,344 claims instituted from 237 Petitions, with 66% challenged
· 1,701 claims challenged but not instituted, with 34% of claims challenged

Of the 3,344 claims instituted:

· 999 claims were found unpatentable
· 606 claims were cancelled or disclaimed during the proceedings
· 1,739 claims were found patentable

On the surface, the results would appear to represent a 48% chance of a given claim failing to survive once the review is instituted. However, as McNamara and Driscoll point out, this is somewhat misleading, and the results for patent owners may be even grimmer. Taken on a per-petition basis, 66 proceedings reached decisions on patentability. That is a small number for statistical analysis, but the results should still give patent owners and their attorneys pause. Of the 66 cases:

· 6 cases resulted in all claims found patentable (9%)
· 10 cases resulted in a mix: some claims patentable, some unpatentable (15%)
· 50 cases resulted in all claims found unpatentable (73%)

The PTAB has actively tried to combat the perception that is has an agenda to find claims unpatentable. However, the unavoidable conclusion has to be that few patents survive completely unscathed once a review is instituted.

In the months following the period that McNamara and Driscoll studied, the pace of filings has increased. In fact, December 22, 2014 saw an all-time high of 28 petitions filed in a single day. The ongoing statistics to February 15, 2015 show the continuing patterns, from 20,206 claims in 617 petitions:

· 9,048 claims were challenged, 11,158 not challenged
· 6,114 claims instituted from 425 Petitions, with 68% challenged
· 2,934 claims challenged but not instituted, with 32% of claims challenged

Of the 6,114 claims instituted:

· 2176 claims were found unpatentable
· 893 claims were cancelled or disclaimed during the proceedings
· 3,045 claims were found patentable

Source: USPTO

At the time of writing, results on a per-petition basis from 9/4/2014 to 2/15/2015 has not yet been completed. However, the chance of a given claim failing to survive remains on the order of 50 percent. The initial evidence suggests that the trend remains essentially unchanged at best, and could even be worsening. In the final analysis, the chances of a given patent surviving unscathed will very likely continue to be on the order of 10 percent at best. Poor odds, indeed.

The news is of particular importance in computer technology and, specifically, the semiconductor industry. As of February 5[SUP]th[/SUP], 2015, the vast majority of AIA petitions for fiscal year 2015 — 68.3%, or 432 petitions — addressed TCs 2100, 2400, 2600, 2800, or electrical, electronic, and computer areas.

Furthermore, we at Micro Methods have noted an increased number of petitions filed by major semiconductor manufacturers against Non-Practicing Entities (commonly known as “patent trolls”, thanks to Intel) since roughly October of 2014. It would appear that some of the major players in our industry have begun to see that the IPR process might well be precisely the blunt instrument needed to respond to a lawsuit filed against them by a patent troll. This can be very effective as a strategic move, as quite often the initial court case can be stayed pending the results of any PTAB action.

This trend certainly deserves further study. As McNamara and Driscoll conclude, “…a petitioner’s best strategy is to ensure that a review is instituted, while a patent owner’s best defense against an IPR is to make certain that one is not instituted in the first place.”

The message has become clear to those subject matter experts who support Inter Partes review efforts. As Cyrus Morton and David Prange of Robins Kaplan LLP point out in their article “Surviving Inter Partes Review: Good Experts Are Key”, experts must redouble their efforts to provide unassailable detail and basis for any opinions, and be prepared to comprehensively rebut each and every argument of the opposing side, whether retained by the petitioner or the owner. The stakes are high, and the PTAB has been very consistent in its willingness to find less-than-perfect expert testimony unpersuasive, often with disastrous results for the patent owner.

Scott Griffith is a Member of Micro Methods LLC, a group of Subject Matter Experts committed to excellence and unerring accuracy in providing semiconductor focused Intellectual Property services for our multinational client base.

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SPIE Advanced Lithography Preview

SPIE Advanced Lithography Preview
by Scotten Jones on 02-20-2015 at 1:00 pm
Categories: EDA, Foundries

Next week is the SPIE Advanced Lithography Conference in San Jose, the premier conference for advanced lithography used to produce state-of-the-art semiconductors. Last year I blogged after the conference about some of the key points I heard at the conference and this year I plan to do the same.

Last year’s blog is available HERE:

One of the things that really struck me last year was how pessimistic the general mood was about EUV and how optimistic the people I spoke to were about the extendibility of multi-pattering. In the last year it seems to me that EUV has picked up some momentum so I am very interested to see what the general tone is about EUV and multi patterning.

I have been going through the program for the conference looking for sessions I want to attend.

Monday morning and early afternoon have some interesting sessions on EUV and multi patterning that look like they will address the issues I spoke about above. There is also some interesting etch session papers in the afternoon.

Tuesday morning will see the EUV sources addressed. The output of the EUV sources is a key gating item for high volume usage of EUV so this will be an important session. Nikon will also discuss their non EUV roadmap, Nikon is no longer working on EUV and instead focused on 450mm ArFi. There are also interesting sessions on directed self-assembly (DSA) and negative tone develop (NTD). I am hearing that DSA has been used to make DRAMs and may be close to at least partial implementation so it will be interesting to see what is presented. NTD is also a technique that is seeing growing usage for ArFi layers with dark field masks. Tuesday afternoon will feature more interesting sessions on EUV and DSA.

Wednesday morning includes more interesting DSA and etch presentations as well as multi-patterning presentations. Wednesday afternoon features a couple of interesting papers on multi-beam e-beam lithography.

Thursday warps the conference up with additional papers on EUV systems and processes for sub 10nm resolution.

Stay tuned for my post conference blog on what I see and hear at the conference.

About SPIE, the international society for optics and photonics, was founded in 1955 to advance light-based technologies. Serving more than 256,000 constituents from approximately 155 countries, the not-for-profit society advances emerging technologies through interdisciplinary information exchange, continuing education, publications, patent precedent, and career and professional growth. SPIE annually organizes and sponsors approximately 25 major technical forums, exhibitions, and education programs in North America, Europe, Asia, and the South Pacific. SPIE provided $3.4 million in support of education and outreach programs in 2014.

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Synopsys Earnings Call Q1 2015

Synopsys Earnings Call Q1 2015
by Paul McLellan on 02-20-2015 at 7:00 am
Categories: EDA, Synopsys

Synopsys announced their results yesterday. Their 2014 already ended, this is the end of their fiscal first quarter. On the call were Aart, one of Synopsys’s two co-CEOs, the other being Chi-Foon Chan; and Trac Pham, the new CFO on his first earnings call.

Synopsys’s results were good. A quick look at the results. Revenue was $542M so comfortably above a $2B/year run-rate. Non-GAAP EPS was $0.80. They also raised future guidance. They see the environment as solid.

But as usual my interest is not so much short-term financial measures but discerning longer-term trends in things like process, foundry availability, sea-changes in EDA methodology and so forth.

“The number of active FinFET designs and tapeouts to date grew nearly 15% in just the last quarter, to almost 200. The breadth of our FinFET proven tools and IP gives us a notable competitive advantage, as evidenced by Synopsys being relied on for approximately 95% of these designs.”

I think “relied on” is just a wiggle word meaning that they used a lot of Synopsys tools, but since they probably also used Virtuoso and Calibre, I think Cadence and Mentor could say they were “relied on” too. Also, designs and tapeouts “to date” grew to 200, not just last quarter.

“We’ve taped out more than 30 FinFET chips.” So with the previous bullet, that means there are 170 FinFET designs in progress, around 30 of which started last quarter.

“We’re engaged in numerous 10 nanometer partnerships with early adopters”. “Through our TCAD technology, we’re already collaborating with silicon providers and research consortia such as imec on 5 nanometer and 7 nanometer.” One key question is whether FinFETs will work at 7nm or whether we will need to go to gate-all-round or some other technology.

“Our flagship VCS functional verification product is the primary simulator for 80% of advanced designs.” That is a big percentage, given that both Cadence and Mentor also have credible offerings in the same space.

“Synopsys is the number one supplier of interface, analog, memory, and physical semiconductor IP.” In fact they are the #2 supplier of IP behind ARM.

“Our HAPS FPGA-based prototyping solution does just that, and has proven itself in the marketplace. Q1 was its highest revenue quarter ever, and with more than 5,000 HAPS systems installed at customers today.” Later Aart said that this was being driven by the needs of software development. “The challenge with that is of course that the software guys would like to start modeling and trying out their software before the chips are ready.”

There were a couple of questions about IC Compiler II which Aart characterized as growing market share. But Cadence also talked about digital design as an area where they were investing additional resources and also growing share. Aart said that some of this is just the Lake Wobegon effect “EDA is the industry where all the children are always above average, and all the share gains are above average.”

“The Coverity integration of infrastructure and sales has gone well, and our initial financial expectations are on track. We saw 32 new logos in the quarter, and executed an important agreement with a large, U.S. energy company.” Coverity is used for analysis of software especially in safety and security critical applications. Analysts reckon this area is growing at around 20% per year. In the questions Aart said they were on-track to be profitable in the second half of this year and over $100M in 2016.

“One customer accounted for over 10% of revenue”. Everyone knows it is Intel. It is a big number since 10% revenue last quarter is over $54M.

“We ended Q1 with approximately 9,300 employees, with more than one-third in lower-cost geographies.”So over 3100 employees in India, China and other similar countries. “You can see that the headcount did decrease from Q4 to Q1. A large portion of that was due to the voluntary retirement program and the small layoff we had, but also the delayed hiring.”

There is a lovely transcription error in one of the questions which talks about moving from the “plainer world to FinFETs”. I think I’m going to start calling “planar” transistors “plainer” from now on. Those FinFETs are so exciting for EDA.

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FinFET Designs Need Early Reliability Analysis

FinFET Designs Need Early Reliability Analysis
by Pawan Fangaria on 02-19-2015 at 9:30 pm
Categories: Ansys, Inc., EDA

In a world with mobile and IoT devices driven by ultra-low power, high performance and small footprint transistors, FinFET based designs are ideal. FinFETs provide high current drive, low leakage and high device density. However, a FinFET transistor is more exposed to thermal issues, electro migration (EM), and electrostatic discharge (ESD) compared to a planar FET. A higher current in FinFET transistor leads to local self heating and a significant increase in substrate temperature. Since the active area in a FinFET is covered by field oxide on three sides, the generated heat is trapped inside. The heat slowly dissipates towards the substrate, thus increasing the substrate temperature. This can lead to domino effect in case of interconnected systems. With high current drive capability of FinFETs, the overall current density of metal interconnects also increases, thus increasing the heat all over. An increase of temperature by 25[SUP]o[/SUP]C can degrade the life of a device by 3x to 5x.

Similarly, with technology scaling the margin between nominal voltage and breakdown voltage of a device is significantly reduced. This leaves very thin operating window for ESD. Also, a FinFET device has very poor snap-back characteristic. Read “Full Chip ESD Sign-off – Necessary” for more details about ESD in devices. Interconnects can be equally vulnerable to large current crowding due to an ESD event.

Considering the FinFET devices to be more prone to such effects which can render them to short-term as well as long-term risks of failure, an SoC design based on FinFET technology nodes cannot be left for EM and ESD sign-offs at the end of the design cycle. It’s advisable to do thermal, EM and ESD analyses of a design as it progresses from very early stages until completion.

RedHawk from ANSYSprovides a thermal-aware EM analysis platform that can be used as the design progresses. Power and signal EM analyses can be performed at non-uniform temperatures for different metal layers. Temperature profiles generated from ANSYS Sentinel-TI can be annotated on to the RedHawk layout to re-compute the true thermal aware EM violations. This capability is perfect for FinFET based designs which exhibit large variation of temperature across the chip. A detailed description about how Sentinel-TI utilizes RedHawk created CTM (Chip Thermal Model) and analyzes chip-package thermal impact due to leakage and self-heat is provided in a technical paperat techonline website. It also describes about ANSYS Icepak which can be used for system-level thermal analysis.

ANSYS PathFinder provides ESD planning, verification and sign-off solution for full-chip SoC as well as IP. It utilizes a simulation based methodology that accurately identifies current density issues and appropriately places diodes and clamps to resolve current bottlenecks in case of an ESD event. An accurate ESD device modeling, flexibility to handle different scenarios and user-friendly debug environment helps designers find route causes for design weaknesses and take appropriate action. Read the technical paper for actual details on ESD analysis and handling.

The paper also describes about different approaches utilized for different types of IP such as standard cell libraries, analog and mixed-signal, I/Os, sensors, PMICs, memories, and so on. For example, Vectorless approach that exercises all nets with accurate switching behavior can be best utilized for a comprehensive EM coverage on power and signal nets inside standard cells. Similarly ANSYS Totem can be used for complex IP such as high-speed I/O, image sensor, and so on.

Today, FinFET node is entering mainstream for IC manufacturing. This expresses the acute need for reliability analysis to become an integral part of the design flow. In order to meet aggressive time-to-market window, the reliability analysis must start as early as possible in the design flow and sign-off at the end for a faster design closure.

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Mentor and ASSET Intertech Do a DFT World Tour

Mentor and ASSET Intertech Do a DFT World Tour
by Beth Martin on 02-19-2015 at 1:01 pm
Categories: EDA, Siemens EDA, Uncategorized

The Mentor Graphics test folks and ASSET Intertech have teamed up to provide a series of free DFT seminars in the US, Europe, and Asia. The first one is in Austin, TX on February 19, 2015, and the last is in Tokyo on April 24. Hereis the full list of locations and dates.

The morning session covers IJTAG. The new IEEE 1687 Internal JTAG (IJTAG) standard is changing the way the industry validates, tests and debugs chips and circuit boards. IJTAG-based methods are more cost-effective, more accurate, faster and less time-consuming for you. IJTAG’s software-driven tests and validation routines are initiated from instruments embedded inside chips providing key benefits from a silicon or board perspective based on the type of problems you are trying to solve. This seminar will highlight the synergy between Mentor and ASSET tools and how the IJTAG ecosystem that they provide will accelerate adoption of this technology. Don’t miss the chance to learn how to tap into this useful IP.

Related — IJTAG was recently ratified by the IEEE-SA standards board. Its a bouncing baby IEEE standard!

Who should go?

  • DFx Engineers who need to insert the IJTAG networks and gain the benefits of accessing IP within the silicon.
  • Board Designers who want to gain the benefit of enhanced board validation and test features accessed by IJTAG.
  • Test Managers who want to improve their overall test process and resolve test challenges that cannot be addressed with current test technologies.

Following a delicious lunch, the afternoon seminar is all about the next big thing in test compression—EDT Test Points. Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This session will begin with a review of leading-edge test compression features and techniques and will then introduce and focus on an exciting new technology, called EDT Test Points, which has been developed specifically to work with embedded compression to further reduce pattern volume for compressed patterns. Numerous customer beta engagements have shown that EDT Test Points can reduce compressed pattern counts on an average by a multiplicative factor of 2-4X, without affecting test coverage, and even for designs with the most aggressive embedded compression configurations.

Related — Daniel Payne recently wrote a very good article on EDT Test Points, More Test Points are Better

Who Should Attend?

  • Designers, DFT engineers, and test consultants involved with creating testable ICs and producing the manufacturing test sets
  • Product engineers responsible for manufacturing test of ICs
  • Test managers looking to minimize manufacturing test costs while maintaining or improving test quality

Registernow for an ASSET InterTech and Mentor Graphics DFT Technology Seminar near you!

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Earnings Calls: Behind the Scenes

Earnings Calls: Behind the Scenes
by Paul McLellan on 02-19-2015 at 7:00 am
Categories: General

Last weekend I wrote about the Applied Materials earnings call. And over the last couple of years I’ve written about lots of other earnings calls. Most people have never been on an earnings call, I mean in the conference room where the call is being conducted, not just listening. So I thought it might be interesting to describe how it actually goes down.

When I was at Cadence I was part of the investor relations team in that I was the technical person that they would arrange meetings with if an analyst came by and wanted to discuss technology. The main investor relations people could talk about the company finances but knew little about technology. I was the house-trained technologist who could be trusted not to pre-announce a product or say something that I wasn’t meant to. In fact the analysts actually knew very little about technology in most cases, and were out of their depth if I went too deep into anything. I think they just wanted to try and assess whether we were ahead of Synopsys by looking someone (me) in the eye, and also learn a few new buzzwords so they could sound smart when they asked questions on earnings calls.

You generally only hear 3 people talk on the earnings call. The head of investor relations who introduces the call and reads the safe-harbor statement. The CEO of the company who usually goes next and gives some color to the quarter with the headline financial results, which all the analysts already know since the press release went out 30 minutes prior to the call. Finally the CFO who will give more detail of the finances, cash-flow, capital investment, headcount and so on. Then the interesting part begins when the CEO and CFO have to answer questions.

So you might assume that there are just 3 people in the boardroom when the call takes place. Actually, at least when I was at Cadence, we would have another half-dozen or more people. Another investor relations person learning the ropes, maybe someone else from finance. Since the CEO Ray Bingham was from finance and not technology we would have several of us on hand to handle technical questions. We didn’t actually answer them, of course, we trained Ray so he could answer them. Our job was to make him look good. One challenge was that the boardroom had a top-of-the-line phone system with microphones hanging from the ceiling so on a call anyone in the room could speak and be picked up. On an earnings call this was a disadvantage since it means that nobody could speak, however quietly.

The CEO and CFO’s statements have been word-smithed to death over the preceding few days and so provide a very controlled perspective of the company’s business. The interesting stuff happens in the questions when there is no script. If it were a financial question Ray, or Bill Porter the CFO, would answer. If it was technical or product related then Ray would stall for time for a few seconds while we wrote talking points on a white-board and he would then take those bullet points and run with them. That way we made it look like he knew a lot more about the underlying technology than he really did.

With Regulation-FD (fair disclosure) anyone has the right to listen to an earnings call. This regulation was passed to stop the practice prior to 2000 of giving market-moving information to a select few (typically large institutional investors) before it became generally public. In those days, you wouldn’t be able to get on a conference call if you weren’t a professional investor or analyst.

So now even you can get on the call. But don’t expect to get called on to ask questions, that will be limited to analysts who already have a relationship with the company since their opinion has a broad reach (aka affects the stock-price). I prefer to read the transcripts than to listen. I usually skim the CEO and CFO’s statements since they are not going to contain any surprises. It is the question and answer session where interesting stuff gets conveyed and maybe something off-message gets said. I’m not interested in the financial stuff in general so I skip questions about next quarters cash-flow or tax-rate. The questions about product are always interesting. Fabless companies and manufacturing equipment companies often let out details of foundries that the foundries themselves do not. After all, if a volume manufacturing ramp pushes out, these are the first people to know and it is often material to their business so they cannot say nothing at all.

A good place for listening to recordings of calls are reading transcripts is SeekingAlpha here.

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Mentor shows post-PC industrial device approach

Mentor shows post-PC industrial device approach
by Don Dingee on 02-18-2015 at 9:00 pm
Categories: EDA

The term “human machine interface” originated from the factory floor. In the context of HMI, machine refers not to the computer, but to a machine tool or other instrument the computer was attached to. For decades, if an HMI was needed, it was implemented on a PC or single-board computer running Microsoft Windows. Real-time processing often came from dedicated processors running an RTOS, or microcontrollers running code on bare metal, elsewhere in the system.

Each side wanted what the other had. The PC guys tried to incorporate elements of real-time control, using virtualization techniques to guest an RTOS on Windows. The real-time guys tried to add graphics capability. In some situations, these approaches worked, but the integration was somewhat fragile. This was especially true when integrating graphics on an RTOS. The GPU market on Windows PCs moves so quickly, it was hard to keep from being eaten by obsolescence on a unique chip and driver with limited support.

Speaking of fragile, the evolution of Windows caused problems. In the age of Windows NT, things were pretty good: it integrated with enterprise networks and management tools, it was stable, and developers liked it. Windows 7 was a hot mess of instability, resulting in the Windows Embedded Standard 7 fork to tailor out unneeded pieces. Windows 8 brought issues with a new presentation layer and changes to administration. As a result, many HMI applications tried to stay on Windows NT – until the bitter end, when it was recently end-of-supported. A few went the Windows Embedded Compact route, trying to capture near-real-time needs. Again, some of that worked, but some are still looking for a more modern solution.

This is the post-PC era. A single multicore SoC can now handle what it used to take several boards worth of computers to do. Cores can be dedicated to real-time, or networking, or user interface, or a thread-optimized approach can be used. High performance mobile GPUs can handle most HMI needs. A powerful device can be built around a single SoC.

What operating system should run on a multicore SoC in industrial automation? Linux? Certainly a DIY option, but it doesn’t exactly handle real-time control all by itself. Android? An apps-based strategy might be cool, but again stability and robustness is a question. RTOS? Super for control, but IT guys and OT guys don’t see eye to eye on deployment. And, what is the right graphics approach? How is connectivity handled?

Just as multicore SoCs are heterogeneous, what best fits industrial automation is a heterogeneous OS that blends all these environments into a single framework.


Mentor Embedded has created that industrial automation framework. They have taken all their knowledge about multicore SoC software development and debug, combined it with their knowledge on multicore OS virtualization, added their RTOS and Linux and Android experience, and pulled graphics, safety, and connectivity from the industrial ecosystem. We’ve covered the Mentor Sourcery software development tools recently, but several new pieces in the industrial automation context merit discussion.

First is their selection of Qt. There is no better choice for a cross-platform, open source user interface development framework. Many developers are already familiar with it from mobile apps space. It natively supports OpenGL to run on a mobile GPU, or has a Quick 2D renderer plugin. It has charting and data visualization capability. It has a pre-packaged virtual keyboard, and a library of common controls like gauges, buttons, dials, and other user input and display items.

Image courtesy Mentor Embedded and Digia plc
Qt is a registered trademark of Digia plc and/or its subsidiaries

The next news here is the Nucleus RTOS is now IEC 61508 certified for safety-critical use. Also, Mentor has obtained Wurldtech Achilles Communication Certification, a cybersecurity specification becoming a checklist item for industrial control.

Another interesting area is the top of the stack. Mentor has teamed with Softing to get much of the connectivity, such as Fieldbus, Ethernet/IP, and an OPC UA toolkit. The thing with many industrial automation applications is they enter a brownfield, with legacy protocols already deployed. Having legacy interfaces side by side with modern industrial IoT wired and wireless capability is a big plus.

Finally, there is the enterprise integration aspect. Mentor has worked with Icon Labs on the Floodgate family of solutions. Floodgate Defender provides an embedded firewall with stateful packet inspection, rules- and threshold-based filtering to help secure networks. Icon Labs is also integrating with McAfee ePO, providing policy-based endpoint management.

As Mentor demonstrated at the recent 2015 ARC Industry Forum, this all rolls together nicely:


The combination of a multicore SoC with this Mentor Embedded industrial automation software solution allows small, safe, and highly functional industrial devices to be built. Designers creating SoCs for industrial automation environments should consider this suite of software when evaluating designs, rather than just verifying under Linux. Mentor Embedded has the tools and knowledge to assist designers in constructing their solutions.

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