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Makers get access to Intel RealSense

Makers get access to Intel RealSense
by Don Dingee on 01-08-2015 at 11:00 pm

One of the great devices in maker lore is the Polaroid 6500 Series Sonar Ranging Module. It was originally part of the autofocus system for their SX-70 cameras circa 1978, long before through-the-lens optical autofocus sensors were perfected. Back then, people couldn’t focus. Dr. Land thought he was teaching people to compose images, not just point and shoot. Earlier models of the SX-70 with a focusing view screen enhanced by a rangefinder prism were producing too many fuzzy pictures. The ranging module bounced ultrasound off the primary subject and focused accordingly, even in low visible light.

Polaroid wanted to reduce costs and stimulate applications for the technology. In kit form with an ultrasonic transducer and a small logic board, the 6500 Series measured distances from 6 inches to 35 feet. This gave makers working on toys, robots, and other ideas an easy way to remotely measure distance from the perspective of the host.

Here it is 2015, and guess what? People still can’t focus, even though there are more pictures being shot on smartphones and tablets than ever. There is nothing worse than taking a picture of a critical, once-in-a-lifetime moment and finding out the shot is out of focus. More accurately, the subject of interest is out of focus in the scene – the camera usually decides to focus on something, sometimes not what you wanted. Photoshop can work some miracles with unsharp masks and Smart Sharpen, but too little detail or too much shake and the image is toast. Image stabilization and other computational photography techniques help a lot.

Intel showed off quite a few buzzworthy demos at CES 2015. One was bringing RealSense back for a longer look, with more details after a slight tease at last year’s event and several Jim Parsons commercials over the recent holidays. There are two keys to RealSense technology: the 3D imaging subsystem, and the algorithms behind them.

There are erroneous reports it is a 3D camera (and Intel even calls it that for simplicity, hoping nobody would notice). Smartphone enthusiasts may recall that craptastic fad from just a couple years ago, stereoscopic optical images from dual lenses. Amazon also got the 3D label with the dynamic perspective sensor system on the Amazon Fire Phone, which uses four front-facing cameras plus infrared LEDs to sense how a user is holding and looking at the device and adjust the display.

Intel RealSense goes much farther than either. It uses three physical pieces to capture images: a normal optical imager, an infrared laser projector, and an infrared imager. RealSense actually scans the entire scene up to 30 meters away in infrared, measuring distances from the optical sensor to each pixel, and with some computation the real-world dimensions between pixels in the scene. A closer comparison is Microsoft Kinect, which uses the same basic tactic of infrared scanning and 3D reconstruction, but only up to 4m.

Distance does wonderful things. It allows computational refocusing of an image, since the depth is known across the scene. It also allows gesture recognition, even emotional analytics, in a far more advanced way than just a 2D digitized set of pixels can convey. It also powers drones to recognize and avoid objects, again not just a blob of pixels in a scene but a known object with position, vector, and velocity.

RealSense also allows real-time extraction of objects from a scene. For instance, I could replace the background for a video chat shot in my office with something more interesting, like seats on the 3B line at Angel Stadium of Anaheim.

Just as Amazon and Microsoft have done, Intel has an SDK for developing RealSense applications. It is broken into three parts: a front camera suite for gestures and interaction, a computational photography suite for photo processing, and a coming-soon rear camera suite for augmented reality and other ideas. They support Windows 8.1, and claim to need a 4th Generation Intel Core Processor to have enough horsepower for running the SDK effectively. They are also offering a standalone RealSense camera kit, manufactured by Creative.

We’ve come a long way since the chirpy Polaroid kit. We’ll see if RealSense catches on, gaining support in smartphones and tablets. In the meantime – makers, away.


Tizen to connect Samsung’s world – Can it set new equations?

Tizen to connect Samsung’s world – Can it set new equations?
by Pawan Fangaria on 01-08-2015 at 7:30 am

The USA has very good culture of demonstrating new innovations in every industry by way of conferences, exhibitions, workshops, large meetings and so on. The Consumer Electronic Show (CES) is one of its kinds which exhibit new electronic products that tell about which way the industry is heading. Electronic products are final outcome of semiconductor industry and hence CES clearly tells about the strategic directions of semiconductor industry. After bloggingabout my observations of last year and foreseeing 2015 to be pivotal for new emergence of semiconductor landscape, I was remotely reading about the developments in CES 2015. And as expected, I could see IoT related and connected devices in consumer space in the limelight.

The South Korean tiger, Samsungis betting big on its Tizen O/S to make all of its devices internet ready starting with smart homes and smart automotives. They unveiled smart TV powered by Tizen software which will run on all web-connected models in 2015. They demonstrated curved UHD (higher definition than 4K) TVs which will be powered by content from 20[SUP]th[/SUP] Century Fox. The TV is added with a nanocrystal semiconductor layer for brighter screen and better color appearance. With TV package of channels being delivered over internet, any video or movie while being viewed on a Smartphone can be easily switched TV and vice versa. Samsung debuted Milk VR, a virtual-reality video app, exclusively for its device Gear VR. It will expand Milk Music and Milk Video to its smart TVs.

Chef Collection app was another charmer that provides recipes and tips from expert chefs and will be available from Google Play. Home and Kitchen appliances have been upgraded. The Korean chaebol says all of its products will be internet ready within five years from now.

Samsung is working with BMW (Bayerische Motoren Werke AG) to install Samsung tablets as touch command screens in cars. They demoed on how a wristwatch can be used to communicate with a car.

I just watched an interesting video on CNETwhere Samsung CEO, Yoon Boo Keun outlined his vision about IoT. Samsung having presence in most of the consumer electronic devices, home appliances and entertainment systems can rule the world after connecting all of them through internet and web. As I perceive the electronic world going forward, IoT can be a boon to some conglomerates (like Samsung) provided they can connect their systems well to perfection and the software works well. At the same time, unconnected systems can push organizations to failure. Of course standardizations are needed to connect systems from different sources; Samsung has a clear competitive advantage as it has its own devices in many segments. It’s yet to demonstrate Tizen working on its Smartphones though.

About Samsung, I had mentioned about their collaboration with Intel for Tizen development, joining Thread Group, signing up with Cisco, acquiring SmartThings, its Innovation Museum and so on in one of my blog last month – What Will Drive Smartphone Market Now? Samsung seems to be on the right strategy to pull through its Smartphone market along with IoT strategy. Will it?

More Articles by PawanFangaria…..


Ion Implant – Its Not Just for Doping Anymore

Ion Implant – Its Not Just for Doping Anymore
by Scotten Jones on 01-07-2015 at 8:30 pm

At the heart of fabricating integrated circuits is the ability to selectively change the electrical properties of the semiconductor substrate. This key to fabrication is accomplished by doping – introducing atoms locally into the semiconductor substrate.

In the early days of the semiconductor industry doping was accomplished by creating a pattern on the surface of the semiconductor substrate typically in an oxide film and then depositing a doped glass over the surface. A subsequent heat treatment would then diffuse the dopants from the glass into the exposed semiconductor surface in some areas and the dopants would be blocked by the glass in other areas.

With the introduction of ion implantation for doping, solid source doping has largely disappeared (although Intel recently brought it back for one application in their 14nm process). Ion implantation utilizes a particle accelerator to inject dopants into the semiconductor material with high energies. Ion implant has several advantages over solid source doping, first and foremost is better control of the amount of dopant introduced. Ion implant can also better control the depth of the dopants and utilize photoresist as the mask for doping as opposed to requiring a film that can withstand high temperature; and Ion implantation can introduce nearly any atom of interest and does it at low temperature.

Recently the semiconductor industry has begun the evolution of logic processes from planar devices to fully depleted devices such as FinFETs and FDSOI. This transition greatly improves the electrostatic control of the gate over the channel of the device and dramatically reduces leakage. This transition also reduces the need for ion implantation. As semiconductor devices have shrunk into the deep sub-micron range the control of threshold voltages has driven a significant increase in the need for ion implantation. Different threshold voltages have required threshold adjust implants for NMOS and PMOS for each threshold voltage. At deep sub-micron dimensions the halo implant at the drain extension step and even the source/drain contact implants also have to be tailored for each threshold voltage. An additional threshold voltage can require as many as 13 implants at 40nm and smaller nodes! With FinFETs threshold adjust implants are still used but there are no halo implants so only extensions implants for NMOS and PMOS are required and raised source/drains are used with no implants. FDSOI further reduces the implants required by controlling threshold voltages with biasing instead of implants. At first glance this all seems like bad news for implant companies.

At SEMICON West in 2014 I attended an Axcelis presentation on the use of implants to change the material properties of wafers. Current state-of-the-art implanters can vary the dose implanted into a wafer radially. So if for example you had a CMP process that removed material faster at the edge of a wafer versus the middle of the wafer you could implant a higher dose of an implant specie in the center of the wafer than the wafer edge increasing the CMP removal rate in the center and creating a CMP/Implant process combination that is uniform across the wafer. This new application for ion implant was presented as having the potential to maintain or grow the market for implanters even though doping applications were declining. Some applications for this technique:

1. Amorphization
2. Modifying CMP removal rates
3. Modifying Etch rates
4. Hardening photoresist
5. Reducing photoresist pattern line-edge-roughness (LER)

At the time I thought this was an interesting potential application but I wasn’t aware of it actually seeing much use. I will comment that I could see a lot of potential for it, implant steps are relatively inexpensive particularly if no photoresist mask is required at only $1 to $2 per implant for a 300mm wafer.

Since then I have become aware that this technique is rapidly being adopted with some logic processes using materials modifications implants 10 or more times per wafer. On the memory side the usage is lower, more in the 2 to 5 implants per wafer but it is growing as well. As process linewidths continue to shrink this is a technique that will likely see increased adoption. In most cases the specie being implanted is similar to the material it is being implanted into so these implants don’t show up on reverse engineering analysis of parts but they are being used today!


Tizen, Is It a Thing?

Tizen, Is It a Thing?
by Paul McLellan on 01-07-2015 at 7:00 am

I’m not at CES so I’m reporting second hand. But Samsung made some announcements and, since they didn’t make any mobile announcements, people were disappointed. Like Don Dingee, I think that any major mobile announcements will be done in March at Mobile World Congress. Although CES is starting to get a little bit more of a mobile focus, MWC has a laser focus on mobile and everyone involved in the industry will be in Barcelona.

Tizen is an operating system based on Linux largely developed by Samsung. There is actually an open source consortium (which also involves Intel) but it is perceived as the “Samsung Operating System.” The first product using the operating system was a camera over a year ago. At CES Samsung announced that going forward all their smart TVs were going to be running Tizen. That is a big step, the first time they have made a solid commitment to it.

But the big question everyone wants to know the answer to is whether Samsung will switch a lot of their smartphone product line to Tizen. The reason that this is so important is that Samsung is far and away the #1 smartphone supplier (roughly twice as big as Apple but not as profitable per phone). So if they switched a lot (or even all) their phones from Android (which they use today) to Tizen then it would have a big effect not just on Samsung but on the Android ecosystem too. Samsung is the only company with enough market power to create a third ecosystem (along with Android and iOS). Microsoft hopes to do it with WindowsPhone and their Nokia acquisition but with 3% market share they just don’t have the clout to make headway. If you are paying developers to write apps for your platform you are losing (what does Intel call it, contra revenue).

There are lots of rumors (and no facts) that Samsung was very unhappy that Google both supplied their operating system and competed against them (not very successfully, it has to be admitted) in the hardware business. The big worry was that if things continued then Google might have to give its Motorola subsidiary a better/earlier version of Android than it let Samsung have to try and make that business more successful. So in some sense Tizen might be regarded as an insurance policy.

One version of the story is that Samsung told Google that they would go full steam ahead in mobile with Tizen if Google didn’t sell off its hardware business. But they would back off if they did. They might regret than now that the purchaser turned out to be Lenovo, who have a track record of taking marginal or failing businesses and making them wildly successful. They took over IBM’s notebook business, which was losing money for IBM, and built it up. Recently they acquired IBM’s low-end server business too. Combined with Motorola they are a solid #3 in mobile behind Samsung and Apple, well ahead of Lenovo alone, who already had their own mobile business.

Evidence for this version of events is that Tizen for mobile suddenly slipped a couple of quarters when Google announced the sale of Motorola Mobility. But if Tizen is going to be in every smart TV then the operating system is not going to wither away. The carriers have always wanted a 3rd ecosystem so they can play everyone off against each other, which may or may not be significant. Apparently next month Sammy will release their first Tizen smartphone, but only in India. Whether this is dipping a toe in the water in an “off-Broadway” market remains to be seen.

2015 could be the year of Tizen. Or not. But keep an eye on it.


More articles by Paul McLellan…


Cycling, Semiconductors and CES 2015

Cycling, Semiconductors and CES 2015
by Daniel Payne on 01-06-2015 at 10:00 pm

I’m an avid cyclist that rode some 6,744.3 miles in 2014, according to www.strava.com, a free web site and popular app for road bikers like me. At CES this week I’ve read about many creative devices and apps to make your cycling experience better, so here’s my take on all of it.


Continue reading “Cycling, Semiconductors and CES 2015”


Lights, audio, and waiting for action from Qualcomm

Lights, audio, and waiting for action from Qualcomm
by Don Dingee on 01-06-2015 at 3:30 pm

The news Qualcomm has shipped over a billion Snapdragon chips in Android smartphones broke last September. After reiterating that and a sustained outlook for smartphones over the next five years, the Qualcomm CES 2015 presser seemed to leave most media outlets a bit disappointed. Naturally, that prompts us to ask what is going on in the bigger Qualcomm picture. Continue reading “Lights, audio, and waiting for action from Qualcomm”


Intel: 2015 and Beyond?

Intel: 2015 and Beyond?
by Daniel Nenni on 01-06-2015 at 7:00 am

Russ Fischer of Seeking Alpha fame just posted another article on Intel which, for a change, I agree wholeheartedly with except of course the part where he comments on the fabless semiconductor ecosystem, something he knows nothing about. But other than that it is definitely worth a read because as investments go Intel is certainly in a strong position.

Like me, Russ is a semiconductor professional although he is retired. Unlike me, Russ invests in the stocks he writes about which, in my opinion, is a questionable practice. Yes there is a disclaimer at the end but unfortunately blogs are quoted and cut/pasted all over the internet and the disclaimer does not follow.

According to Russ, we can ignore the non-mobile Intel Custom Foundry business (Altera etc…) as a growth driver which I agree with. Russ does however suggest that Intel could be a player in the mobile foundry business but of course that did not happen at 14nm. Given the problems Intel has had with 14nm yield on internal products it is not surprising the big fabless companies skipped it. You also have to ask yourself: Will one of the big SoC companies hand over designs to one of their fiercest competitors? Intel may not be a competitor for smartphone SoCs but tablets are another story completely (Core M and Cherry Trail). Flooding the SoC channel with 40 million “contra revenue” Bay Trails did not help either (scorched earth).

Russ also states that TSMC 20nm is all Apple with very little or no wafers going to all other customers. This is a complete Fischer Fabrication. CES will be filled with 20nm silicon from both TSMC and Samsung. I also noticed that the 64-bit SoCs being launched at CES this week use ARM Cortex A57/53 cores versus doing their own ARM implementation like Apple. Even the latest QCOM Snapdragon uses ARM versus their in-house Krait core which begs the question: Why?

Here is the funniest part of the article cut and pasted so the humor is not lost:

Intel: 2015 And Beyond:The non-Intel finfet business represented by TSMC and Glo Fo is in a serious state of confusion. The latest news is that Glo Fo will be delayed a couple of quarters on 14nm and that Apple is scurrying to figure out a solution. Glo Fo denies the delay.

Russ is the only one in a serious state of confusion here. This was a “rumor” and not “news” of course and it has since been debunked. Check the comments section of this blog:

GlobalFoundries did NOT Pull the Emergency Brake!

I have exactly zero direct knowledge of whether TSMC or Glo Fo will ever deliver finfet-based products in production volumes. I do know that neither company is delivering finfets today. We are down to the “fish or cut bait” time on non-Intel finfets. If TSMC and Glo Fo really can’t get a finfet process working pretty soon, Apple and others (under the new, “All customers for foundry” policy at Intel) will have no choice but to get involved with Intel.

This could be the ultimate solution to the smartphone problem; Intel gets it through the foundry.

Smartphone problem indeed. The funny thing is that when I read his articles they track with what I hear from the Intel PR machine and even the Intel executive staff. Seriously, Russ should come with an “Intel Inside” label. Here are some other famous quotes for perspective:

“Trigate? We are on our second generation, no one has figured that out, they aren’t going to figure that out.” Paul Otellini, Intel CEO, 12/2012

“TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed to mitigate leakage current.” Mark Bohr, Senior Fellow at Intel Corporation, 4/2012

“We’re going to introduce FinFET after the 20-nanometer planar. We’ve been working on FinFET for more than 10 years. We’re quite confident that we will have a robust FinFET technology.” Dr. Morris Chang, TSMC Chairman, 4/2012

To be clear: TSMC, Samsung, and GF are delivering risk production FinFET wafers today with volume production scheduled to start in Q2 2015. Fabless heavyweights Apple and QCOM are driving this effort at all three foundries so I have no doubt it will happen, absolutely.


Apples Versus Zebras

Apples Versus Zebras
by Scotten Jones on 01-06-2015 at 12:00 am

I have seen a couple of posts comparing the density of the Apple A8 to the Intel Core M and concluding that the TSMC 20nm process is denser than the Intel 14nm process. In one of the threads one of the posters likened this to comparing apples to oranges, I agree except I think it is even worse than that, I think it is more like comparing apples to zebras and here is why:

Let’s start by talking about the elements one might see in a chip design on these advanced processes. First there are logic elements. Depending on the design goals, density, power, and speed the logic elements will vary in size. They will also vary in size versus SRAM cache and SRAM cache itself will vary in size depending on the goals even on the same process. For example, TSMC’s 45nm process has high density SRAM cache with a 0.202 um2 cell size and other SRAM cache (presumably high performance) with a cell size of 0.324 um2, a 1.6x difference on the same process! Intel’s 22nm SOC process offers HDC cache with a cell size of 0.092 um2, LVC with a 0.108 um2 cell size and HPC with a 0.130 um2 cell size, a 1.4x difference! And these are just a few quick examples from scanning published papers on processes. Analog circuit elements will also have a different density particularly when considering that elements such as resistors and capacitors aren’t even counted towards the circuit density.

I have analyzed seven different Intel MPU designs I have data on, all were produced on the same Intel 32nm process. The designs vary from just over 2 million transistors per mm2 to over 5 million transistors per mm2, a 2.5x difference in density on the same process for different MPU designs executed by the same company! To compare the Apple A8 design that has a completely different set of design goals to an Intel Core M on two different processes and conclude one process is more or less dense than the other is simply not a valid comparison. You would need two identical or close to identical designs on the two different processes to make a valid comparison and in this case that isn’t available. This is why at all the major technical conferences, all of the companies use design independent minimum pitches to compare processes.

Lately I have made several posts using the gate pitch x metal pitch metric to compare relative process density. This is a metric Intel has used in several recent presentations; IBM and the common platform alliance have also used it in their own technical papers. Even TSMC when disputing an Intel density advantage claim didn’t question the metric, they merely said Intel used old numbers for TSMC. The best and indeed only valid design independent comparisons of processes currently available are SRAM cell size and gate pitch x metal pitch which is why process experts use them.

I think it is fair to say that process experts generally agree that Intel has the densest 16nm/14nm logic process currently available, but so what? The more relevant question is whether Intel’s 14nm process is the best process and that depends on your design goals. Intel’s processes are first and foremost designed to produce Intel MPUs, and then the processes are adapted to make SOCs. TSMC processes are developed in close coordination with their customers and are specifically targeted at the SOC needs of those customers. I would bet money that if Apple knocked on Intel’s door and wanted to make the A9 on Intel’s 14nm process, Intel would be interested, in fact I would be surprised if Apple hadn’t at least evaluated that option. Apple makes the A8 on TSMC’s 20nm SOC process because they concluded that at the time they did the design that was their best option from a performance, price and delivery perspective for Apple’s design goals. I have no doubt the A9 sourcing decision will be made based on the same criteria.

Intel’s processes look different from TSMC’s processes because their design goals are different and TSMC’s processes look different than Intel’s process because TSMC’s customers have different design goals. TSMC is far and away the market leader in foundry and their process development is targeted at maintaining that lead. Intel is far and away the market leader in MPUs and their process development is targeted at maintaining that lead. One company makes apples and one company makes zebras, they both do it really well.


Coventor Panel at IEDM Digs into Variation Issues

Coventor Panel at IEDM Digs into Variation Issues
by Tom Simon on 01-05-2015 at 7:00 pm

Recently I attended a panel discussion on variability in semiconductor fabrication hosted by Coventor in conjunction with the IEEE IEDM conference in San Francisco. The IEEE bills the conference as “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling.” It’s easy to see how this discussion was relevant to the conference focus. SemiWiki’s own Dan Nenni was the panel moderator.

The panelists were John Wise from Lam Research, Jan Hoentschel with GLOBALFOUNDRIES, David Fried of Coventor, Jeff Smith for Tokyo Electronics NA, Tom Dillinger of Oracle Corporation, and Tomasz Brozek representing PDF Solutions. Each made opening comments, but the overriding theme was that variation is becoming a huge bottleneck for IC design and manufacturing. Paul McLellan has already written here about this panel, but I thought certain highlights were worth focusing on.

Tom Dillinger of Oracle spoke from the perspective of the design community, so I found his observations to be particularly interesting. He started out right away by saying that the device models are the most important thing. For FinFET you need to use BSIM-CMG models. BSIM-CMG comes with new parameters to indicate the number of fins. With additional fins comes “lots of parasitics.” Tom’s view is that for SRAM designers statistical models help a great deal with modeling variation. You have many copies of the exact same physical device. But with logic designs you introduce a wide variety of physical parameters that make predicting variation effects extremely difficult. FinFETs have finger counts and fin counts to factor in. With high fin counts it is necessary to reduce the parasitics in the models.

Tom feels that one of the models fall down because the fin is presumed to be rectangular. In reality it is a trapezoid or even a triangle. Also at more advanced nodes without EUV, moving to multiple patterning will introduce new sources of variation in devices. In fact a great deal of the Q&A after the panel discussion centered on whether EUV will become viable. There was no clear consensus on this point. There was agreement with Coventor CTO of Semiconductor David Fried’s statement that without a lightning bolt change from the current, 7 generation old, approach to lithography, that the only way to reduce the effects of variation is to work a ‘chorus’ of smaller improvements.

David Fried sees each discipline in the design and manufacturing process taking a silo based approach and specifying worst case parameters for the design. The result is expensive guard-banding that is probably overkill. It used to be that you could run batches of wafers and have a good idea about the variation problems you might encounter. With an exploding number of sources of variation, Fried asserts, it is impossible to run enough wafers. Jeff Smith of TEL America said that they use Coventor tools to identify the highest risk areas so they know what kinds of test wafers they should run. This makes it possible to find a manageable number of test cases to explore.

Fried also made the point that causes of variation are now masked so that it is harder to connect physical effects to yield results. The underlying physical effects can be misunderstood. This leads to overly conservative design guidelines. Not surprisingly, Fried called for a predictive approach, using simulation tools to better understand the underlying physics.

The panel discussion highlighted that we are at an interesting juncture. There was some talk about SOI versus FinFET, but the consensus was that FinFET on SOI will be the winner. So, going forward there are many questions. Will a cost effective lithography change come in time? How well will existing FinFET models work in production designs? Can excessive guard-banding that reduces cost effectiveness of new nodes be eliminated?

It promises to be an interesting year ahead.


QuickLogic betting big on sensor hubs

QuickLogic betting big on sensor hubs
by Majeed Ahmad on 01-05-2015 at 12:00 pm

QuickLogic Corp.—the former FPGA maker that reinvented itself through configurable design for consumer electronics (CE) products—is taking its sensor hub arsenal to high pitch at the 2015 International Consumer Electronics Show (CES) in Las Vegas. Sensor hub, a companion to application processor, offloads data from sensors and processes it to boost overall performance while saving power for the main processor. Sensor hubs serve always-on, always-aware sensor-based applications for smartphone and wearable products.


S2 Sensor Hub Block Diagram

The Sunnyvale, California–based company is demonstrating its latest sensor hub solution—the ArcticLink 3 S2—along with reference designs and evaluations kits at the MP25452 booth in South Hall 2, Las Vegas Convention Center. QuickLogic is also participating in a MEMS Industry Group panel at the CES.

QuickLogic engineers call their sensor hub chips customer specific standard products (CSSPs) and claim that they have an edge over competing solutions that are either based on MCUs or ASSPs. They point to the fact that the MCU-centric approach is entirely based on software that uses more power than hardware. The company spokesman asserted that QuickLogic’s ArcticLink 3 S2 chip consumes 95 percent less active power than typical MCU-based sensor hub solutions.

On the other hand, alternatives like ASSPs, while they are power savvy, they don’t have the inherent flexibility to adapt sensor hubs to emerging applications like gesture and context awareness. QuickLogic engineers say that their hardware-based solution offers greater power efficiency, and its programmable fabric enables greater flexibility to add upcoming features and adapt to design changes.

Furthermore, QuickLogic engineers maintain that the fact that ArcticLink 3 S2 sensor hub consumes only 150µW, which makes it ideal for the always-on, always-aware smartphone and wearable applications. The company has also joined hands with Bluetooth Smart chipmaker Nordic Semiconductor, and the collaboration of the two semiconductor firms has led to the creation of TAG-N wearable sensor hub evaluation kit.


Nordic nRF51822 Development Kit

“The kit incorporates QuickLogic’s ultra-low power sensor hub, related algorithms, and a direct connection to a Nordic Semiconductor multiprotocol development kit for its nRF51822 SoC,” said Frank Shemansky, Senior Director of Product Management at QuickLogic. “The resulting wearable reference designs are suitable for quick prototyping, demonstration and testing of monitoring, context and gesture algorithms.”

Context and gesture solutions
QuickLogic spokesman said that the TAG-N development kit aided by pedometer, gesture and context algorithms could help OEMs significantly accelerate product development cycles. He added that QuickLogic’s context, gesture, and transport algorithm library includes pedometer accuracy, context awareness, and more.


S2 Sensor Hub Context and Gesture Solution

QuickLogic President and CEO Andy Pease said, “The context and gesture solutions available through sensor hub will enable a wide variety of apps ranging from motion detection to enhanced pedometer.” Take pedometer functions, for instance, which are the foundation of witness and wellness apps. A pedometer helps the application processor determine if a user is walking or running and does the step count for each condition.

Gesture requires no verbal communication while context is the state of being that doesn’t need an immediate response. And both gesture and context need to be accurate. QuickLogic has developed sensor algorithms for activity, gesture, location and transport contexts. These algorithms work as a baseline along with third-party and OEM-developed algorithms in an integrated development environment that provides software engineers with an easy-to-use way for deploying algorithms to hardware.

Image credit: QuickLogic Corp.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.