webinar IPXACT banner

MEMS Require 3D Field Solver for Accurate Cap Values

MEMS Require 3D Field Solver for Accurate Cap Values
by Tom Simon on 02-18-2015 at 9:00 am

MEMS devices have become extremely important and common. Freescale last year reported its combined MEMS shipments exceeded 2 billion units. If we just examine how many accelerometers we each probably own today, it is easy to see why the market for these products is growing so rapidly. The first and most obvious device is our cell phone. Another growing area is for hard drive protection using fall sensors in laptop computers. If you have a sports tracker, you can add another to the list. The earliest use of these devices was for air bag crash sensors. Also a lot of cars use them for traction and antiskid control.

Already we have a handful on our list of devices we own that use them. I have read about smart meters using them to detect tampering. Many of us have video game controllers with motion or gesture controls. The list goes on.


Actually it’s understandable how there can be billions of units already installed, with the need for more on the way. MEMS technology has opened the doors for many new applications for devices that interact with the real world. To make this possible there have been advances in fabrication and design
technology.

A key element for the success of MEMS is design analysis and verification. In this respect they are not unlike semiconductors. MEMS stands for micro electro mechanical systems. Electrical properties of these systems need to be well understood before a successful working design is possible.


In classical semiconductors most people are familiar with finger caps, or MOM caps as they are sometimes called. Modern MEMS accelerometers rely on a similar structure that relies on changes in sidewall capacitance as one set of plates moves relative to the other during acceleration. The moving plates are connected via ‘flexible’ attachments so they behave somewhat like a weight on a spring. Usually there are differential fixed plates on each side of the moving mass so that as it moves in a direction one set are seeing increased capacitance and the other is seeing reduced capacitance.


Sidewalls are made very large to maximize the side wall surface area. And of course the space between the conductors is air not dielectric. However, just as with finger caps, the best way to determine capacitance is with a field solver. Another parallel issue with MEMS is parasitic capacitance.

The challenge with FEM or Method of Moments solvers is that the number of unknowns is large and the compute resources and time required can be quite large. For less accurate results, on-chip capacitance extraction based tools have been used historically. But they are being supplemented by embedded field solvers such as Mentor’s xACT-3D used with Calibre.

Mentor has announced that the xACT-3D solution is now available for MEMS designs. As like most field solvers it starts with a stack up description. Next the design is read in from a layout tool and it is converted to a 3 dimensional data base. Mentor says that xACT-3D uses a true field solver that runs very quickly to output a parasitic database that has capacitance values for every node pair, including parasitic caps values. At that point the data can be output in a variety of standard formats such as a SPICE netlist. Here is a white paper that goes into more detail regarding the Calibre xACT-3D solution for MEMS.


MEMS accelerometers are in great demand and are needed for wide range of applications. They are needed for subtle activities such as gesture recognition, all the way up to impact sensors for passenger safety or industrial applications. Design complexity and sophistication is bound to accelerate. A fast and efficient means of performing critical design analysis and verification before silicon will be useful.


32-bit MCUs Way to Go for IoT

32-bit MCUs Way to Go for IoT
by Majeed Ahmad on 02-18-2015 at 7:00 am

Cost, power and performance, and security are the fundamental ingredients of chip development for the Internet of Things (IoT) market and that 32-bit microcontrollers are a way forward to meet these basic requirements. That was the crux of the message from the webinar held by Andes Technology Corp. on February 10, 2015.

You can see the full webinar HERE.

“The 8-bit MCU standard is limited by peripherals and instruction set and it doesn’t offer the cost advantage in the IoT environment,” said Emerson Hsiao, Senior VP of Sales & FAE at Andes. “Moreover, memory interface in 8-bit MCUs lead to bottlenecks for both power and performance, so they don’t make sense for IoT devices.” He added that peripherals in Andes’ 32-bit processor cores operate at different power modes, and thus they optimize power consumption.

Hsiao said that the IoT market is constantly evolving and there are significant changes in the IoT landscape every year. So IoT chips should not only offer lower power and higher performance but they should also be future proof in terms of technology upgrades. Hsiao quoted touch-panel controllers as an example where 8-bit MCUs sufficed for the first-generation touchscreens. However, for second- and third-generation touch-panel controllers, more demanding gesture applications for smartphones and wearable devices necessitate more powerful 32-bit MCU cores.


Andes’ ultra-low-power processor core solutions

Hsiao also presented smart meters as a case study where a chip costs US$2-3 and features MCU, communication port, and sensor interface as primary components. So rather than saving a few cents in chip development with 8051, more advanced power-saving techniques offered by 32-bit MCU cores could lead to a lot more energy conservation in the end. Hsiao mentioned that there are 300 million smart meters only in China. That just shows the scale of energy conservation that power-efficient chips could bring to smart meter operation at large.

For security, Hsiao again used the smart meter case study and explained how a secure MCU system can carry out embedded code protection within end-user device. He said that smart meter devices are mostly vulnerable at the memory and JTAG levels, and showed how Andes cores could allow access to JTAG debug interface and ILM to secure embedded software and program data.

CPU and Memory Bottlenecks

For IoT and connected wearables, Hsiao emphasized the small gate count for saving die area and high performance with execution efficiency for designers needing an upgrade path from 8-bit cores that have been widely used in embedded applications during the past two decades. However, if there was a prominent theme in this webinar, it was how power is driving requirements for applications such as IoT, connected wearables and other flash-memory based requirements. And the fact that Andes’ low power solutions impact beyond the processor cores.

Hsiao said that Andes’ 32-bit MCU cores offer greater energy efficiency through power-saving modes that outnumber competitor solutions. “Andes employs PowerBrake technique that results in flash acceleration, which in turn, reduces power consumption and improves performance.” The PowerBrake technology is based on the variation in frequency scaling at 16 levels and has met industry benchmarks for both Coremark and DMIPS, he added.

The PowerBrake technology helps minimize the idle power through creating different power modes for the CPU. The creation of power profiles for different connect stages helps to optimize the power interface to CPU and thus lowers power consumption and improves performance horsepower.

Another power efficiency technology that Hsiao mentioned during the webinar was FlashFetch, which minimizes access to NOR flash memory and thus lowers power and enhances memory interface speed. FlashFetch memory acceleration technique records repeated code sequence in a structure called TinyCache for later fast accesses.


FlashFetch eases memory interface bottlenecks

TinyCache is different from traditional caches in a sense that it takes power consumption into account. It improves program execution efficiency by providing zero wait-cycle for instruction accesses, and at the same time, it helps in cutting the total power consumption of CPU and flash memory. So, while the power consumption contributed by the CPU slightly increases due to the additional logic for the TinyCache, the power use coming from flash memory is greatly reduced due to less number of accesses.

Moreover, if required, FlashFetch can allow instruction accesses to read ahead, thus speeding up the execution of sequential code. This feature supports 64-bit and 128-bit fetch widths of flash memory. Hsiao acknowledged that prefetch buffer helps in enhancing performance, but it also brings in redundant instructions that lead to increased power consumption.

Image Credit: Andes Technology Corp.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.


Freescale and Samsung

Freescale and Samsung
by Paul McLellan on 02-17-2015 at 6:58 pm

It is impossible to keep a secret in this business. Everyone knows that Freescale is being shopped around and there is interest.

From Yahoo Finance:
The parties that Freescale is speaking to could not be learned. The New York Post first reported that Freescale was working with investment banks to explore a sale. Freescale shares were up 8.5 percent at $37.66 in morning trading, giving it a market value of $11.5 billion.

Well, I’ve done some learning and apparently Samsung is the suitor and the deal is pretty much done. Of course no deal is done until it is done, and one of the reason for engaging investment bankers is to get the price up by getting some other players into the ring. Samsung would make a lot of sense, they already have a major presence in Austin where Freescale is headquartered. In fact I believe the Samsung fab in Austin is the largest in the US, bigger than anything Intel has, or GlobalFoundries or…anyone else…Micron I guess.

About half of Freescale’s business is automotive, a fast growing market now and for the future (driverless cars don’t really drive themselves, a lot of semiconductors do) and area where Samsung is not strong. I expect they supply a lot to Hyundai and Kia, that is the way Korea works, but globally they are not the name that leaps of everyone’s tongue. The US in particular is a huge automotive market. Not just the big 3 but transplant factories for BMW, Mercedes, Toyota, Honda and others. Most of the rest of Freescale is various forms of communication (but not mobile, they exited that business a few years ago after they failed to find a buyer for it).

Freescale was a spinout of Motorola’s SPD, silicon products division, taken private by Blackstone, Carlyle and TPG Capital (and maybe some other smaller companies). The first CEO was Rich Beyer (a name to make any salesman’s heart leap for joy) who was COO at VLSI for a couple of years and I used to give weekly tutorials to about how designs were done and what EDA was. In 2011 Freescale went public (it was never public before, of course, except as part of Motorola which was). The buyout companies still own almost 2/3 of the company.


7nm node is arriving, which ones will continue past 2020?

7nm node is arriving, which ones will continue past 2020?
by Pawan Fangaria on 02-17-2015 at 6:30 pm

‘Laughing Buddha’ is eternal, but for semiconductor industry, I must say it’s ‘laughing Moore’. Moore made a predictive hypothesis and the whole world is inclined to let that continue, eternally? When we were at 28nm, we weren’t hoping to go beyond 20/22nm; voices like ‘Moore’s law is dead’ started emerging. Today, we are already into production at 16nm and 14nm, and looking at 10nm, 7nm, 5nm, 3nm, and even lower going forward.

Well, there is a large contribution of FinFET transistor structure in scaling the semiconductor technology to 16nm/14nm. FinFET along with high mobility materials like III-V and Ge for its channel can pull the node up to 10nm, may be 7nm, but not beyond that.

For 5nm or even for 7nm, foundry experts are gearing up to develop further next-generation transistors, the front runner among them seems to be what is called ‘Gate-All-Around’ (GAA) transistor.

If we look at the evolution of transistor structure through gate, it appears to be progressing pretty much in line starting from single gate to double gate, tri-gate/FinFET and now GAA. However, it’s extremely difficult, expensive and time consuming to experiment fabrication of such complex structures and with newer material compositions. Fabricating transistors is one part of the process, often called FEOL (Front-End-Of-Line) process. BEOL (Back-End-Of-Line) process is to do all the interconnections, and there comes the complex part of managing the RC. Again, there are local interconnects at device level accomplished by MOL (Middle-Of-Line) process. The global interconnects are done by BEOL and they are prone to RC delays. Today at lower nodes, BEOL employs multiple patterning which requires extra deposition and etching with every pattern, thus increasing the cost of production. Technically, multiple patterning can still be viable at 7nm, however the industry is looking at EUV (Extreme Ultra Violet) lithography to reduce that cost; with EUV, BEOL process can be done with single exposure and throughput can be as good as ~150 wafers per hour. But for EUV lithography, foundries are dependent on semiconductor equipment manufacturing companies. To accelerate EUV lithography, Samsung, Inteland Applied Materialsare reported to fund Inpria Corporation, a pioneer in high-resolution photoresist development and materials for emerging semiconductor patterning technologies. Recently, Inpria patented a technology in which inorganic photoresists provided nano-scale imaging below 20nm. By the way, aBeam Technologies is reported to have developed a technology to fabricate test patterns with minimum line-width of 1.5nm which can be used to test metrological equipments with ultra-high precisions.

Nevertheless, if we see the roadmap of big ones, Intel, GlobalFoundries, Samsung, TSMC, UMC, all plan to bring 10nm chips latest by 2017. Daniel Nenni even bloggedabout Intel’s plan to launch 10nm chips in early 2017.

TSMC is much aggressive on 7nm as well. According to ASML, TSMC has already ordered for EUV scanners to be purchased in 2015 and they are expected to start 7nm chip production in early 2018. Intel does not seem to be behind either; it plans to go ahead with 7nm, even without EUV if that’s not ready. So, let’s take some delay into account and say 7nm comes out in 2019. That translates to roughly two years gap for every major production node.

Above graph clearly shows 90nm, 65nm, 45nm, 32nm, 22nm, 14nm and 10nm to have around two years gap in every succession. 32nm/28nm was an inflection point below which it really was difficult to scale down. Double patterning and then multiple patterning started taking place. FinFET was invented, and now we are looking at GAA and other innovative transistor structures, EUV, and so on to go below 10nm. 7nm may arrive in 2018, 2019. Let’s say 5nm and 3nm also arrives past 2020 with support from EUV, GAA and other innovation as required. Then what? Which nodes will survive? Definitely, a few of them will have long maturity curve with major production volumes. It needs clever and strategic planning for fabs to reap the benefits from them; they will become the cash cows in the long-run. Let’s look at design starts per node as of 2013 (courtesy Synopsys) –

We can clearly see 350nm – 90nm in declining mode, 65nm – 32nm still moving towards maturity and 22nm – 14nm in growth mode. If we extrapolate this trend to 7nm and then 5nm and 3nm beyond 2020, we can envision that by that time 14nm and 10nm will be in major production. Will they continue for long? I would think so, because the FinFET process will be perfected by then with 16nm, 14nm and 10nm adopting the same technology with improved performance. If GAA and other technologies get perfected by say 2025, they may take over by 2030. Beyond that we need to again look at our ‘laughing Moore’!


Arteris Adds Functional Safety to NoC

Arteris Adds Functional Safety to NoC
by Majeed Ahmad on 02-17-2015 at 1:00 pm

Arteris Inc.has joined hands with Yogitech S.p.A. to help automotive system-on-chip (SoC) designers meet the required functional safety metrics and obtain the ISO 26262 certification for automotive safety integrity levels (ASIL) in the least possible time.

Arteris—which provides network-on-chip (NoC) interconnect IP solutions—will license the fRSVC_flexNoC Safety Verification Component from Yogitech to jump start the safety analysis and verification of its FlexNoC Resilience Package IP for accomplishing safety objectives in a much faster way.

“Customers who license the Arteris FlexNoC Resilience Package from Arteris will also be able to license the fRSVC_FlexNoC Safety Verification Component from Yogitech,” said Kurt Shuler, VP of Marketing at Arteris. “Many of Arteris’ Resilience Package customers are already longtime customers of Yogitech, so this partnership makes it very convenient for these companies to integrate Arteris FlexNoC into their existing functional safety analysis and verification processes.”


Arteris and Yogitech: ISO 26262 certification solution

Shuler calls Yogitech’s offerings “functional safety verification IP.” Yogitech is now developing the fRSVC_FlexNoC Safety Verification Component for FlexNoC. It’s going to be a component to the Yogitech Safety Designer and Safety Verifier Tool Suites that will make it easier for FlexNoC users to automate the required ISO 26262 test coverage and fault injection needed for certification.

Arteris will also be adding safety documentation to the existing FlexNoC Resilience Package IP. “Arteris is working with Yogitech to create this safety documentation to ensure it meets ISO 26262 requirements,” Shuler added. “Having this available to customers will make it easier for them to create the necessary ISO 26262 for their custom design.”

According to Shuler, implementing functional safety features in hardware is crucial for three reasons. First, the software-centric approach for implementing safety features in automotive SoCs involves a lot more effort to develop and maintain than using a certifiable hardware IP.

Second, software can be violated, and ultimately, the chipmaker will have to be answerable for safety risks. Third, chipmakers, which come at tier 4 in automotive products hierarchy, have to leave the software implementation of safety features to tier 1 and third-party players and thus they lose control of safety features.

The partnership between Arteris and Yogitech is targeting compliance with the ISO 26262 functional safety standard for SoC design teams. However, Arteris and Yogitech will also extend the offering to the IEC 61508 standard, addressing safety-related industrial markets such as robotic systems.

Anatomy of NoC IP Partnership

Yogitech—a leading player in creating the ISO 26262 safety spec—provides services and solutions to semiconductor outfits and system integrators to help meet functional safety demands.Its customer portfolio includes chipmakers such as Renesas, STMicro and TI; IP vendors like ARM; and system integrators as such Bosch and Denso. Yogitech, being part of the entire value chain, is able to help its customers with a broad view of the automotive SoC market.

Mauro Pipponzi, Director of fRTools at Yogitech, said that the partnership with Arteris involves a number of steps. First, it will produce a functional safety analysis and verification on the Arteris FlexNoC IP in order to generate the Safety Manual of the IP and the Safety Documentation Package, including the data—both analysis and verification—characterizing the IP from safety standpoint.

Second, according to Pipponzi,is the development of the fRSVC_FlexNoC Safety Verification Component, packaging safety documentation data in a format reusable with Yogitech fRTools during the integration of the IP.

Third, Pipponzi concluded, is the use of the fRSVC_FlexNoC by Arteris end customers. They will be able to integrate the FlexNoC IP in their SoCs using the fRSVC_FlexNoCand together with Yogitech Safety Designer and Safety Verifier Tool Suites and achieve safety objectives on their products with safety metrics and verification data being already provided.


Safety Verification Component for FlexNoC

According to Arteris’ Shuler, connected car standards like Advanced Driver Assistance Systems (ADAS) and V2V/V2I are all about functional safety. He added that stringent reliability becomes a requirement for automotive SoCs when they interact with the vehicle system for either acceleration or deceleration. Moreover, the addition of cameras and sensors to connected car platforms like ADAS will require greater processing power and that will lead to computation consolidation for automotive SoCs.

Shuler added that consumer electronics and mobile SoC makers like Nvidia and Qualcomm are new to safety features that are imperative to in-car electronics. That’s why they are adopting IP for car safety and are becoming Arteris customers.

Image credit: Arteris Inc.


Mobile 2014 and the Future

Mobile 2014 and the Future
by Paul McLellan on 02-17-2015 at 7:00 am

The numbers are in now and so we can look at the top suppliers into the mobile market for 2014, and then a look out to what the future might bring. Before getting to the companies it is worth looking just how dominant the Chinese market is, at 32% of the entire world market compared to, for example, US’s 9%. China Mobile alone has more subscribers than the entire US population. Android continues to be dominant on the OS front, although with Apple resurgent this quarter the percentage is down slightly. But for the first time ever, over 1B Android phones were shipped last year out of a total of 1.3B phones, the rest being mostly iPhones.

At the top of the table are Samsung at #1 with 314M and Apple at #2 with 193M. Although Apple and Samsung were neck and neck in Q4 that is an anomalous quarter, just after Apple’s annual new product introduction. Going forward I expect Samsung will move ahead of Apple again as the impact of the new iPhone 6s wears off. Probably the most amazing statistic is that in Q4 Apple made 93% of the profits of the smartphone industry and Samsung made 9%. Some other companies such as Sony and Xiaomi have announced that they are profitable. So there must be a lot of companies losing a lot of money.

At #3 is Lenovo/Motorola with 95M. As you probably know, Lenovo acquired Motorola Mobility from Google last year. People were skeptical when Lenovo acquired IBM’s laptop business but they have made a success of it. I expect them to make a success of the Motorola acquisition too. Unlike with IBM, Lenovo can keep the Motorola name indefinitely so it will be interesting to see how they market themselves. My guess is that they will use the Motorola name in US, the Lenovo name in Asia, and who knows in the rest of the world.

Huawei snuck ahead of Xiaomi for #4 and #5, with 61M and 59M units respectively (so almost a tie anyway). Xiaomi is an amazing story, coming out of nowhere to be #1 in the #1 market in the world, which is the only market in which they sold until recently (they have started to sell in India too). Huawei have built up their business without acquisition which is impressive; they weren’t in the top 10 five years ago.

Bringing up the rear:

  • LG (Korea)
  • Coolpad (China)
  • TCL-Alcatel (pure China, despite the little bit of a French name due to history)
  • Sony (Japan)

Sony announced that they were profitable last quarter for the first time for several quarters. But they have also announced that the division is up for sale. They are the only Japanese company that is serious about the market, all the other Japanese manufacturers squabble over the Japanese market and ignore the rest of the world. Controversially, just before Christmas, Palo Alto networks announced that they had found a backdoor in 24 models of Coolpad’s phones which appears to have been installed by Coolpad when they modify Android.

Notable for not being in the top 10 are three famous companies. US/Finland’s Microsoft/Nokia which continues to lose share and is now below 3%. Canada’s Blackberry which is down around 1%. There are rumors (denied) that Samsung is trying to buy them. And Taiwan’s HTC which, as recently as 5 years ago, was #4 ahead of Samsung.

Going forward, assuming Sony is sold, it looks like there are only going to be three countries seriously in the mobile business: Korea (Samsung and LG), US (Apple, and Motorola if you want to count them separately) and China (everyone else).


Physically Aware DFT Improves PPA

Physically Aware DFT Improves PPA
by Pawan Fangaria on 02-16-2015 at 7:00 pm

Introducing on-chip test circuitry has become a necessary criteria for an ASIC’s post manufacture testability. The test circuitry is usually referred as DFT (Design-for-Test) circuit. A typical methodology for introducing DFT circuit in a design is to replace usual flip-flops with special types of flip-flops called ‘scan flip-flops’ that contain logic targeted for improving testability. Scan chains are formed by connecting scan flip-flops serially that allow Automatic Test Pattern Generation (ATPG) tools to control and observe the sequential state of the design and to generate test patterns to achieve the highest fault coverage. Further, extra circuitry can be added to compress test data volume and optimize test time. Also, several self-testing logics, such as logic built-in self-test (LBIST) and memory built-in self-test (MBIST) can be added on a chip.Clearly, the DFT circuits are a must for testability, reliability and robustness of designs. However, they introduce overheads in terms of area and wiring which can increase power consumption and decrease performance of a design substantially. Also, accommodating clock domain crossing (CDC), clock-edge mixing, and voltage domain crossing in an SoC (which can have multiple modes of operations) needs extra hardware such as lock-up latch and voltage level shifter. This extra hardware introduces additional wiring along the scan path resulting into excessive wiring congestion. So, what’s the alternative in such a dilemmatic situation? We truly do not have a choice. We need to use the DFT circuitry. What if we have the best of both worlds? Here is a smart methodology where the overall design is optimized for best PPA (Power, Performance and Area).The idea revolves around doing design placement before test circuit insertion. Traditionally, placement is the last stage in the design flow when scan chain re-ordering is done to shorten long wires in the scan-paths. Naturally, this approach is limited in the sense that placement cannot be changed to a large extent. The break-point logic on the scan-path that involves lock-up latches, clock crossings, etc. cannot be affected to re-order flip-flops. Hence only feasible long wires can be re-routed. In a new approach at Cadence, a scan-mapped netlist is placed just after synthesis, before inserting DFT. Then, based on the placement, scan flip-flops are assigned to scan chains. Further, scan chain re-ordering is done as a final step.Cadence implemented this new methodology on a real wireless communication chip by using its ‘Encounter Digital Implementation System’ and ‘Encounter RTL Compiler Advanced Physical’ that provided an impressive gain of ~16% in scan-chain wire length reduction compared to traditional methodology. The net result in PPA optimization was ~42% saving in total negative slack in timing, ~5% saving in power and ~2% saving in area. Actual detailed data and the detailed steps applied in the flow by using these tools can be found in a whitepaperfreely available at Cadence website.The whitepaper also describes about how Encounter RTL Compiler leverages I/O pad placement information to optimally order the boundary-scan cells in the boundary-scan shift register. IEEE 1149.1 boundary-scan testing is essential for board-level interconnect testing. Here, boundary-scan cells are inserted between I/O pads and the system logic. The boundary-scan cells are serially connected and provide controllability and observability to board-level interconnects. Their ordering is also important to minimize long crossovers along functional paths.The Cadence’s physically aware DFT methodology is proven to prevent wiring congestion due to DFT insertions, thus providing significant improvements in power, performance and area optimizations of a design.


Secure Processor for IoT

Secure Processor for IoT
by barun on 02-16-2015 at 1:00 pm

In my last blog “Processor for IoT” I have discussed security as one of the key requirements for processor used in IoT devices. In this blog we will analyze different method of hacking and some techniques which can be used to prevent those security breaches.

One of the common ways of attack is to probe address and data bus between processor and memory/ IO devices. The attacker can monitor or override information on those buses. The easiest method of preventing such attack is to encrypt any information (data or address) going out of processor and decrypt them before use inside the processor. This can ensure the confidentiality of the information. To ensure integrity of the information, i.e. the data is not corrupted by an external source; one can add a signature using encryption methodology on the block before sending out of the processor to the memory. When the data is again retrieved from memory the same operation is performed and both the signatures are compared to ensure data integrity. Both encryption and authentication can be performed together by a range of algorithms, commonly referred to as, authenticated encryption.

Now the issue is both the techniques is extra latency delay generated by the encryption and decryption mechanism as well as additional area overhead needed. Particularly the latency may become a critical issue if processor’s response time is required to be low like in real time application environment. One of the remedy deployed is to have dedicated crypto processor where the encryption and decryption are implemented in hardware leaving the main processor free for regular computation.

The next question on security arises where to store the key which is used for encryption and decryption. The key should be protected from outside attacks; otherwise the encryption and decryption will have no impact. Typically the key used to be stored in an on chip non volatile memory. But it may include the cost of manufacturing as it may need some special fabrication process (like EEPROM).

But these processes are not fully secured from physical attacks where the hacker has physical access of the chip and can extract the secure information by timing analysis, power analysis. Usage of physically un-clonable function (PUF) is a solution of this solution. In PUF the key is generated from the physical characteristics of a particular chip (for example delay of a particular circuit in a chip). Even if the hacker knows the circuit used to generate the key he cannot reproduce the same delay due to the variations of manufacturing process. Also this does not need any extra manufacturing process.

Another techniques used by designer to prevent timing attack is to introduce random delay to prevent attacker know the timing of its desired operation from reset of the system. To make it more effective the time period of the clock itself is randomized in low frequency application like smartcard. Designer can also impose randomness in the power consumption, electromagnetic radiation to prevent power analysis and electromagnetic analysis attacks respectively.

Trojan is another new way which new generation hackers are using to change the functionality of a circuit from its normal mode and make the circuit behave as per hacker’s need to extract confidential information from the circuit. Trojans are small module which is put by a hacker who has access to design files of an SoC or it may comes from a third party module which is reused inside an SoC. Trojans are typically dormant and hence make it difficult to get identified in the circuit. But in some rare event, Trojan gets activated. To prevent this circuit designer put a small monitoring block which monitors the functionality of different portion of the circuit and flags an error whenever any abnormality in circuit functionality is observed.

Barun Kumar De, Senior Business Development Manager – SmartPlay Technologies


ARM 2014 Results: 12 Billion Cores

ARM 2014 Results: 12 Billion Cores
by Paul McLellan on 02-16-2015 at 7:00 am

Last week was the ARM earnings call, giving the Q4 results and a summary of 2014. 12B chips containing ARM processors were shipped last year which has meant that they have grown in all their major end-markets: mobile, embedded intelligence, and enterprise infrastructure. Almost half of those 12B chips were in mobile, around 5.6B. That is obviously a lot more than the total number of smarphones shipped (1.3B) meaning that there are, on average, four to five ARM processors in each smartphone. Of course the one in the application processor gets all the attention and is probably the only one that is a high-end 64-bit Cortex-Ax core.


If you want some evidence that IoT is really a thing and is not just pure hype, then ARM has some numbers:around 200 companies in total with Cortex-M and what are, many of those companies are doing is generating products for these new emerging markets wearables, smart devices, IOT, which integrates a different technologies in different ways to address new and growing markets

Their market share in networking has doubled year on year from 5% market share to 10%. This is all still 32-bit since this is not an industry with short design cycles. So there is future upside with the V8 instruction set to address a bigger market (and carries higher royalty rates).

ARM reckons they are now the #1 GPU vendor with their Mali series with their partners shipping 550M chips. I’m guessing that means they believe they have overtaken Imagination who are the only other serious GPU IP licensor, most notably to Apple for the iPhone.


One statistic they reported, which they never have before, is how many chips contain ARM’s physical IP (descendants of the old Artisan product line). The answer is 8.9B. I don’t know if that is only chips that contain ARM processors, obviously you can use ARM standard cells without having a processor on your chip. That is 2/3 of the number of chips shipped with ARM cores anyway.

Last year ARM teased analysts by pre-announcing a product with a code-name Maya. This turned out to be the Cortex-A72 announced a couple of weeks ago along with a suite of other products. On the call they started teasing again, pre-announcing two new products called Teal and Grebe, although they gave not a hint as to what sort of products these might be.

See also New Suite of ARM IP for Mobile

One surprising statistic is that they expect that by the end of this year around 50% of the cores shipping will be 64-bit, including more than 30% of mobile devices.

ARM was asked about how much share they anticipated Intel getting in mobile with their agreements with Rockchip and Spreadtrum. Simon wasn’t going to go there that directly but they are clearly not quaking in their boots:So we’re not assuming any significant market share loss in smarpthone in any of the numbers and outlook that we’ve given today. I think we’ve got an excellent portfolio of technology that’s got enable ARM and our licensees to continue to succeed in that space. So we’re not baking in some big share loss and therefore there is not the opportunity that doesn’t materialize. I think over the foreseeable future here, over the lifetime of the products that we have, our shares there are looking good.


So great results. To me the most surprising number was the explosive growth of 64-bit when you think that it was only introduced a year or two ago and ARM expects to exit the year with over half of their partners’ shipments being 64-bit. Given that they also expect a lot of growth in the IoT/Cortex-M end of the business, which is all 32-bit, this is impressive. They also said that they expect to have 20% of the server business by 2020, which would be an amazing achievement if it turns out that way.

Next place to get your ARM fix: it is Mobile World Congress in Barcelona in a couple of weeks. Expect to see lots of ARM v8 smartphones announced.

Transcript of call here. Slides here.


Greetings from Digitopia!

Greetings from Digitopia!
by Bill Boldt on 02-15-2015 at 7:00 pm

digitopia

When it comes to the privacy and security of data, what does the future hold for consumers, companies and governments?

A tremendously interesting document, called “Alternate Worlds,” was published by the U.S. National Intelligence Council. It’s a serious document that not only examines four different alternatives of what 2030 might look like, but possesses some major geo-political thinking about the future.

In the entire report there was only one comment regarding privacy, which is amazing. This brings up many questions. Has privacy already become a quaint notion and a relic of times past? Is the loss of privacy a done deal? Will there be any attempt at reclaiming personal privacy? Will renewed privacy only be available to the upper classes? Will companies be required to take responsibility for embedding more security and privacy in their products and systems? Will governments fight for citizens’ rights to privacy or insist on the right to intrude? These all are important 21[SUP]st[/SUP] century questions, and they are simply impossible to answer now given that there are far too many variables. Only time will tell.

At the moment, however, it is pretty clear that the trend is away from privacy, at least in the way that privacy was defined in prior generations. If you observe first-world high school and college kids, you can easily see that many, if not most, live their lives way out in the open on apps like Facebook, Twitter, Tumblr and others, and don’t really seem to care all that much who is watching. Lately, more limited audience apps like WhatsApp, Snapchat, and WeChat that focus on smaller groups rather than general broadcasts have been growing, which belies some return to privacy concerns (i.e. don’t let mom see this), but the generational theme is clearly “live out loud.” Younger people live in a type of virtual society. Let’s call it “Digitopia.” Digitopia is far from a utopian place because it is insecure — really insecure. Cyber criminals, nosey companies, sneaky governmental operators, and other techno-mischief makers run rampant there.

One of the more intriguing predictions in the Alternate Worlds report points to future brain-machine interfaces that could provide super-human abilities, as well as improve strength, speed and other enhancements (i.e. bestow super powers). This notion could have come right out of author William Gibson’s classic cyber-punk novel Neuromancer where people’s brains directly “jack-into” the matrix. The report states:

“Future retinal eye implants could enable night vision, and neuro-enhancements could provide superior memory recall or speed of thought. Neuro-pharmaceuticals will allow people to maintain concentration for longer periods of time or enhance their learning abilities. Augmented reality systems can provide enhanced experiences of real-world situations. Combined with advances in robotics, avatars could provide feedback in the form of sensors providing touch and smell as well as aural and visual information to the operator.”


Hanging Out in Digitopia

Even the peaceful denizens of Digitopia are by default reckless, especially when it comes to their own privacy.

“A significant uncertainty … involves the complex tradeoffs that users must make between privacy and utility. Thus far, users seem to have voted overwhelmingly in favor of utility over privacy,” the Alternate Worlds report states.

As introduced in a prior article calledDigital Annoymity: The Ultimate Luxury Item,”the desire for personalized services is very seductive, and consumers are now complicit in, and habituated to, revealing a great deal about themselves. Volunteering information is one thing, but much of the content about our digital selves is being collected automatically and used for things we don’t have any idea about. People are increasingly buying products that automatically track their lives including cars storing data about driving habits and downloading that to other parties without the need for consent. As we visit web pages, companies get access to our digital histories and bid against each other in milliseconds fir the ability to display their advertising to us. This is kind of creepy. There is now an unholy trinity of governments snooping on us, corporations targeting our buying behaviors, and cyber-criminals trying to rip us off. The antidote is better security, but cyber-security is not something that individuals will be able to make happen on their own.

Data collection systems are not accessible, and they are not modifiable by people without PhDs in computer science. Because of that, security and privacy could easily become commodities which consumers will demand and thus economically force companies to provide. The only weapon consumers have is what they consume. If consumers only purchase secure products, then only secure products will succeed. In Digitopia, a company’s success may become dependent simply upon how well they protect the interests of their customers and partners — that is not a hard concept to understand.

You can almost see how there could easily be the equivalent of a “UL” label for privacy. Products and services could be vetted for the strength of their security mechanisms. Subsequently, products should then be rated on if they have encryption, data integrity checks, authentication, hardware key storage, and other cryptographic bases.

Beyond the testing of the products themselves, there could easily be businesses set up to provide secure protections to individuals and companies like a digital Pinkerton’s for digital assets. It is likely that those who can afford digital anonymity will be the first to take measures to regain it. To paraphrase a concept from a famous American financial radio show host, privacy could replace the BMW as the modern status symbol. The top income earners who want to protect themselves and their companies will be looking for a type of “digital Switzerland.”

Regaining privacy will likely democratize over time as the general population will demand the same protections as the 1%-ers. Edward Snowdon showed us that everyone is under some sort of surveillance, so we have to face the facts that data gathering on a grand scale is part of the world now and will only grow in scope. However, we don’t have to just accept insecurity because things can be done, including adding secure devices to digital systems.

The Future Belongs to the Middle Classes

Maybe the most important factor noted in the Alternative World report has to do with the forthcoming growth of middle classes. As populations increase and more people worldwide move into the middle class, a growing number of people and things will be connected. That is why the Internet of Things is expected to grow so quickly. More connected things means more points of attack, and more data gathering for legitimate and illegitimate purposes. Therefore, the need for digital security is tied directly to the number of communicating nodes, which is tied directly to the growth of the middle class. More people with financial means means there will be more things to secure. This is becoming obvious. The middle class buys the lions’ share of products and services, and more of those products and services and how they will be ordered and delivered will be electronic. More people, more electronic things, more need for security.

When it comes to population, South and East Asia are the elephants (and dragons) in the room, as the chart below demonstrates.

The most powerful trend going forward is arguably the emergence of new “super-sized” middle classes in China and India. The worldwide middle class will grow exponentially, and it has already started to super-charge demand for food, energy, and manufactured products — particularly smart communicating electronic devices, many with sensing capabilities. That, of course, is how the IoT is getting started. Major companies are holding out the IoT as a way to drive efficiencies in production and distribution while keeping costs low. You can see that in the literature of major companies such as GE who is targeting the Industrial Internet of Things as a major strategic vector.

Population and purchasing power go hand-in-hand, and the evolution of smart, secure, and communicating systems will follow. As Stalin said, quantity has a quality all its own. That is why Asia matters so much.

From the demographic analyses, you can see that most Digitopians will be physically living in South and East Asia and this will continue to rise with time. So, what does that mean for security and privacy?

There is a very different view of the privacy rights in Asia due to a varied tapestry of intricate and ancient cultures — cultures that differ from Western traditions in many ways. However, it must be pointed out that that Western governments are far from the white-knight protectors of privacy rights by any means. Even with uncertainty in how privacy will be embraced (or not) long-term woldwide, in the short- to medium-term, enhanced security will have to filter into networks, systems, and end products, including the IoT nodes. You can look at that as securing the basic wiring and digital plumbing of Digitopia, even if governmental institutions retain the right to snoop.

Practical Security

To close on a practical note, in the short- to medium-term there will be a strong drive to embed more robust security to embedded systems, PCs, networks, and the Internet of Things. Devices to enhance security are already available, namely crypto element integrated circuits with hardware based key storage. Crypto elements are powerful solutions, whose fundamental value is only starting to be recognized. They contain cryptographic engines to efficiently handle crypto functions such as hashing, sign-verify (ECDSA), key agreement (ECDH), authentication (symmetric or asymmetric), encryption/decryption, message authentication coding (MAC), run crypto algorithms (elliptic curve cryptography, AES, SHA), among many others. Together with microprocessors that run encryption algorithms crypto elements easily bring all three pillars of security (confidentiality, data integrity, and authentication) into play for any digital system.

As certain forces move the world towards less privacy and more insecurity, it is good to know that there are real technologies that have the potential to move things back in the other direction. To make a fearless forecast, it seems that going forward companies will increasingly be held liable for security breaches, and that will force them to provide robust security in the products and services that they offer. Consumers will demand security and enforce their preferences with class action legal remedies which they are damaged by lack of security. The invisible hand of the market will point towards more security. On the other hand, governments will argue that they have a duty to provide physical and economic security, which gives them license to snoop. Countervailing forces are in play in Digitopia.

Bill Boldt, Sr. Marketing Manager, Crypto Products Atmel Corporation