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Intel to Buy Altera?

Intel to Buy Altera?
by Paul McLellan on 03-28-2015 at 1:05 pm
Categories: FPGA, Intel Foundry, TSMC

You may already have heard today’s big news in the semiconductor fabless ecosystem that Intel is apparently in talks to buy Altera. I embarrassed myself predicting that Samsung were in talks to buy Freescale (which, of course, they might have been but NXP won that particular race). But this time it is definite enough that the WSJ covered ittoo. Altera had a market cap of $10.4B so this is a big acquisition, up there with the aforementioned NXP/Freescale merger.

The Wall Street types (by which I mean people who work in finance, not the WSJ people) are all trying to predict the effect that this will have on TSMC, since they assume that if the deal is done tomorrow morning that Intel will be making all Altera FPGAs from, maybe, tomorrow evening onwards.

But here is the reality. Altera used TSMC down to 20nm. Then it famously switched to Intel foundry for 14nm. It is right now working on taping out those first parts. On their earnings call they admitted that this was slipping from Q1 to Q2 (to be fair, Xilinx said the same thing about their parts in TSMC 16FF+). I would not in the least bit be surprised to find that they slip further still since I have heard that the program is not going smoothly. Switching from a foundry that truly knows what is doing, TSMC, to one that is just starting in the business, Intel, was never going to be easy.

Once those parts tape out (let’s be generous and keep to the Q2 estimate) they need to be prototyped and then early production parts shipped to customer to design them into things like LTE base-stations or routers, then those systems need to go into manufacturing and get into volume and then Altera will get volume orders. That will be in 2017 or 2018. Until then, every FPGA that Altera ships will be manufactured by TSMC. If that sounds a little unlikely, it is just the same as Intel’s LTE modem line which is also manufactured by TSMC and not in-house at Intel, and is unlikely to be until 2017 it seems. And that is a part that they would dearly love to bring inside since it means they can then integrate it with their application processors for tablets and mobile.

In the meantime, every part shipped by Xilinx will also be manufactured by TSMC (or maybe there are some very old parts still shipping from UMC, Xilinx’s old foundry until 28nm) and every Lattice part will ship from UMC.

This makes it all sound very important but actually the number of wafers that FPGA companies need is not that high compared to anything going into mobile devices.

In my opinion this is really negative for Intel foundry. The implication is that Intel cannot compete in foundry without owning its customers. The only other publicly announced foundry partners for Intel I know of are Tabula (who shut down recently) and Achronix. Both Tabula and Achronix have Intel as an investor, so partially owning their customer. Also they were both in the FPGA business and so compete with Altera. I’m guessing that Achronix will not be happy if this happens.

See also Tabula Closes Its Doors

Another wrinkle. Altera have a close relationship with ARM. In fact their next generation products (the one that Intel will make) contain ARM processors. That was unlikely enough when Intel was the foundry but Altera was the company designing the parts and selling them. If Intel buys Altera then they will be designing, marketing and selling ARM parts. Given Intel’s obsession with Atom (see Intel’s failed mobile strategy) I wonder how that will play out.

See also Pigs Fly. Altera Goes with ARM on Intel 14nm

I talked to Xilinx but after thinking for a bit they decided not to comment. And kudos for Kevin Morris at EE Journal for his piece last year When Intel Buys Altera.

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CEVA Eyes DSP Scale in China’s $65 LTE Handsets

CEVA Eyes DSP Scale in China’s $65 LTE Handsets
by Majeed Ahmad on 03-27-2015 at 8:00 pm
Categories: Ceva, EDA, Mobile

China Mobile’s bid to go for 3-mode Long-Term Evolution (LTE) has led to the first major breakthrough, $65 LTE handsets, and here baseband and application processors provided by chipmakers like Leadcore Technology, MediaTek and Spreadtrum Communications have all one thing in common: DSP cores from CEVA Inc.

The advent of the $65 LTE handsets in the world’s largest mobile phone market could reinvigorate the smartphone boom all over again. Here, it’s important to note that signal processing is the centerpiece in two of the major building blocks of the LTE technology: orthogonal frequency-division multiplexing (OFDM) and multiple-input multiple-output (MIMO). Not surprisingly, therefore, DSP socket supplier CEVA is seeing China’s expected 300 million new LTE subscribers in 2015 with a lot of hope and excitement.

The CEVA-XC soft-modem for LTE baseband chips

In 2014, there was an interesting twist to China’s LTE story when China Mobile decided to reduce the LTE format specifications to 3-mode products. Within the LTE standard domain, 3-mode products support GSM, TD-SCDMA and TD-LTE cellular standards for 2G,3G and 4G wireless communications, respectively. These wireless standards are predominantly used in China, so inevitably, 3-mode LTE would be more suitable for China’s chipmakers and smartphone manufacturers.

The international version—5-mode LTE—supports GSM, W-CDMA, TD-SCDMA, TD-LTE and FDD LTE and favors chipmakers like Qualcomm who have a global footprint. Apparently, China Mobile’s bet to stick with TD-LTE has started to show results with the launch of inexpensive smartphones. And China Mobile, one of the three large cellular operators in mainland China, is expected to consume 50 percent to 60 percent of these 3-mode LTE phones.

CEVA’s Smartphone Sockets

In January 2015, the trade media in China reported Xiaomi launching a $65 LTE phone that sported mobile chipset from Leadcore Technology. Leadcore, which uses DSP cores from CEVA, has actually replaced Qualcomm’s Snapdragon 410 that Xiaomi used in its earlier Redmi 2 handset. Qualcomm uses its proprietary Hexagon DSP cores in the Snapdragon chips.

Likewise, TCL’s upcoming LTE phone for China Mobile is reported to cost $65 and is based on MediaTek’s quad-core MT6582 application processor and LTE MT6290 modem chip. Again, MediaTek licenses CEVA-X DSP cores and subsystems from CEVA. Next up, Spreadtrum, another licensor of CEVA DSP cores, is supplying SC9620 LTE baseband chips to Coolpad and Lenovo handsets. Spreadtrum claims to have shipped 30 million CEVA-powered baseband chipsets.

Lenovo a388t phone features a DSP core from CEVA

Winning DSP sockets in China’s volume 4G wireless market could be a vital breakthrough for CEVA, but the DSP licensor of baseband chips is not putting all its eggs in China’s 3-mode LTE basket. CEVA has also scored an important design win in Samsung’s Galaxy phones.

Samsung is trying to reinvigorate its Exynos SoC with the help of LTE application processors. According to Forward Concepts, which focuses on DSP-centric wireless communications market research, Samsung’s quad-core Exynos ModAP is the Korean firm’s first generation of integrated LTE modem-application Processor solution with multimode LTE connectivity. The second one is the Exynos 300 modem that supports LTE-Advanced. Both modem chips are based on CEVA DSP cores.

CEVA claims to have shipped DSP sockets in more than 1 billion chips in 2013 and around 40 percent of these chips went into mobile phones. Wireless baseband chips inside smartphone are a key volume market for CEVA and China’s great baseband game could well bring the next big growth opportunity for the DSP licensor. According to industry research firm Strategy Analytics, CEVA licensees MediaTek and Spreadtrum rank second and third, respectively, after Qualcomm in the global mobile baseband chip market.

About DSP Socket in Smartphones

The DSP part is now predominantly used in system-on-chip (SoC) solutions for communication and consumer markets, and here, mobile phones constitute the largest segment for DSP cores. All baseband chips carry one or two DSP cores. On the baseband side, the voice signal needs to be digitized and compressed, modulated onto a wireless signal, transferred through the wireless infrastructure to the other end of the call, and decompressed again.

According to a recent newsletter of Forward Concepts, even application processor have now started to deploy DSP functionality, either as co-located DSP cores or as SIMD extensions to the CPU instruction set. On the application processing side of a mobile phone, data files containing video, images and audio need to be decoded and sent to the device’s screen, speakers and headset, all very specific DSP tasks.


CEVA’s DSP solution for mobile handsets

The CEVA DSP cores allow both hybrid and soft modem approaches for developing mobile baseband chips. For the hybrid approach, which mixes hardwired design with a programmable processor, the CEVA-X family of multi-purpose DSP cores enable a high level of concurrent instructions processing as well as low power consumption.

The CEVA-XC family of DSP cores, built on the CEVA-X processors, offers a complete soft-modem implementation, supporting multiple wireless standards concurrently on the same chip in software. They use a single engine for all wireless processing and thus eliminate the need for multiple baseband co-processors. That way, the CEVA-XC DSP cores reduce power consumption and die size related to additional memories, data buffers and overall data traffic.

Also see CEVA and LTE: Happy Together

Majeed Ahmad is author of books Age of Mobile Data: The Wireless Journey To All Data 4G Networksand Essential 4G Guide: Learn 4G Wireless In One Day.

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Full-chip Multi-domain ESD Verification

Full-chip Multi-domain ESD Verification
by Paul McLellan on 03-27-2015 at 7:00 am
Categories: EDA, Silicon Frontline

ESD stands for electro-static discharge and deals with the fact that chips have to survive in an electrically hostile environment: people, testers, assembly equipment, shipping tubes. All of these can carry electric charge that has the “potential” (ho-ho) to damage the chip irreversibly. Historically this was a problem only for I/O pads which had to take care to dump the unwanted influx of charge without harming any of the on-chip transistors. There are three models for the aggressor, almost always just identified by their acronyms: human body model (HBM), machine model (MM) and charged device model (CDM). They all inject charge in various well-specified ways, using circuits involving capacitors, resistors and inductors.

In modern chips, with thinner gate oxides and multiple power domains, ESD is not an issue confined to the pad-ring. ESD protection devices need to be included in the core. Of course many chips are bumped and in that case the pads are often not confined to the “pad-ring” since there is none, but even chips where the pads are at the edge of the chip can suffer internal failures from ESD. The ultimate way to check ESD is with a real chip and real ESD test equipment, but obviously, except in the case of a test-chip, that is too late to address any issues.

ESD cells and devices such as diodes, transistors, clamps, and so on, consist of a large number of elementary devices that are interconnected by metal layers to provide sufficient ESD protection. Detailed understanding of the current flow and potential distributions in these interconnects and devices is important to optimize the device layouts and to ensure a balanced current distribution, low resistance, and efficient connection of devices to power nets. Standard parasitic extraction and simulation approaches are inadequate to describe these effects.

Silicon Frontline’s ESRA (ElectroStatic Reliability Analysis) fills this gap and provides a full-chip ESD analysis solution. It delivers extraction, analysis and debugging capability in one integrated environment with the capacity to analyze the full chip. Highlighted violations permit designers to perform corrections at any time in the design process.


ESRA builds on production-proven technologies, including fast and guaranteed accurate parasitic extraction and circuit-proven, high-capacity matrix solvers. Layout based, full-chip visualization and debugging of current density and potential distribution is included, and the whole solution is seamlessly integrated within existing layout flows.

ESRA automates verification of ESD protection networks for electrical connectivity, resistance, and current density checks. It:

  • replaces manual ESD checks with well defined automated checks
  • offers a new verification methodology that quickly identifies issues in the layout, and analyzes weak elements of ESD network
  • provides a detailed (mesh-based) simulation and analysis of ESD protection devices and network elements, ensures the efficiency of electrical connections, and their compliance with current density and resistance rules
  • enables early capture of ESD protection problems avoids expensive silicon re-designs and re-spins

Problems can be displayed graphically annotated onto the layout by highlighting problem areas using color.


In summary, ESRA verifies that ESD design guidelines are met, highlights weak areas of designs, reports current density violations and high resistance paths. Details of ESRA are on Silicon Frontline’s website here.

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Medicals Marriage with Semis

Medicals Marriage with Semis
by Pawan Fangaria on 03-26-2015 at 7:00 pm
Categories: EDA, Foundries

I remember a couple of decades ago, my father used to go to a nearby doctor’s clinic to get his blood pressure and sugar levels checked. I guess, in around 1990s small electronic kits became available to measure these usual daily health indicators and instantly display the numbers. I bought a few for my father then. Today, the scene is very different. Even your ECG (Electrocardiogram) can be done at your home, office, or wherever you are through a small portable and very much affordable ECG machine. There can be many such other examples. The ubiquity of such small and powerful healthcare systems has been possible with the infusion of semiconductor ICs and sensors into these systems. The semiconductor chips have not only disrupted the prices of computing and consumer electronics (e.g. PCs, mobile phones, households etc.), but also medical and healthcare systems. Along with making the prices affordable, the semiconductor chips have also made these systems automated and easy-to-use for the healthcare personnel, patients or healthy persons alike for preventive health check up.

It’s a very healthy sign that the medical semiconductor market is continuously growing. The ICs and sensors, specifically those used in small, powerful medical systems are driving the sales of ICs for medical purposes. The advancement has gone to the extent that a biotechnologically treated pill can also have micro-sensors, which after getting into your stomach can transmit intended signals about the condition of your stomach to the employed healthcare system (or even your Smartphone), and get out of your stomach with excretion without doing any harm to you.

The IC Insights’Medical Semiconductor Market Forecast report shows that the worldwide medical semiconductor sales CAGR (Compounded Annual Growth Rate) between 2013 and 2018 can grow to ~12.3% with a total sale reaching to $8.2 billion by the end of 2018. The CAGR was ~6.9% between 2008 and 2013. As we know, a medical semiconductor system may consist of optoelectronic, sensor/actuator or discrete (O-S-D) components along with the ICs, the report further suggests that the O-S-D portion can rise at a CAGR of 20.3% while IC portion can rise at a rate of 10.7%; albeit the total IC portion by the end of 2018 stays higher at $6.6 billion compared to $1.6 billion of O-S-D.

The O-S-D components are frequently used in optical imaging and diagnostic equipments. The advancements in SoCs, MEMS (Micro-electro-mechanical systems), and analog front-end data converter technology has given rise to portable and smaller size healthcare equipments which can be used at other places then just hospitals. Since their prices have also reduced significantly, they have become more affordable. This has opened up a new market for semiconductor medical ICs, embedded sensors and systems.

Today, small imaging systems can cost one-tenth the price of large diagnostic systems (such as MRI or CT scanners) installed in hospitals and can be used in doctor offices, clinics, or elsewhere. Wearable devices such as fitness band, sleep pattern monitor, cardiac monitor, and so on are giving rise to another dimension in the medical semiconductor system market. In this market, software apps are equally important along with the hardware medical systems.

It’s not only towards making portable medical systems, development of more powerful and integrated large medical systems are also happening that can be used at large scale. These systems can lower healthcare cost for treatment of severe ailments such as cancer which were either not possible or out of reach for common people due to their prohibitive costs. Detection of diseases sooner than later and preventive treatment including less invasive surgery has become possible today with the use of semiconductors. It is expected that the total medical electronics systems sales can reach to ~$70 billion by the end of 2018.

Semiconductors and medical systems are complimenting each other; the semiconductors make the medical systems available and affordable while the medical systems drive the growth of semiconductor market. Happy Marriage!!

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Verification IP for PCIe and AXI4

Verification IP for PCIe and AXI4
by Daniel Payne on 03-26-2015 at 2:00 pm
Categories: EDA, Siemens EDA

Engineers love acronyms and my latest blog post has three acronyms in the title alone, so hopefully you are doing or considering SoC designs with the AMBA AXI4(Advanced eXtensible Interface 4) interface specification along with PCI Express (Peripheral Component Interconnect Express). One big motivation for using semiconductor IP and verification IP along with standards is that you can get your new product to market faster, with fewer bugs and using the minimum engineering effort. When you hear the phrase “Verification IP” your mind may quickly jump to vendors like Cadence or Synopsys, however Mentor Graphics is also in this business as well. Doing just a quick Google search on the phrase “Verification IP” turned up these three EDA vendors, along with SemiWiki in the #4 position:

Mentor produces something called the Verification Horizons Newsletter, where I read an article by David Aerne and Ankur Jain, “Fast Track to Productivity Using Questa Verification IP“. Here’s what to look for with any verification IP:

  • Proven by multiple customers
  • Checks for compliance to each protocol
  • Has a compliance test suite
  • Gives engineers analysis coverage

Related – Virtual Emulation Extends Debugging Over Physical

Integration

Let’s say that your DUT (Design Under Test) is a PCIe using RC (Root Complex). The design IP along with verification IP would look like this:

QVIP stands for Questa Verification IP, a Mentor product name. The QVIP has wrapper modules for each use case, making integration connection easier. Interface types supported for PCIe QVIP include: Serial, Pipe, PIE8 and MPCIe.

Configuration

Verification engineers can quickly configure each QVIP to model a PCIe End Point (EP) or Root Complex (RC) using a descriptor. This descriptor approach is quicker than writing UVM (Universal Verification Methodology) code to create analysis ports.

Related – UVM Debugging Made Easy & Productive in Questa

Here’s what an example PCIe QVIP configuration looks like:

Further automation allows you to bring up a PCIe test bench using a sequence at a high level, shown in this code fragment:

Starter Kits

Buying your design IP and then getting them to work with Mentor’s QVIP is enabled through quick starter kits that allow you to install, instantiate, configure and bring up QVIP in a work day:

Related – A Functional Verification Framework Spanning Simulation to Emulation

APIs

Generic APIs are provided that let you use read and write commands across all of the ARM AMBA protocols: AHB, AXI3, AXI4, ACE and CHI.

This generic API approach makes it easier to verify each SoC that uses ARM AMBA protocols.

Summary

Mentor Graphics does offer verification IP called QVIP that makes the task of SoC verification easier to bring up for the most popular protocols like AMBA AXI4 and PCIe bus interface. Connectivity modules, configuration, quick starter kits and portable utility sequences help automate the verification tasks. Monitors with QVIP ensure protocol compliance, and for analysis you get scoreboard and coverage collectors. Your verification team can track and achieve coverage goals by using the test suites and functional test plans.

Automation is your ally for verification, and Mentor’s QVIP can help. Read the full newsletter article here.

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25 Years of SNUG; 50 Years of Moore’s Law

25 Years of SNUG; 50 Years of Moore’s Law
by Paul McLellan on 03-26-2015 at 8:00 am
Categories: EDA, IP, Synopsys

Earlier this week it was the Synopsys user group meeting SNUG. Not just any old SNUG but the 25th Annual SNUG. The first one was 15th March 1991 and was attended by 100 people. At the time, Synopsys had annual revenues of $22M. This year, the various SNUGs around the world will have a total attendance of 10,000 people and Synopsys revenue is $2.2B.

Aart de Geus, co-CEO of Synopsys, gave the keynote as usual. Since it was the same Shift Left keynote as he gave earlier at DVCon that Dan already wrote about, I won’t cover it in detail.

See also Shifting Chip Design Left

But as Aart pointed out, there is an even more important anniversary coming up in 28 days (down to 25 now), the 50th anniversary of Moore’s Law. In Electronics Magazine on April 19th 1965 Gordon Moore (at the time still at Fairchild) published an article titledCramming more components onto integrated circuits. Everyone in semiconductors knows what Moore said about doubling of transistors and probably have seen the original graph that he published in the article. What I think is perhaps even more amazing is that the second paragraph of his article said:Integrated circuits will lead to such wonders as home computers…automatic controls for automobiles, and personal portable communications equipment.

Remember, this was 1965. The Beatles were still two years away from putting out Sergeant Pepper. Gordon Moore himself was still 3 years away from founding Intel. Computers filled rooms. Touch-tone phones had not yet been introduced. This was an extraordinary prediction when an integrated circuit did not contain billions of transistors but just 64.

During his keynote, Aart pointed out that he was using the term Moore’s Law in an imprecise sense. I have always liked to use Moore’s Law backwards, namely that the cost of any given functionality implemented in silicon halves every couple of years. That exponential cost reduction means that our smartphones contain much more powerful graphics than a multi-million dollar flight simulator used to.

However, that aspect of Moore’s Law is now broken. Yes, for chips that can make use of it there will be wonderful capabilities at 14/16nm, 10nm, 7nm. Much lower power. Much higher performance. Another factor of 10 in integration. But not lower cost. As FinFet volume manufacturing builds up, perhaps 16nm will eventually be cheaper than 28nm, but for sure not by as much as we have been used to (the rule of thumb used to be twice the number of transistors, 15% increase in wafer cost, so 35% reduction in cost per transistor). That is why so many people are predicting that 28nm will be a very long-lived process. Double patterning (necessary below 28nm) is an impossible additional cost to swallow completely.

One of the new areas of business for Synopsys has been from their Coverity acquisition. One result is that Synopsys have changed the tagline under their logo to From Silicon to Software. Another result of that is that Synopsys themselves have discovered that they have one of the largest code bases around at over 400M lines of code (LoC), around the same number of DNA base-pairs as a mouse. Coverity is about 5% of Synopsys revenue (IP is 25% and the rest is EDA software).

Software development groups are starting to need the same sort of discipline as chip design groups have had for many years. If a chip doesn’t work it costs millions of dollars for a respin, whereas software has a “patch it later” attitude. But as software finds its way into medical devices, cars (not to mention the arrival of IS26262) and, especially, as security moves towards being mission critical, then software has had to adopt similar approaches to quality and testing. After all, what is “fuzzing” apart from another name for “constrained random.”

Aart had 3 lessons from chip design for software:

At the press lunch, Aart talked a bit about IP and how a modern process is simply not viable on its own. It doesn’t just need EDA flows and foundation IP like standard cells and memories. It also needs a portfolio of microprocessors, PCI, USB, DDR and so on. Without it only the largest and most advanced SoC groups can think about doing a design since they will need to design all that IP themselves. As a result Synopsys are working on 10nm IP and FD-SOI IP. They already have lots of 10nm active designs.

Aart reminisced that when he was an undergraduate at school in Switzerland everyone just knew that 1um was the ultimate limit for IC design. Well, that day came and went and we are now at 10nm. We can see about another 10 years ahead today, but then that has pretty much always been the case. It will be interesting to see what comes next.

The SNUG 2015 proceedings page is here.

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Innovative MIPI Display Solution for UHD Mobile Devices

Innovative MIPI Display Solution for UHD Mobile Devices
by Pawan Fangaria on 03-25-2015 at 7:00 pm
Categories: EDA, IP, Synopsys

Today an SoC cannot be without multiple IP blocks integrated together in the most optimal manner. In such an environment, it’s natural that interoperability and configurability of an IP get prime considerations to achieve the best PPA (Power, Performance and Area) for the SoC containing that IP. While PPA is a basic criterion to must achieve, it’s heartening to see IP providers partnering and going beyond PPA to create interoperable solutions that enable next generation technology and devices.

In the modern electronic world, high resolution displays like UHD (Ultra High-Definition) and 4K requires very high bandwidth, of the order of 16Gbps; the bandwidth requirement keeps growing rapidly with higher resolutions. It’s just not possible to keep transmitting video signals at such high bandwidth by using the same old methodology. Synopsysand Hardenthave worked together to develop an innovative Display solution for ultra-high resolution in UHD mobile devices and other next-generation devices utilizing resolution of 4K and beyond. The solution is a combination of Synopsys’ DesignWare MIPI DSI Host Controller IPand D-PHY, and Hardent’s VESA DSC Encoder IP.

To know more about this, I had a phone conversation with Alain Legault, VP of IP products at Hardent. Alain tells me that the effort to establish a DSC standard for ultra-high resolution technology started in Jan 2013 when VESA(Video Electronics Standards Association) setup the DSC Task Group. The DSC 1.1 was released in July 2014 in collaboration with MIPIwho supports DSC (Display Stream Compression) in DSI (Display Serial Interface) 1.2. Hardent has been a member of the DSC Task Group since it began and is the first to come up with the DSC IP. With Synopsys’ MIPI compliant DSI and D-PHY IP,the companies create a complete interoperable Display subsystem.

The DSC solution reduces data transmission bandwidth by compressing and transmitting video signals through existing display interfaces for ultra-high resolution. The DSC IP is fully compliant with DSC 1.1 and enables visually lossless video compression between the application processor and the display module inside a mobile device. It reduces the DSI transmission bandwidth by up to 3x, thus requiring smaller frame buffer and lesser transmission lanes for lower pin count. This clearly reduces cost as well as power consumption and electromagnetic interference (EMI). More information about the DSC IP offering can be obtained from the datasheet here.


[DesignWare DSI Host Controller IP Block Diagram]

Synopsys provides a fully verified and configurable DesignWare MIPI DSI Host Controller IP that is compliant with the latest MIPI AllianceDSI specification v1.2. It supports all commands defined in MIPI Alliance DCS (Display Command Set) and interfaces with MIPI D-PHYs that support the PHY Protocol Interface (PPI). Along with DesignWare MIPI D-PHY, the host controller provides a complete and interoperable display solution that lessens designers’ risks of integrating the MIPI DSI interface into application processors, display bridge ICs and multimedia co-processors. The DesignWare IP supports dual MIPI DSI with VESA DSC 1.1 standard.

Synopsys has been a leading member of MIPI Alliance Display and PHY working groups for several years and has provided MIPI IP with hundreds of design wins to support mobile ecosystem with innovative display interfaces complying with MIPI standards.

On my concern about the quality of the Display subsystem, Alain tells me that it’s visually lossless compression. They experimented with thousands of transmitted video images with and without compression and asked a large group of individuals to participate in a formal test to identify any difference between them; no perceivable difference could be found by the participants between the original and the DSC encoded video images. He says, this solution is scalable to target a required display resolution (4K, 5K or 8K) and provides an ecosystem in the mobile market to offer high-definition devices. Leading SoC vendors have adopted this solution. Silicon products based on this display solution are expected to come in the market by the middle of this year.

This Display solution is fully compliant with MIPI and VESA standards and is highly interoperable. Synopsys and Hardent jointly announced the availability of this new solution for next-generation displays in the MIPI Alliance’s open day in Seattle. Read the press release here.

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Chips and pins and layers within

Chips and pins and layers within
by Don Dingee on 03-25-2015 at 3:00 pm
Categories: EDA

After teams sweat the details of SoC and industrial design, they turn to printed circuit board designers for magic. Here are a pile of chips and passives, and a schematic for interconnecting them. This is how much physical space the board can occupy. Connectors have to be here, and here, and mounting holes there, and there. There are a few constraints in power domains, signal routing, and thermal hotspots to worry about. From that point, skilled PCB layout artists create and cross check the layout, and the Gerber files go off to the board house for fabrication. Continue reading “Chips and pins and layers within”

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The Apple A9 Samsung & TSMC Love Triangle

The Apple A9 Samsung & TSMC Love Triangle
by Robert Maire on 03-25-2015 at 10:00 am
Categories: Foundries, Samsung Foundry, TSMC

The Apple A9 drama continues to play out with no certainty!
At the end of the day does it matter?
Will the winner be the loser?
A Comedy, Tragedy or Love Story?
Depends on your view…

Act I Scene I…The stage is set….

We are watching an Italian Opera of a standard love triangle….
The object of desire is the rich and beautiful Princess Iphonia Applelina being pursued by Prince Don Samsune and Count Don Tsemcee. Each is trying to prove their love for the princess. There are rumors swirling around about whom the princess has secretly promised her love and fortune to. The respective villages of the two suitors are both claiming that their nobleman is the one and true love of the princess whose heart has been betrothed to him.

The plot is further complicated by the young and sexy Countess Snap Dragonee from Qualcomia who is trying to steal away both suitors with her charms. In the background, the mysterious Arabian merchant Glabal Faadhil is hoping to have an affair with the princess so that he may get some of the leftovers of her fortunes. Meanwhile the princess has said nothing publicly except that the Crown Ball for her engagement party will be in the fall of the year but no one yet knows who will be on her ARM for the affair. The opera is full of the standard bit players of servants and interested parties who all have an axe to grind and an interest in the outcome. The endless rumor mongering of an opera is at full farce…..

How will this end?
Who will win? and who will lose?
The fat lady has yet to sing……

We still don’t know & we wouldn’t trade on it
We have been back and forth with the trade “rags” in Taiwan and Korea each claiming victory for the local team. This volley started months ago and its still likely too early to tell for sure. Now the latest rumor is that yield issues at Samsung has pushed business in the direction of TSMC. We don’t understand how this is new news as we have been very publicly talking about disappointing yields at Samsung for months now and how it doesn’t make either mathematical of financial sense given the current yields we have heard about.

Analysts are out there touting this as incremental information. Additionally its unclear that no matter what the financial arrangement that Apple would risk the iPhone 6S roll out on unstable process and poor yields. Is the A9 business really fungible?

The reality is that the Samsung 14nm process and the TSMC 16nm process flows are pretty far apart. The TSMC process is much more conservative and more like a warmed over 20nm design with FinFET rather than a full on new process which is closer to the Samsung description. Its not as if the business can be switched back and forth at the drop of a hat. As we have said in the past, Apple could “tape out” two designs, one for Samsung and one for TSMC and follow through to the end but obviously that’s a lot of work. They already have to tape out two designs, one for the A9 and one for the A9X (the Ipad processor) so we would really be talking about 4 potential designs.

Its likely a zero sum game

There is only so much foundry capacity in the world to go around at the leading edge. If it isn’t used for Apple its going to get used for Qualcomm or others. Whoever doesn’t win the Apple business will get Qualcomm’s business, which as far as I can see is not all that shabby.

This is much like all the speculation on Wall Street as to who won the DRAM contract for which phone and which device. In memory there is contract and spot pricing. Though its always nice to have a “locked in” contract , the reality is that the spot market is more profitable over the longer term as contracts are at a substantial discount to the spot market. So, are the DRAM contract winners really the stocks I should buy??

Will the winner be the loser?
Is the winner of Apple’s A9 business the real loser? Given the pricing we would expect and the way Apple treats its suppliers we think we know the answer to that question. So what does the winner get? Bragging rights? You can’t pay the rent or buy new chip tools with bragging rights. Investors seem to want to buy whomever wins the A9 business or whomever wins the DRAM contract but maybe they are buying the real loser in terms of financial performance. Spending this amount of time, ink and internet bandwidth over who has won what percentage of Apple’s business is not as productive nor as accurate a predictor of who the financial winner is or what the stock will be 6 months or a year from now.

Apple’s the real winner here…
Apple is playing its suppliers like a Stradivarius. We wonder when Apple will have its suppliers paying them to supply them parts. Much like the princess, Apple can lead both suitors on ad nauseam. They will kill one another to get to yield faster at better pricing. We wouldn’t cry for Qualcomm either as they get the benefit of Apple pushing the envelope so hard and can fall under Apple’s pricing and technology umbrella.

More like a TV soap opera…..
Whereas a real opera has some sort of an end, even though many end unrequited, this opera will go on almost forever. We will hear daily and weekly updates on the the dalliances of the players and it won’t end when the A9 winner is chosen because then we will have the A10 and A11 and on and on… This is going to be syndicated into endless reruns.

The stocks!
To be clear, we think that its near impossible to draw a very strong correlation between who wins what contract and the stock price. While it may lift revenues and bragging rights, its unclear as to the benefit to the bottom line. As we had mentioned in a previous note we thought that winning a bigger slice of the A9 pie could cause Samsung to choke on it when the semiconductor business is the only one making money there.

Also read: TSMC 2015 Technology Symposium

We continue to think that TSMC has played the smarter game in dealing with Apple and appears to be playing a more predictable, conservative game and remains very, very focused on the bottom line. For the equipment companies we could yet see a sudden rush of orders once the fat lady sings and one of the players actually has to produce the A9 in volume to make the iPhone 6S Crown Ball in the fall of this year. Until there is more clarity, we wouldn’t jerk around our portfolio based upon the rumor du jour as to who has what A9 business or it could wind up as a tragedy……..

Bravo!! Bravo!!

By Robert Maire
Semiconductor Advisors LLC


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TSMC 2015 Technology Symposium

TSMC 2015 Technology Symposium
by Paul McLellan on 03-25-2015 at 7:00 am
Categories: Foundries, TSMC


This year’s North American TSMC Technology Symposium is fast approaching. There are three, starting in Silicon Valley.

  • San Jose on Tuesday April 7th at the San Jose Convention Center
  • Boston on Tuesday April 14th at the Burlington Marriott
  • Austin on Thursday April 16th at the downtown Hilton

The symposium will also take place in Shanghai (date tbd), Hsinchu (tbd), Amsterdam (6/16), Herzliya (6/29), Yokohama (tbd).

Another save-the-date to put on your calendar is the 2015 TSMC OIP Ecosystem Forum which will take place in Santa Clara on 17th September.

What will you hear about if you attend? The current status of all things TSMC and roadmaps for the future. In more detail:

  • update on TSMC’s processes including 16FF+, progress at 10nm, to infinity and beyond
  • specialty technology portfolio including image sensor, embedded flash, power IC, MEMS, and the ultra-low-power ULP processes
  • GIGAFAB ramping capabilities and plans
  • advanced backend technologies including CoWoS, InFO and more
  • OIP (open innovation platform) EDA and IP ecosystem: 16FF+ and 10FF status

Of course, if you are going to attend, you should go all day. But the program for the day (at all 3 locations) is:

  • 8.30 onwards: registration is open
  • 9.35 to 9.50: welcome remarks (Rick Cassidy, President TSMC America)
  • 9.50 to 10.30: industry overview and corporate update (Mark Liu, co-CEO)
  • 10.30 to 10.50: coffee (and ecosystem pavilion will be open)
  • 10.50 to 11.20: technology leadership
  • 11.20 to 11.40: design solution and enablement
  • 11.40 to 12.10: manufacturing excellence
  • 12.10 to 13.10: lunch (and ecosystem pavilion will be open)
  • 13.10 to 14.10: advanced technology updates
  • 14.10 to 14.40: design enablement, flows and services
  • 14.40 to 15.10: coffee (and ecosystem pavilion will be open)
  • 15.10 to 16.10: specialty technology updates
  • 16.10 to 16.40: advanced backend technology
  • 16.40 to 17.30: social hour in the ecosystem pavilion

I will be there. The reason that I think you should be too (assuming you work with TSMC) is that this is one of the very few occasions during the year where you will hear senior TSMC executives talk about their future direction and current status. It is much more compelling, for example, to hear the head of TSMC’s manufacturing talking about fab ramp plans or to hear about 10nm from the head of the organization responsible for developing the process than it is to read a dry press release later in the year.


You can register for the technology symposium here.

“The future of the semiconductor industry is promising with many growth opportunities ahead. To capture these opportunities, we need to continue to work as a collaborative innovation force. Together, we will help each other grow business and stay competitive. This vision is the foundation for the TSMC Grand Alliance. At TSMC, customers are always at the center of all our efforts. With this spirit, TSMC has become our customers’ TRUSTED technology and capacity provider along the way.”