Various foundries have made announcements about licensing FD-SOI technology from ST Microelectronics and then fallen quiet. GlobalFoundries made an announcement a couple of years ago. Samsung made an announcement just before DAC last year. But neither company has said anything much since. Of course the big noise at 14/16nm is all around FinFET but the reality is that the number of designs moving to those process nodes is relatively small. Many designs are remaining at 28nm or larger processes (TSMC has re-architected their 45nm and 65nm processes to have ultra-low power versions for example). FD-SOI is seen as a good way to extend 28nm by giving it most of the characteristics of 20nm, even lower power if the biasing is used, at a slightly reduced cost since it is slightly cheaper to manufacture than bulk planar. In particular, I don’t see IoT designs being 14/16nm SoCs and older processes where the analog and RF are easier are probably going to be the workhorses for those markets (I hesitate to call IoT a market but it is certain that lots of devices will be connected to the internet in the coming years).
As if to emphasize this, Yongjoo Jeon titled his presentation 28FD-SOI Cost Effective Low Power For Long-lived 28nm.
Yongoo started with a history of technology migration. Down to 130nm we scaled everything including the gate-oxide thickness but that ran out of steam then. Since then we have had copper interconnect at 90nm, low-K dielectric at 65nm, stress engineering at 45nm and Hi-K metal gate (HKMG) at 32/28nm. Basically the era of material innovation. At 20nm planer hit the gate length scaling limit and the two structure innovations going forward are FinFET (at 22nm if you are Intel and 16/14nm if you are not) and FD-SOI (initially as a retro-fit to 28nm processes).
One of the challenges faced by FD-SOI has been the perception that it is only available and used by ST. Customers want alternative sources. Of course they need other stuff too, such as low cost per transistor, IP support, performance and, above all, low power. With Samsung, the worlds #2 (or #3 depending on how you count) foundry the process has a lot more credibility.
Last month in Tokyo was the FD-SOI and RF-SOI Forum in Tokyo Samsung presented on FD-SOI. Another interesting looking presentation is by Sony who are using 28nm FD-SOI for RF design, but their presentation is not yet available so I don’t have details, but the fact that customers (as opposed to foundries) are starting to endorse the process is more good news for the ecosystem.
Samsung emphasized the cost aspects since there are 289nm FD-SOI has fewer process steps than bulk 28HKMG and the BEOL (metal) is the same. The simpler process helps to offset the fact that the SOI substrate is more expensive than bulk.
Compared to 28HKMG the performance is better, the power is lower and the area is the same. And it is much better in all dimensions than either 45bulk or 28PSION.
Samsung emphasized that the better short-channel control means a shorter channel length and more gate bias. This gives two knobs to control performance and leakage. Gate CD-biasing, which is physical, and body-biasing which is electrical and can be used to reduce leakage when performance is not required or the circuit is idling. But where FD-SOI really shines is that the voltage can be further reduced down to 0.63V with reasonable performance and much lower power.
Samsung did a full qualification of the process completed in September 2014 and both the pmos and nmos transistors passed everything.
The business model on the IP side is that IP vendors will supply everything except the foundation libraries which will be delivered by Samsung themselves. I don’t know if any of this work is shared with ST or if Samsung have a completely separate ecosystem.Share this post via: