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Dealing with FPGA IP in all its forms

Dealing with FPGA IP in all its forms
by Don Dingee on 02-12-2015 at 10:00 pm
Categories: EDA, FPGA, Synopsys

One of the recurring themes I see here in the pages of SemiWiki and elsewhere is this pitched, bordering on religious battle between Altera and Xilinx. Just because both are FPGA technologies, the tendency is to put them in the same bucket, drawing direct comparisons between them. Some folks say there is no comparison; Xilinx has a significant lead in process technology and capacity, and is therefore “better” according to many comments.

From my perspective, the two approaches are very different – and always have been. Both have merit. That raises issues for both the purveyor and consumer of “FPGA IP”. Continue reading “Dealing with FPGA IP in all its forms”

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ADAS Going Mainstream One Chip at a Time

ADAS Going Mainstream One Chip at a Time
by Majeed Ahmad on 02-12-2015 at 1:00 pm
Categories: EDA, IoT, STMicroelectronics

Advanced Driving Assistance Systems (ADAS) are an essential element in the vision of autonomous or semi-autonomous vehicles, and they are becoming available today. The ADAS automotive technology raises driving safety by detecting obstacles around the vehicle such as other vehicles and pedestrians, as well as traffic signs and lane markings to automatically operate brakes or control speed and following distance.


(Image: CiA)

That makes ADAS a key highlight of the connected car movement. ADAS makes proactive use of the radar and camera technologies to improve safety and help avoid accidents. A number of chipmakers have recently unveiled ADAS components for both camera- and sensor-centric car safety features. Take STMicroelectronics’ imaging vision processor, EyeQ3, which it has jointly developed with Mobileye, a company that produces vision-based ADAS products for collision prevention and mitigation.

The EyeQ3 processor enables vision-based detection of pedestrians, vehicles, signs, and lane markings. ST demonstrated the EyeQ3 vision processor for ADAS applications at the 7th International Automotive Electronics Technology Expo in Tokyo, Japan last month. At the show, ST also demonstrated transceiver ICs for radars that emit millimeter waves to measure distance and the direction of obstacles around the vehicle.


STMicro’s vision processor for ADAS

Earlier, at the 2015 CES, NXP Semiconductors has demonstrated a fully integrated 77-GHz radar front-end IC based on RFCMOS technology. According to the company spokesman, it’s a complete radar system that, when used in combination with a back-end DSP or MCU, creates a compact two-chip solution.

24-GHz Radar Sensor

Infineon Technologies AG is also upping the ante on the ADAS front by integrating separate RF components for a radar sensor into a single transceiver that it calls microwave monolithic integrated circuit (MMIC). Infineon has joined hands with the German automotive supplier Hella KGaA Hueck & Co. to develop a sensor module that monitors the blind spot in the car’s rear section.


Infineon’s 24-GHz automotive radar system

Hella develops and manufactures components and systems for the automobile industry and has one of the largest retail organizations for vehicle parts, accessories and diagnostics in Europe. Moreover, it produces complete vehicle modules, air-conditioning and on-board network systems in collaborations with chipmakers like Infineon.

The driver assistance system that Hella has produced detects moving objects even in poor weather and warns of vehicles coming from behind while changing lanes and overtaking other vehicles. Hella’s 24-GHz radar sensor system for blind spot detection uses Infineon’s MMICs, fully integrated transceivers that contain all high-frequency components, like oscillators, transmission amplifiers and reception branches with low-noise amplifiers and I/Q mixers.

ADAS products for blind spot detection are gradually making headway in new vehicles. According to a Strategy Analytics study published in 2013, by the year 2020, the number of worldwide installed, radar-supported driver assistance systems is to rise from about 14 million to more than 40 million.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

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SEMI ISS: Samsung, the Keynote That Wasn’t

SEMI ISS: Samsung, the Keynote That Wasn’t
by Paul McLellan on 02-12-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

At the SEMI International Strategy Symposium last month, one of the keynotes was by Jim Elliot, the CVP of Memory Marketing for Samsung. Unfortunately, due to some personal emergency, he wasn’t able to make it. But he did allow the slides of the presentation he would have given to be put up on the SEMI website. So here, for the first time ever, Jim’s ISS keynote highlights.


He didn’t get to memory until the end of his presentation. He started off like many keynotes with some amazing statistics about growth in everything:

  • more video is uploaded to YouTube every month than the 3 major TV networks have ever produced in the 60 years of their existence
  • 80% of the world’s population has a mobile phone but only 1/3 are smartphones, lots of upside left in smartphones
  • 100M selfies are taken per day
  • phones are checked 100B times per day (Facebook 9B/day, WhatApp 50B/day, Twitter 500M/day, SnapChat 1.2B/day)
  • 91% mobile internet access is for social media
  • 3.6B photos uploaded in 2014 (whatsapp, facebook, instagram, snapchat and more)
  • 166M people have visited Yellowstone since it opened, 642M to Disneyland since 1955…but 807M people have watched the YouTube video “Charlie bit my finger again.”

OK, time to get a bit more serious. By 2018 3/4 of global data center traffic will come from cloud services and applications (Cisco data). The number in 2018: 8.6 Zettabytes (a Zettabyte is one trillion gigabytes) almost exactly double the 2014 number. Not surprisingly the datacenter is driving server growth but it also seems to be driving mobile growth too. Datacenter capex is $6B/quarter, driving down both compute and storage cost and allowing compute-expesnsive functionalty to be offloaded from mobiles (voice recognition, face recognition etc).


In turn this drives big data services. For example, preventative maintenance for a fleet of jets. Each engine generates 1TB of data per flight. With a non-optimized Hadoop (map-reduce) cluster what took 30 days now takes 20 minutes. And these are in high value segments: medical, power grids, energy, logistics, maintenance. Previously unsolvable problems are now in reach. No keynote would be complete without a mention of the Internet of Things (IoT) with the forecast of 50B smart objects connected by 2020. Everything will be connected to everything.

Well, since Jim is in charge of Samsung memory marketing you are not going to escape without hearing about Samsung memory. Memory is the core of the datacenter and every consumer device.


DDR4 is the 5th generation driving down memory power consumption. He didn’t talk about wide I/O but that is another significant technology in DRAM in my opinion.


NAND flash is continuing its exponential growth (smarphones, solid state disks, memory cards and more). But the technology is running out of steam. Density is not going up much, costs are going up a lot, as we move from process node to process node.


The breakthrough seems to be V-NAND (V is for Vertical) which enables both density and cost scaling, and even improves the bit-error-rate (BER). The performance is improved for both programming (write) and consumption (read) by a factor of 2.

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How Well is HSPICE Tracking Current Design Trends?

How Well is HSPICE Tracking Current Design Trends?
by Tom Simon on 02-11-2015 at 10:00 pm
Categories: EDA, Synopsys

For about 5 years now Synopsys has held an HSPICE SIG event in conjunction with DesignCon. It features a small vendor faire with companies that partner with Synopsys on HSPICE flows. They also have a dinner with industry/customer speakers and provide an update on HSPICE development. Lastly there is a Q&A where customers get to ask questions. I was able to attend this year’s event last week. Synopsys has posted a video of this interesting session here.

There were guest speakers from TSMC, Xilinx, and Micron. Raed Sabbah from Micron spoke about how he uses HSPICE to characterize SRAM bit cells. His talk covered a 6T bit cell bi-stable latch, which as he pointed out is vulnerable to process variation. In his analysis method he needs to run over 10 million simulations. He relies heavily on the Large Scale Monte Carlo feature of HSPICE to get his results. For this he uses distributed processing. He is able to check the write and read margins using transient analysis with split T and V.

Next up was Brandon Jiao from Xilinx who spoke about their 28G SerDes verification with channel models. They have created their own IBIS AMI 5.0 models to perform linear time invariant time domain simulations. The model support clock/data recovery and DFE. The models they created also account for impairments and non-idealities found in silicon. For the channel model they use an s-parameter model that has ports for coupled lines. They run this with the coupled lines grounded and then with TX/RX data.

PBRS is used to ensure that they get good coverage of states. The last challenge is to get past the ignore bits while the system stabilizes and then record the data bits of interest. They use HSPICE heavily in this entire process. In their design the pulse time is on the order of 35 picoseconds, and the response time is orders of magnitude longer at ~75nanoseconds. To get coverage of all the possible bit patterns the need to run 20e20 bits.

In the his talk Min-Chie Jeng of TSMC spoke about their partnership with Synopsys in developing the TSMC Model Interface (TMI). This is an API interface that offers advanced modeling capabilities that are out of reach of traditional models. Newer process nodes are offering relatively less process improvement, putting increased pressure on design margins. One area that is becoming problematic is layout dependent effects. Traditional SPICE models do not handle them well. This creates a gap in pre and post simulation results. One example of a source of this gap is the differences between fingers within a single device.

Another important use of TMI is in predicting aging effects. TMI can include an aging model based on self heating. This in turn is dependent on the specific waveform used in the simulation. In a comprehensive flow it is possible to identify the hottest device in a design which would consequently be the one that would suffer the greatest self heating induced degradation, and pose the greatest reliability risk.

In closing, Scott Wedge from Synopsys spoke about recent HSPICE development. He opined that they have been achieving roughly a 1.5X performance improvement with each release. This is significant because over a period of many successive releases this has accumulated to provide much better performance than in years gone by. Scott maintains that they have been very consistent in the themes of the prior releases: capacity, coverage, improved s-parameter support, multi-core and transient noise.

In the talks that preceded, and in his, there was a lot of focus on stat-eye support in HSPICE. This is clearly a significant feature that they just further enhanced with additional metrics.

The Q&A started off with a few easy questions. But inevitably the issue of s-parameter support came up. It seems that at an event like DesignCon, where board SI is a hot topic, s-parameter support is essential. The SI solvers now provide s-parameter models with hundreds of ports for present day boards and packages. S-parameters for on-chip devices are relatively easy to work with, but many members of the audience are facing hundreds of ports.

Scott was up front regarding the challenges, citing passivity and causality as issues in creating rational functions. Realistically there is no magic bullet. But Scott committed to work with customers as corner cases come up to ensure solutions.

All in all HSPICE has been the so-called gold standard for SPICE since its inception. It has fared well under Synopsys’ stewardship. HSPICE has been a crucial tool for electronics designers for many years. By Scott’s own admission he has been involved with HSPICE for over 25 years. Synopsys is still clearly tracking the trends that are driving the market.

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UVM Debugging Made Easy & Productive in Questa

UVM Debugging Made Easy & Productive in Questa
by Pawan Fangaria on 02-11-2015 at 2:00 pm
Categories: EDA

As design complexity and size is increasing, SoC verification has become one of the most difficult and time consuming tasks in the design closure.UVM (Universal Verification Methodology, an accellera initiative) is one of the best verification methodologies that support common language, coherent strategy, clarity and transparency and most importantly, provide easy-to-use APIs. Today, UVM is a very popular SoC verification methodology. Among various tasks associated with verification such as test planning, test bench preparation, test creation, test run, and debugging, most of the time is spent in debugging. UVM provides freedom to use its APIs in best possible ways in any user environment such that the verification and debugging can be optimized according to the environment.

Mentor’sQuesta Verification Platform has integrated UVM that provides a powerful and productive environment for debugging designs. The Questa_UVM package is just add-on SystemVerilog package which enables better UVM debug for Questa users. Any UVM kit is pre-compiled in Questa and does not require any kind of instrumentation. Although UVM source code is also provided along with Questa, it is recommended to use pre-compiled version for easy use of the built-in Questa UVM debug.

vsim –uvmcontrol=all
An ‘uvmcontrol’ switch with various options can be used with ‘vsim’ simulator command. It’s recommended to use ‘all’ option that includes all UVM-aware functionality and debug options except ‘disable’ and ‘verbose’. There are other options to control visibility into debugging by setting only desired blocks in the hierarchy to be visible and hence optimize the overall debug process. The visibility can be enabled selectively in the RTL as well.

Questa uses a specific nomenclature to define various class types and their unique instances. With SystemVerilog classes, Questa provides software-like debug views of class tree and class graph. It uses OOP (Object Oriented Programming) methodology for inheritance relationships. A class tree is shown in the above picture where classes, their extensions, methods, properties etc. can be seen in a hierarchical view.

Similarly all SystemVerilog classes can be seen graphically. Any particular class can be zoomed in to see methods and properties associated with it.

Any function call stack can be seen in a ‘call stack window’ to analyze the depth of function calls. Several commands are provided which can be executed directly from command line or from simulator command line. For example, ‘call’ can be used to call any UVM SV function; ‘findregisters, fr’ can be used to find HDL registers for a UVM register model; ‘findsequences, fs’ can be used to find currently active sequences; and so on. There is a very useful command called ‘find insource’ that searches through only compiled code to find the given matching string. The returned text is hyperlinked that can be clicked to go straight to the source code.

Questa has methods to aggregate data into a single entity for viewing in the ‘wave window’. These entities are called transaction streams (blue stars in the above picture). The transaction streams are created automatically in UVM. Questa system calls allow flexibility in defining these transaction streams. To record a transaction stream, begin_tr() and end_tr() functions are called in drivers and monitors which automatically call do_record(). The do_record() function has been added in Questa as part of UVM debug features.

The transactions can be viewed in detail and analyzed in the ‘wave window’. Any particular item can be clicked and seen in more detail in a pop-up window.

A detailed view of the advanced UVM debugging can be seen in an on-line webinarposted on Mentor website. Tom Fitzpatrick, Verification Evangelist at Mentor, has described strategies for debugging UVM-based test benches in Questa environment in great detail. He also demonstrated live debugging with an example test bench that shows the real power of the Questa Verification Platform along with UVM.

This is an excellent platform that enhances class-based SystemVerilog debugging for UVM. The performance is optimized while preserving visibility in debugging design blocks. The UVM methods can be called directly from command line that enhances verification engineer’s productivity.

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Using NoCs to Reduce Power

Using NoCs to Reduce Power
by Paul McLellan on 02-11-2015 at 7:00 am
Categories: IP, Sonics

Earlier this week I moderated a webinar at Sonics entitled NoC 102: Using SonicsGN to Address Low Power Requirements. Drew Wingard, the CTO of Sonics, presented it. It goes without saying that power is a major concern in SoC design, not just with chips for battery powered devices but also tethered devices. A major cost of ownership issue in datacenters is how much power the equipment takes and how much power the air-conditioning takes to get the heat out again.One particular challenge is that the number of power domains is increasing. These are either islands at different voltages for power reasons, or regions that can be powered down when idle (such as the transmit/receive blocks in your cell-phone when you are not making a call). Increasingly it is not feasible to keep all of a chip powered up at the same time, the challenge of dark silicon. If everything is on at once the chip will breach its thermal envelope.The clock can consumes as much as 30% of the power on a chip so reducing power in the clock itself, and associated with the clock is important. Synthesis will do some fine-grained clock gating for you, replacing muxes recirculating registers with clock-gates. But coarse grained clock gating further up the clock tree (at the block level for example) is even more important. NoC designs typically achieve 99.5% or even 99.9% gating, perhaps 16 free running registers out of 40,000.That leads us to Rule #1:The NoC must support both automatic coarse-grain and fine-grain clock gating which should be architected into the design, don’t just rely on synthesis
Next, power domains. Reducing the voltage reduces dynamic power (a lot, the voltage is squared in the power equation). Reducing it to zero also saves on leakage power which is a big issue in the planar processes that many designs are still done in. If domains that are powered up and down together can be grouped it can save a lot since there are typically fewer signals crossing the boundary compared to gating at the boundary of the blocks themselves.This leads us to rule #2:The NoC must allow “domain boundaries” within the network

  • Different clocks for different parts of the network
  • Different voltage supplies for different parts of the network
  • Portions of the network can be idled or even switched off


One of the challenges with powered-down blocks is putting them to sleep and waking them up. Historically this has often been done by software. But this has two problems: the software is hard to get right, and just to be running software requires the high-powered microprocessor to be running.If the NoC knows the power state of all the blocks it can handle a lot of this in hardware without the microprocessor needing to be powered up. Blocks that have been idle for a long time (no messages) can be powered down, and then when a message arrives it can be buffered while the block is woken up (it takes time to wake up a block since it can’t simply be turned on at full-power from one moment to the next due to inrush current which risks causing voltage droop all over the chip).So rule #3 is: The NoC must be aware of the power state of network components

    [*=1]Allows network interfaces to tell power manager when it is safe to switch off a block
    [*=1]Catch traffic early that accesses powered down parts of the SoC

And rule #4 is:Integrate auto-wake-up features into Network

    [*=1]Network requests wake-up of necessary power domains, without software assistance

You can watch a replay of the webinar here.

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TSMC vs Samsung!

TSMC vs Samsung!
by Daniel Nenni on 02-10-2015 at 9:30 pm
Categories: Foundries, TSMC

One of the trending topics in Taiwan last week is the escalating conflict between Samsung and TSMC. This time however it is of a legal nature which has been a long time coming for the semiconductor industry. Reverse engineering has been an integral part of the semiconductor business since the beginning, as has intellectual property theft. The difference being employees with prior knowledge are doing the reverse engineering and the resulting email trails are their undoing every time.

The driving force behind this of course is the demand for second source foundry manufacturing. As I have mentioned before, at 40nm and above TSMC design databases (GDS II) were given to UMC, Chartered, and SMIC for second, third, and sometimes fourth source production. At 28nm and 20nm it is much more difficult to do and at 14/16nm and 10nm it will require a copy exact strategy or a significant redesign. In fact, at 10nm you will not even be able to use the same design team for different foundries due to strict legal constraints.

Take a look at this blog about the legal action TSMC took against SMIC at 180nm and 130nm. It is an interesting story, one that will certainly have some commonality with the Samsung legal action:

TSMC versus SMIC
byDaniel Nenni
Published on 09-28-2009

The recent events surrounding the TSMC vs Sasmung legal action are detailed in this article. Please note that I have not fully fact checked this yet but will do so in the coming weeks. You should also know that this is a Taiwanese publication known for “Solid, sober reporting, CommonWealth magazine gives Taiwan’s entrepreneurs and decision-makers the insights they need to keep ahead…”

Hunting Down a Turncoat
By Liang-Rong Chen
Published: January 23, 2015

It really is a sordid story if you have the time and interest. The bottom line, as with the SMIC case, is that it alleges Samsung hastened the delivery of 14nm by using technology that they obtained from a former TSMC executive. Right now the legal action is against the former employee but that may change when the Samsung 14nm silicon is fully investigated.

“The 16nm and 14nm FinFet products that both companies will mass produce this year were even more alike. It could be hard to tell (if the product) came from Samsung or TSMC if only structural analysis is used, the report said.”

One of my former employers had a similar experience when a consultant “borrowed” code from a competitor to hasten a product delivery. The result was hundreds of millions of dollars in damages, jail time, and a forced acquisition. At one time I remember customers using the software in question were also under legal threat but fortunately cooler heads prevailed. It really is a bad idea to take legal action against customers.

The FinFET technology at the heart of today’s fierce battle between TSMC and Samsung was also one of Liang’s strengths. In its claim against Liang, TSMC stressed: “Liang Mong-song was deeply involved in TSMC’s FinFET process research, and he was the inventor behind related patents.”

According to Patent Buddy, 47 patents were filed and 15 issued between June 2001 and July 2012:

Mong-Song Liang Inventor – TSMC Patent Owner

I would be interested to know which of these patents are FinFET related if someone out there has the time, expertise, and interest to investigate. Hopefully the result of this blog will be a lively conversation in the comments section, just remember that this is but one side of a very complicated story.

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Sony Endorse FD-SOI to Attack Wearable & IoT

Sony Endorse FD-SOI to Attack Wearable & IoT
by Eric Esteve on 02-10-2015 at 12:04 pm
Categories: FD-SOI, Foundries, STMicroelectronics

We are writing about FD-SOI technology since the beginning of 2013 in Semiwiki. So far, most of the design experience was related to ST-Microelectronics (even if IBM and GlobalFoundries have been actively working on the technology, probably more on a research mode than pure production). Sony being actively working to develop consumer products on FD-SOI technology (since 2012) is a real indicator about FD-SOI momentum in the SC industry. The paper presented at the SOI forum in Tokyo last month is here.

Sony is playing in the consumer electronic (CE) segment, probably the most crowded after the mobile. An OEM can play different strategies to win in the CE segment, for example developing “me-too” products, cheapest than the original, but with no differentiators. That’s not the way Sony is playing! Sony is an OEM (developing IC internally when it make sense) being recognized as one of the most innovative in the industry, and Sony’s winning strategy is to launch highly differentiated new products. When talking about wearable and IoT, ultra-low power is certainly one of the most important differentiator. If you analyze this well-known formula:

Power = af C V[SUP]2[/SUP][SUB]dd[/SUB] + I[SUB]leak[/SUB] V[SUB]dd[/SUB]

You understand why Sony has heavily invested into FD-SOI to develop IC targeting wearable and IoT. Designing with FD-SOI allow minimizing the two components of power consumption:

  • Running the device at a much lower Vdd (0.6V instead of 1.1V) than Bulk CMOS dramatically divides the active power consumption (in V[SUP]2[/SUP][SUB]dd)[/SUB]
  • Because FD-SOI active device is by nature built on Insulator, the leakage current is lower, so the related power consumption (I[SUB]leak[/SUB] V[SUB]dd)[/SUB]

I realize that we have mostly write about high complexity (and high performance) logic IC designed in FD-SOI, like Application Processor or IC supporting communication infrastructure. But SOI in general and FD-SOI can be extremely effective for RF design as well: on the above picture Low power RF device exhibits:

  • Very high Intrinsic Gain for FD-SOI 28nm, compared to Bulk 28 or 40nm
  • Comparable noise

Sony has developed an analog chip in 28nm FD-SOI to explore the possibility to design an extremely low power GPS, opening the door for wearable GPS devices. It’s very exciting to see that FD-SOI analog behavior is very promising, like the pure logic behavior. If you look at Sony presentation here you realize that the assessment process has been extremely stringent: the design team has optimized the libraries, designing various gate length options, verified the minimum Vdd to run SRAM, on top of the analog specific simulation and measurement above described. Designing IC for GPS localization, as I have learned a couple of years ago when consulting for an ASIC customer, requires the availability of: High performance analog front end, relatively large on-chip SRAM, very sophisticated algorithm (the real Intellectual Property in fact)… and obviously the right embedded CPU to run these algorithms.

Sony has demonstrated in this presentation that FD-SOI was a very good choice to support such GPS application (thanks to the availability of high performance ARM CPU core, already demonstrated by ST-Microelectronics on the technology), offering even better analog performances than an equivalent Bulk node. But the true killer is the ultra-low power consumption demonstrated on FD-SOI, allowing developing consumer application, wearable or IoT, with a strong competitive advantage. If the effective power budget is 1/10[SUP]th[/SUP] of the equivalent on Bulk, this means that the “thing” you are wearing will need to be charged a couple of time a month instead of every day. This can make the difference for the end user: are you ready to buy another system that you have to charge every day, on top of your smartphone, your smart-watch, etc…?

Sony sharing about their design experiences with FD-SOI is almost a symbol: FD-SOI penetration in consumer application has started!

Next “rendez vous”: SOI Forum in San Francisco on February 27[SUP]th[/SUP], to register: RF-SOI and FD-SOI Forum San Francisco

From Eric Esteve from IPNEST

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Chips Are Going 3D, DRC Needs to Go 3D Too

Chips Are Going 3D, DRC Needs to Go 3D Too
by Paul McLellan on 02-10-2015 at 7:00 am
Categories: Coventor, EDA

The last paradigm shift in DRC was around 0.35um when designs got too large to handle as flat data, and hierarchical approaches were required. Back then the design rules themselves were not that complex, the explosion of data volume came from the complexity of the design itself. But each process node added more design rules intricacies and many new types of rules that needed to be checked.


Until recently, design rule complexity has been increasing around 20% per node (plus the designs continue to get bigger, of course). Now, advanced technology node complexity has exploded either due to FinFETs (for SoCs) or 3D NAND flash and much deeper trenches for DRAM (for memories). The world has gone 3-dimensional, and it’s getting very difficult to use inherently 2D checking methodologies to find 3D design problems. Often a single 3D “problem”, when abstracted to 2D DRC syntax, can drive thousands of individual design rules and entire chapters in a design manual. Since design rules have to account for small but inevitable variations in the manufacturing process, the development of these rules needs to understand the complex relationship of structure to process and design in 3D. For example, it is extremely difficult by examining the mask designs to verify that the fin height of the FinFET produced by those masks is within tolerance…or that this fin height variation won’t cause gate shorts to nearby devices. In effect, there has to be a very indirect and inefficient model of the manufacturing process hidden away in the rules and the DRC algorithms.

Coventor has a product, SEMulator3D that is inherently three dimensional. SEMulator3D is a virtual fabrication platform that many foundries and memory companies use to speed advanced semiconductor processes to market. Relying exclusively on test wafer manufacturing is too expensive and too slow for the continued fast pace and competition for advanced semiconductor products. When SEMulator3D is used for process development it reads in layout and a description of the process recipe and produces a full predictive model of what is going to end up on the wafer. The underlying technology uses voxels (the volume equivalent of a pixel). This is just the foundation required to make a much more direct, accurate and efficient interrogation of the 3D structures on the chip.

Virtual fabrication can be used to augment the conventional DRC approach, which is well suited for some things, with a 3D approach that creates an accurate and predictive view of what those masks create on the wafer. New capabilities in SEMulator3D allow three dimensional rules to be applied to virtually fabricated models. For example, technology developers can build up a complete 3D FinFET based on the masks and then measure critical aspects such as the fin height, spacer thickness and gate isolation much more directly.

Coventor has been actively developing the SEMulator3D technology to apply these 3D design rules to advanced technologies and product designs. It has just been granted a patent in this area and is now expanding its relationship with customers and partners to advance this 3D checking technology to augment the current DRC programs. Of course, it will take time for this 3D checking technology to mature and be ready for production-level sign-off. However, it is already showing great promise. This promises to be the next paradigm shift in DRC technology and should considerably improve the creation and application of design rules in advanced 3D technologies.

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Open Forum for Semiconductor Professionals!

Open Forum for Semiconductor Professionals!
by Daniel Nenni on 02-09-2015 at 8:00 pm
Categories: EDA, Foundries, IP, Semiconductor Services

The semiconductor industry has never been more exciting than it is today, at least not in my 30 years of experience. Things are moving faster than ever before making collaboration at all levels a requirement. At SemiWiki we are afforded the privilege of passes to semiconductor conferences around the world. We also have access to all levels of the fabless semiconductor ecosystem and speak with people both on the record and off. Even so, some of the best information comes from forum discussions, absolutely.

When we first started SemiWiki it was really meant to be a forum with wikis and a place for my weekly Silicon Valley Blog. Fortunately industry experts Paul McLellan and Daniel Payne agreed to move their blogs from EDN to SemiWiki and the rest is history. We now have eight industry experts on staff and dozens of others who blog when they have something of semiconductor interest to say.

The forums however are a different form of communication and a very important one. As you can see we have expanded our forum section to include additional subject areas:

Semiconductor Process Technology
TSMC, Intel, Samsung, GF, UMC, SMIC, 28nm, 20nm, 16nm, 20nm, 10nm, etc…

Electronic Design Automation (EDA) Software
Cadence, Synopsys, Mentor, Ansys, Atrenta SpyGlass,, Calypto, Carbon Design, ClioSoft, Coventor, Dassault, Fractal Technologies, Methodics, MunEDA, Silvaco, Tanner EDA, Etc…

Discussions on the latest SoCs and related technologies
CPU, GPU, LTE, 4G, etc…

Semiconductor IP Market Place Threads
A place to share your IP! DSP, PCIe, USB, DDR, MIPI, HDMI, NoC, etc…

Programmable Devices
Discussions on FPGA, PLD, and CPLD technology, design, and implementation, Xilinx , Altera, Lattice, and Cypress.

Microcontrollers
Discussions on embedded technology, design, and implementation
ARM, Analog Devices, Atmel, Freescale, Infineon, Intel, Maxim, Microchip, NXP, Renesas, Silicon Labs, STMicro, TI, Zilog

Mobile Devices
Discussions and product reviews for smartphones and wearables. Post a review of your favorite mobile gadget and lets crowdsource!

Internet of Things (IoT)
Discussions on IoT and Security. SemiWiki is staffed with IoT experts so this is the place to ask questions, absolutely!

Digital Fabrication: 3D Printing, CNC Milling, Laser cutting, etc…
Discussions and meet-ups on the latest technologies for digital prototyping.

Semiconductor Related Stocks
Where investors and semiconductor professionals interact. Please put stock ticker in subject of all posts: INTC, TSM, QCOM, ARMH, ALTR, XLNX, SNPS, CDNS, MNTR, Etc…

Semiconductor Related Jobs Forum
This is an open forum for recruiters and job seekers. Post jobs here for free! For the greater good of the semiconductor industry!

Each forum will have moderators so if you see one you are passionate about and would like to be actively involved let me know. There is fame but no fortune unless you consider the knowledge and relationships you will gain which is truly priceless. You will have direct connections to hundreds if not thousands of semiconductor professionals in your area of interest. Just imagine the possibilities!

As I mentioned in my blog “EDA Tool Reviews” we want honest and unfiltered opinions, observations, and experiences with tools and technology for the greater good of the fabless semiconductor ecosystem. The same goes for the other forums. Start discussions, ask questions, share your semiconductor design successes and failures so we all can all learn from them. Be an active part of the crowd that changed the world because our work is not done.

It is easy to get started, just register for SemiWiki (use your real name or not) and pick the forums that interest you. While you are in the forum just click on the Forum Tools tab and subscribe so you get notified whenever there is a new post. Or you can subscribe to the RSS feed, simple as that.