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Semiconductor CAPEX Growth Increases Fab Equipment Spending!

Semiconductor CAPEX Growth Increases Fab Equipment Spending!
by Daniel Nenni on 04-01-2015 at 8:00 am

SEMI Forecasts 15% Increase in Fab Equipment Spending for 2015

With worldwide capex growth of 8%, fab equipment spending is expected to increase by 15% in 2015, according to the most recent edition of the SEMI (www.semi.org) World Fab Forecast. SEMI’s data also predicts a slowdown of fab equipment spending in 2016 to low single digits (2-4%). Looking back to the last 25 years, after two years of growth a negative year typically followed. This may not be the case this time as developments in the industry are pointing to a small but positive 2016.

Most fab equipment spending in 2015 is expected for Foundry followed by Memory. The share in 2015 for both is the same with each about 40%, and the share for Logic and MPU is expected at about 11%. Looking into 2016, the share for foundry is expected to increase to almost 44% followed by Memory with about 38% and Logic/MPU with 13%.

Since its last publication in November 2014, about 270 updates were made to the SEMI report, including data on 17 new facilities. The report tracks fab spending for construction and equipment, as well as capacity changes, and technology nodes transitions and product type changes by fab.

Fab Equipment/Fab Construction (2013-2016)

[TABLE] align=”center” border=”1″
|-
| style=”width: 173px; height: 29px” |
| style=”width: 72px; height: 29px” | 2013
| style=”width: 72px; height: 29px” | 2014
| style=”width: 72px; height: 29px” | 2015
| style=”width: 93px; height: 29px” | 2016
|-
| style=”width: 173px; height: 19px” | Fab equipment*
| style=”width: 72px; height: 19px” | $29
| style=”width: 72px; height: 19px” | $35
| style=”width: 72px; height: 19px” | $40
| style=”width: 93px; height: 19px” | $41 to $42
|-
| style=”width: 173px; height: 29px” | Change % Fab equipment
| style=”width: 72px; height: 29px” | -10%
| style=”width: 72px; height: 29px” | +19%
| style=”width: 72px; height: 29px” | +15%
| style=”width: 93px; height: 29px” | +2% to 4%
|-
| style=”width: 173px; height: 28px” | Fab construction US$
| style=”width: 72px; height: 28px” | $9
| style=”width: 72px; height: 28px” | $8
| style=”width: 72px; height: 28px” | $5
| style=”width: 93px; height: 28px” | $7
|-
| style=”width: 173px; height: 28px” | Change % construction
| style=”width: 72px; height: 28px” | +14%
| style=”width: 72px; height: 28px” | -11%
| style=”width: 72px; height: 28px” | -31%
| style=”width: 93px; height: 28px” | +31%
|-

*Chart US$, in billions; Source: SEMI, March 2015

According to the SEMI forecast, the highest fab equipment spending in 2015 will occur in:

  • Taiwan (US$ 11.9 billion, 40% increase over 2014)
  • Korea ($8.7 billion, a 19% increase)
  • Americas ($6.7 billion, a 12% decline)
  • China ($4.8 billion, a 17% increase)
  • Japan ($4.2 billion, a 10% increase)
  • Europe/Mideast region ($2.7 billion, a 16% increase)
  • South East Asia ($1.3 billion, a 15% increase)

Total capital expenditure (CAPEX) for most of the large semiconductor companies is expected to increase by 8% in 2015, and grow another 3% in 2016. These increases are driven by new fab construction projects and also ramp of new technology nodes. Fab spending, such as construction spending and equipment spending, are fractions of a company’s CAPEX. Typically, if CAPEX shows a trend to increase, fab spending follows. Spending on construction projects, which typically represents new cleanroom projects, will see a significant (-31%) decline in 2015, but is expected to rebound by 31% in 2016.

New facilities beginning construction in 2015 and 2016 will start equipping in 2016 or later. SEMI’s data show that eight facilities with various probabilities may start construction in 2015 (including one LED. In 2016, construction will possibly begin on five or eight new fabs.

The SEMI positive outlook for the year is based on spending trends tracked as part of our fab investment research. For the World Fab Watch, SEMI uses a “bottom’s up” company-by-company and fab-by-fab approach which points to strong investments by foundries and memory companies, driving this year’s growth. Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase.


What is Skipper?

What is Skipper?
by Paul McLellan on 04-01-2015 at 1:00 am

What is Skipper? Well, it seems it’s a penguin in the movie Madagascar. And one of Barbie’s sisters. Who knew? But for Semiwiki readers it’s an integrated chip finishing platform from ICScape. Skipper can read in full-chip layout extremely fast, examine it and manipulate it in various ways, and write it out again.

Skipper solves a number of different problems, both before tapeout and when debugging silicon exhibiting problems:

  • True chip finishing, taking the output from the primary design system and producing the file for sending to the mask shop for fabrication
  • Debugging a chip when it fails test in a non-obvious way or when a chip fails and the cause needs to be determined
  • Interfacing to focused ion beam (FIB) systems for microsurgery and deeper analysis of the chip using the real silicon
    Much of the challenge in handling designs at this stage is their sheer size. For Skipper to have good interactive response then it needs to have the most efficient data structures. After all, even a moderate-sized chip has billions of polygons these days, and if the design is being handled after reticle enhancement (RET) and addition of artifacts like dummy metal fill then the polygon count explodes. Skipper has been optimized for handling designs at the full-chip level in order that it can read, manipulate and write back huge GDS files.In its chip finishing mode, Skipper can:

    • handle very large layouts (100GB+ files in GDS, Oasis, MEBES etc) with fast load and refresh
    • merge in standard cells and IP blocks to replace footprints, switch cells, add seal rings
    • make detailed layout changes down to the polygon level
    • debug DRC and LVS errors at the full-chip level including setting waivers, eliminating duplicate errors and generating DRC reports
    • compare layout between any two full-chip representations including checking individual layers of mask representation versus the original layout (e.g. MEBES vs GDS). This is done using multi-core operating for highest performance


    For debugging chips and analyzing failures, Skipper has a number of additional features:

    • despite not requiring a full technology file or a PDK, it can still trace nets, even the largest nets such as power, ground and clock nets
    • failure analysis engineers can pump simulated current into pins of a failed chip to narrow down where a fault may be occurring so as to assist in locating faults to a given area, small enough to be examined in details with scanning electron microscope (SEM)
    • cut out an area of the chip across the whole hierarchy for detailed examination

  • FIB allows chips to be altered using nano-machining with beams of Gallium ions. Some FIB machines also allow the design to be inspected without requiring a separate SEM pass. One problem is communicating what cuts to make since the FIB machines do not operate directly from mask data. Skipper can create layout/edit directives for use on the FIB machine to ensure accuracy and reduce turn-round times.Skipper is the highest performance chip-finishing environment available today. It is regularly used today on some of the most demanding designs such as large memories at leading memory manufacturers, or large SoCs at leading communications companies.

    ICScape’s website page on Skipper is here.


Secret Sauce for Successful Mixed-signal SoCs

Secret Sauce for Successful Mixed-signal SoCs
by admin on 03-31-2015 at 12:00 pm

For a design engineer engulfed in the daily rigorous routine of having to keep in sync with updates from various design team members as well the dictums of the design management team, the task of remaining up-to-date with the design information is very often daunting.

What design changes have been checked in this week? Is the verification team using the correct behavioral model of the analog IP? Is the layout for this design DRC/LVS clean? Looks like the schematic had some ECOs! What changed? Which rev. of the schematic was the layout created for? Is the physical implementation team using the latest pinout of the analog block? Did all teams use version X.X of the USB 3.0 IP?

Sound familiar? These are usually the questions that chip designers are plagued with these days in an increasingly complex and multi-site design environment. Most designers would prefer to focus on the design implementation — such as creating the design or perhaps managing the challenges of scalability and performance of analog/mixed-signal blocks at advanced process nodes — instead of dealing with the increased demands of system-on-chip (SoC) integration and working with various design teams (front-end digital, verification, physical integration, etc.). With design teams located either locally or at different locations across the globe, it becomes imperative for all teams to work in tandem to ensure smooth design handoffs at various stages of the design flow.

To ensure a cohesive work environment for designers, one which enables them to focus primarily on the design creation and implementation, while subtly handling the mundane aspects of managing the sanctity of huge amounts of design data, it becomes important to use a design data management system. Most mixed-signal design modules are co-designed, with design teams working closely and interfacing with each other, and keeping the different design views synchronized often represents a challenge. If the behavioral model, block abstract, layout, timing or power model is not synchronized, it can prolong the turnaround time or, in the worst-case scenario, force a silicon re-spin. Moreover, analog/digital integration at advanced process nodes requires close collaboration between the various teams.

Design teams ignore investing in a design management system at their own peril. To realize a successful mixed-signal tapeout, it has become important to invest in a design management platform that covers all types of designs – analog, digital, RF and mixed-signal – and one that is closely integrated with design tools from various EDA vendors. While some teams have invested in software-based data management systems, with additional layers built on top to adapt to mixed-signal designs, the reality is that they neither meet the rigorous demands of complex mixed-signal design flows nor provide optimal performance. The result is that the designer often has to spend considerable time manually managing the tool and the design data.


Figure-1: Stability of a mixed-design flow with and without a design management platform

The power and size of mixed-signal SoCs are quickly expanding to new levels of integration in order to accommodate highly demanding features in consumer, automotive, industrial, medical and bio-tech applications. This has led to new revolutions in various fields, such as bio-tech. Take the case of DNA sequencing using mixed-signal SoCs as an example. Genia Technologies, acquired by Roche Molecular Systems in June 2014, recently provided a detailed view of its SoC device for DNA sequencing at CDN LIVE in Silicon Valley. The life sciences chipmaker is developing a faster and more cost-effective way of sequencing DNA chains.

For a bio-tech novice like me, who has no clue about the ramifications of having a fast and an affordable means of DNA sequencing, this was quite an eye opener. DNA sequencing provides the ability to assess individuals’ genetic profiles over their lifetime. What this implies is that hospitals and medical clinics can monitor or screen for future diseases efficiently and cost-effectively to provide personalized health care. Since the variation in genes can make people respond differently to the same drugs, doctors now have a means to decide which drugs to prescribe.

The traditional methods of DNA sequencing have been very expensive and time consuming. Genia Technologies is aiming to create a device that can reduce the cost of the sequencing to a few hundred dollars as opposed to a few thousands today. Their SoC-based solution bypasses specialized, expensive optical sensors and instead uses mixed-signal semiconductor chip with a number of sensors. Genia Technologies is aiming to make the chips as inexpensive as the ones found in mobile phones, tablets and other consumer electronic products.

Genia’s NanoTag sequencing technique, developed in collaboration with Columbia University and Harvard University, uses a single DNA strand, which is then processed using tiny bioengineered nanopores. The chip reads the DNA sequence electronically with the help of a number of sensors. According to Hui Tian, vice president of Genia Technologies, electronic reading of single DNA strands requires less “informatics horsepower” to reconstruct a sequence accurately. Each sensor generates kilobytes of data per base and each bio-machine runs at a few bases per second. Each human genome sequencing requires nearly 180GB of data. What was equally interesting is that for the SoC to work as desired, once the SoC was taped out, it was sent to another foundry to form mini-wells and biocompatible electrodes on top of the wafer.


Figure-2: Genia’s technology – Nanopore sequencing

Genia claims that its SoC-based solution, developed at the cross-section of NanoTags and CMOS IC technology, brings the crucial advantage of single molecule capability coupled with semiconductor scalability. But how does Genia Technologies manage the complexity of building such a powerful and complex SoC device?

Genia’s Tian says that his company uses the SOS data and IP management system from ClioSoft Inc., which is tightly integrated with Cadence Virtuoso® technology to ensure collaboration and better design handoff between different design teams. Tian further elaborated on the design flow adopted to develop the analog part of Genia’s SoC design using Cadence design tools and ClioSoft’s SOS design data management to create a platform for sequencing single DNA molecules.

As teams continue to grow across multiple sites and regions, it is becoming necessary to have a collaborative solution for engineers and managers to manage design data, track project activities and deliver IP products in a timely, secure and efficient manner. This avoids design and tapeout delays in their SoC projects. While design data management is not a magic elixir that resolves all SoC delays, it mitigates the risk significantly and provides a path for greater designer productivity and design flow efficiency.

Also Read: Data Management: Bridging Digital and Analog Domains in RF Designs

Ranjit Adhikary is director of marketing at ClioSoft Inc. He has over twenty years of experience and has worked in companies such as Cadence Designs Systems, Magma Designs and Atrenta.

Also Read

DNA Sequencing Eyes SoCs for Stability and Scale

Make Semiconductor IP Reuse Successful?

Design Collaboration across Multiple Sites


Linley Mobile Microprocessor Conference

Linley Mobile Microprocessor Conference
by Paul McLellan on 03-31-2015 at 7:00 am

As The Who sang on Who’s Next:Keep me movin’, groovin’, groovin’, yeah
Movin’, Yeah
Mobile, mobile, mobile, mobile, …

On April 22nd and 23rd the place to be moving (or movin’) to will be the Hyatt Regency in Santa Clara. Because What’s Next is this year’s Linley Mobile Conference. The conference basically focuses on processors for mobile handsets with a sprinkling of IoT (mobile base-stations are covered in the Linley Datacenter Conference which you missed in February or the Linley Carrier Conference on June 10th).

This year the organizer is Mike Demler who I worked with at Cadence, then he took up the noble profession of blogging, but has been a senior analyst at Linley Group for a couple of years now. The program will include technical presentations and panel discussions addressing a broad range of topics. The precise agenda is still has not been finalized but I am assuming it will follow the usual format which consists of a few presentations on a particular topic, followed by a panel session with all the presenters.

One change from previous years is that you will not receive a printed copy of the proceedings when you check in at registration. They will be available for download during the conference however, assuming you brought a (mobile!) device.

Here are some of the presenters already committed:

  • The keynote on the first day will be Linley Gwennap’s Mobile Market Overview. This is an overview of the market, technologies, equipment-design, and silicon trends for designers of mobile devices.
  • Morten Christianson of Synopsys will talk about Designing mobile SoCs with USB Type-C connectors. Synopsys has recently produced a complete suite of IP for this connector. I can’t wait for it to be widespread since the plug can be inserted either way up (the original USB connector seems to be the only connector that takes 4 attempts to get it inserted despite only having two orientations).
  • Synopsys again with Hezi Saar on Cost-Effective Implementation for High-Resolution Display Mobile Devices
  • And you can’t keep them away, no wonder they are a premier sponsor: Synopsys’s Yankin Tanurhan on Embedding Vision in Mobile SoCs.
  • On the same topic, Yair Segal of CEVA on Enabling Intelligent Vision Processing in EmbeddedSystems.
  • And keeping with vision, Jeff Bier of the Embedded Vision Alliance on Computer Vision in Mobile Devices: Progress and Challenges.
  • Cadence’s gets a turn with Chris Rowen of Tensilica fame on Always Alert: New Processors for Low-Energy Wireless Sensor Nodes.
  • Tim Saxe of Quicklogic, will talk about Partitioning Between Software and Hardware is Key to Ultra-Low Power. More always-on I suspect.
  • Steve Singer of Inside Secure on Embedding Robust Platform Security into Application Processors and IoT SoCs. Security is clearly truly “a thing” in mobile and especially IoT and destined to be a huge differentiator, I believe
  • Charlie Janac, the CEO of Arteris, will talk about using FlexNoC Physical to accelerate timing closure.
  • Staying with the NoC theme, Joe Rowlands of NetSpeed will present The Next Challenge in SoC Design: Customizable Cache Coherency.
  • Roy Ju of Mediatek will talk about Heterogeneous Computing for Smart and Energy-Efficient Mobile Applications. I’m still waiting to see an energy-inefficient mobile application.
  • Brian Jeff of ARM on all things ARM Cortex-A72. This is the new 64-bit core that they announced earlier this year, for the time being at least positioned for mobile.


Breakfast and lunch are provided both days (and the food is always excellent), and there is an evening reception the first (Wednesday) evening. With prizes.

The conference is free if you are a designer of mobile chips, mobile devices, or mobile software or a service provider, member of the press (me, yea!) or the financial community.

More details, including a link for registration, are here.


Verifying the RTL Coming out of a High-Level Synthesis Tool

Verifying the RTL Coming out of a High-Level Synthesis Tool
by Daniel Payne on 03-30-2015 at 9:30 pm

With High-Level Synthesis (HLS) the first benefit that comes to my mind is reduced design time, because coding with C or SystemC is more efficient than low-level RTL code. What I’ve just learned is that there’s another benefit, a reduction in the amount of functional simulation required. One HLS customer was able to see this reduction by comparing regression tests that took 1,000 servers running for 3 months using an RTL verification methodology, while using an HLS verification approach the same regressions completed on 12 servers in just 1 week, now that’s a huge difference.

A verification engineer can write tests that give 100% functional and structural coverage on synthesizable SystemC or C++, but when you run these same tests on the generated RTL the functional coverage is still 100% while the structural coverage will lower to about only 80%. This coverage difference is understandable because the HLS tool is automatically creating RTL that is:

  • Adding states to an Finite State Machine (FSM)
  • Adding Stall states
  • Adding Pipeline ramp-up and ramp-down states
  • Using one-hot encoded logic
  • Structuring logic that can lower reported coverage

Thankfully for us, the engineers at Calyptohave figured out a methodology to produce verification optimized RTL code. At DVCon this month they presented a paper, and then made that into a White Paper titled, “Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis“.

Related – Shorten the Learning Curve for High Level Synthesis

The verification flow for testing RTL generated by HLS is shown below in three iterative loops:

In stage 1 you are running directed and constrained random tests so that the C coverage tool shows 100% function, line branch and condition coverage. After stage 1 you run HLS and generate the RTL code, so in stage 2 the RTL code is ready for functional verification. At the end of stage 2 you have to add reset and stall tests. Stage 3 is where RTL structural verification takes place.

Stall and Reset Coverage

During HLS additional states are added, so we need to identify and target tests at these states to improve our stall coverage numbers. In the Catapult HLS tool a small state machine is added per IO cell, and this state is added into a “staller” block which disables flip-flops and the FSM in its thread. You target tests at each IO separately to reach the 100% structural coverage goal.

Related – HLS: Major Improvement through Generations

For reset coverage your tests will place the FSM into every state and then assert reset.

Unreachable Code

It’s likely that a low structural coverage number is being caused by unreachable code, so you can use a formal tool to run an unreachability check. Mentor has a formal tool called Questa CoverCheck and it typically proves that about 50% of uncovered lines are not reachable.

This formal approach still means that the remaining lines have to be manually analyzed by tracing the logic back to prove that it has unreachable conditions. Redundancies in the source code cause these unreachable conditions and they can be traced back to:

  • Writing loops
  • Conditional statements
  • A condition inside of a loop

Example Results

An example design was selected that has a Discrete Cosine Transform (DCT) used in the decoder for a High Efficiency Video Codec (HEVC). This design used just 490 lines of C++ code, and a functional and structural coverage of 100% was achieved.

Related – HLS Tools Coming into Limelight!

The Catapult tool synthesized the C++ code into 15,735 lines of Verilog. Applying the C++ stimulus to the RTL showed about 94% coverage (279 holes). The library components from Catapult are excluded from the coverage data by using a “gray box”, leaving only 153 holes. CoverCheck was run to find unreachable coverage bins, reducing our coverage holes to just 107, about 98% coverage.

Stall and reset testing was next, leaving us with just 25 coverage holes, at 99.5% coverage.

In the end, the last 25 coverage holes were manually waived.

Summary

HLS is an established methodology for modern SoC design, and the challenge of getting high functional and structural coverage at the RTL level is now possible by following a set of high-level modeling coding guidelines. Formal tools are used in this new methodology to identify unreachable lines. The approach presented has the potential to save from weeks to months from your next SoC schedule, something worth checking out.

Read the complete 10 page White Paper here.


Atmel’s L21 MCU for IoT Tops Low Power Benchmark

Atmel’s L21 MCU for IoT Tops Low Power Benchmark
by Majeed Ahmad on 03-30-2015 at 7:30 am

The Internet of Things (IoT) juggernaut has unleashed a flurry of low-power microcontrollers, and in that array of energy-efficient MCUs, one product has earned the crown jewel of being the lowest-power Cortex M-based solution with power consumption down to 35µA/MHz in active mode and 200nA in sleep mode.

How do we know if Atmel Corp.‘s SAM L21 microcontroller can actually claim the leadership in ultra-low-power processing movement? The answer lies in the EEMBC ULPBench power benchmark that was introduced last year. It ensures a level playing field in executing the benchmark by having the MCU perform 20,000 clock cycles of active work once a second and sleep the remainder of the second.


ULPBench shows SAM L21 is lower power than any of its competitor’s M0+ class chips

Atmel has just released the ultra-low-power SAM L21 microcontroller it demonstrated at the electronica in Munich, Germany in November 2014. Architectural innovations in the SAM L21 MCU family enable low-power peripherals—including timers, serial communications and capacitive touch sensing—to remain powered and running while the rest of the system is in a reduced power mode. That further reduces power consumption for always-on applications such as fire alarms, healthcare, medical and connected wearables.

Next, the 32-bit ARM-based MCU portfolio combines ultra-low-power with Flash and SRAM that are large enough to run both the application and wireless stacks. Collectively, these three features make up the basic recipe for battery-powered mobile and IoT devices for extending their battery life from years to decades. Moreover, they reduce the number of times batteries need to be changed in a plethora of IoT applications.

Low Power Leap of Faith

Atmel’s SAM L21 microcontrollers have achieved a staggering 185.8 ULPBench score, which is way ahead of runner-up TI’s SimpleLink C26xx microcontroller family that scored 143.6. The SAM L21 microcontrollers consume less than 940nA with full 40kB SRAM retention, real-time clock and calendar, and 200nA in the deepest sleep mode. According to Atmel spokesperson, it comes down to one-third the power of competing solutions.

Markus Levy, President and Founder of EEMBC, credits Atmel’s low-power feat to its proprietary picoPower technology and the company’s low-power expertise in utilizing DC-DC conversion for voltage monitoring. Atmel’s picoPower technology employs flexible clocking options and short wake-up time with multiple wake-up sources from even the deepest sleep modes.


ULPBench aims to provide developers with a reliable methodology to test MCUs

In other words, Atmel has taken the low-power game beyond architectural improvements to the CPU while optimizing nearly every peripheral to operate in standalone mode and then use a minimum number of transistors to complete the given task. Most lower-power ARM chips simply disable the clock to various parts of the device. The SAM L21 microcontroller, on the other hand, turns off power to those chip parts; hence, there is no leakage current in thousands of transistors in that part.

Here is a brief highlight of Atmel’s low-power development efforts that now encompass almost every peripheral in an MCU device:

Sleep Modes
Sleep modes not only gate away the clock signal to stop switching consumption, but also remove the power from sub-domains to fully eliminate leakage. Atmel also employs SRAM back-biasing to reduce leakage in sleep modes.

Consider a simple application where the temperature in a room is monitored using a temperature sensor with the analog-to-digital converter (ADC). In order to reduce the power consumption, the CPU would be put to sleep and wake up periodically on interrupts from a real-time counter (RTC). The measured sensor data is checked against a predefined threshold to decide on further action. If the data does not exceed the threshold, the CPU will be put back to sleep waiting for the next RTC interrupt.

Sleepwalking
Sleepwalking is a technology that enables peripherals to request a clock when needed to wake-up from sleep modes and perform tasks without having to power up the CPU Flash and other support systems. For instance, Atmel’s ultra-low-power capacitive touch-sensing peripheral can run in all operating modes and supports wake-up on a touch.

For the temperature monitoring application, as mentioned above, this means that the ADC’s peripheral clock will only be running when the ADC is converting. When the ADC receives the overflow event from the RTC, it will request its generic clock from the generic clock controller and peripheral clock will stop as soon as the ADC conversion is completed.

Event System
The Event System allows peripherals to communicate directly without involving the CPU and thus enables peripherals to work together to solve complex tasks using minimal gates. It allows system developers to chain events in software and use an event to trigger a peripheral without CPU involvement.

Again, taking temperature monitor as a use case, the RTC must be set to generate an overflow event, which is routed to the ADC by configuring the Event System. The ADC must be configured to start a conversion when it receives an event. By using the Event System, an RTC overflow can trigger an ADC conversion without waking up the CPU. Moreover, the ADC can be configured to generate an interrupt if the threshold is exceeded, and the interrupt will wake up the CPU.


SAM L21 MCU board

Low Power MCU Use Case

Paul Rako has mentioned a sensor monitor in his recent post in Atmel’s Embedded Design Worldblog. Rako writes in his post titled “The SAM L21 pushes the boundaries of low power MCUs” about this sensor monitor being asleep 99.99 percent of the time, waking up once a day to take a measurement and send it wirelessly to a host. Such tasks can be conveniently handled by an 8-bit device.

However, moving to IoT applications, which constitute protocol stacks, there is number crunching involved and that requires a faster ARM-class 32-bit chip. So, for battery-powered IoT applications, Rako makes the case for 32-bit ARM-based chip that can wake up, do its thing, and go back to sleep. If a high-current chip wakes up 10 times faster but uses twice the power, it will still use less energy and less charge than the slower chip.

Next, Rako presents sensor fusion hub as a case study in which the device saves power by skipping the radio chip to send the data from each sensor and instead uses the ARM-based microcontroller that does the math and pre-processing to combine the raw data from all sensors and then assembles the result as a simple chunk of data.

Atmel has scored an important design victory in the ongoing low-power game that is now prevalent in the rapidly expanding IoT market. Atmel already boasts credentials in the connectivity and security domains—the other two key IoT building blocks. Its connectivity solutions cover multiple wireless arenas—Bluetooth, Wi-Fi, Zigbee and 6LoWPan—to enable IoT communications.

Likewise, Atmel’s CryptoAuthentication devices come with protected hardware key storage and are available with SHA256, AES128 or ECC256/283 cryptography. The IoT triumvirate of low power consumption, broad connectivity portfolio and crypto engineering puts Atmel in a strong position in the promising new market of IoT that is increasingly demanding low power portfolio of MCUs to be matched with high performance.

Also see:

Atmel’s New Car MCU Tips Imminent SoC Journey

Atmel’s Ready to Wear Sensor Hubs

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.


embARC for a Free Ride

embARC for a Free Ride
by Eric Esteve on 03-30-2015 at 3:27 am

It’s probably the first time that Synopsys is offering such a direct access to free and open source software. The goal is to support customers developing application code for IoT and embedded devices based on ARC IP core family. The designer can select the Real Time Operating System (RTOS) which best meet the system requirements, unlike with ARC well-known competitor. Open source software also includes drivers, core services and middleware. Because the dynamic power consumption of the ARC EM processors can be as low as 3 uW/MHz, ARC IP core family is IoT preferred solution. embARC Includes commonly used components for the Internet of Things (IoT) such as MQTT and CoAP internet protocols as well as FreeRTOS and Contiki OS operating systems, helping to jump-start IoT development.


Synopsys has decided to offer a dedicated web portal (www.embarc.org) allowing ARC developers to freely download examples and documentation. This portal is also a forum for users to interact and get help from each other and even more a central repository for easy access to tools and embedded software to run on ARC EM processors. As far as I know, it’s the first time that one of the big 3 EDA/IP vendor proposes central repository capability. Central repository is a concept shared by large semi companies as well as open source software users/developers, quite often geeks considering that their work should be shared with the design community for free. This approach can help a design team starting to develop embedded software for IoT application to benefit from ready to use (open source) software functions, RTOS and drivers and greatly accelerate Time-To-Market (TTM).

embARC software can be split into middleware, libraries running on a RTOS, drivers and core services. The design team can freely download middleware like IoT comms, Networking, File System or GUI, standard toolchain and cloud libraries (C Lib, Maths Lib or Xively Lib) and select the RTOS of it choice. The benefits are multiple: cheaper development cost, faster TTM and the guarantee that the most appropriate solution will be selected to support embedded software development. Using ARC EM-based hardware development platform is a must-have to explore various design tracks, optimize and eventually validate the software.

ARC EM Starter Kit from Synopsys will help starting software development quickly, benefiting from lots of examples to get started with. This development boards includes timers, watchdog timers, UARTs, SPI, I2C, micro USB, SD Card slot, 20 pin JTAG and more. The ARC MetaWare toolkit complements this H/W offer, providing rich DSP software library and C/C++ Compiler as well as GNU tools support.


Availability and Resources
The embARC Open Software Platform is available now, at no cost at www.embarc.org.

embARC.org is a dedicated website that provides developers centralized access to free and open-source software, drivers, operating systems and middleware supporting the embARC Open Software Platform. The website also provides documentation and a forum-based community where developers can share their resources, expertise and code to help speed deployment of ARC-processor based embedded systems.

The ARC EM Starter Kit and the MetaWare Development Toolkit are also available now from the websites below:

From Eric Esteve from IPNEST


Life Without EUV: SPIE Day 2

Life Without EUV: SPIE Day 2
by Scotten Jones on 03-29-2015 at 11:00 pm

I previously published a summary of day 1 of SPIE and I wanted to follow up with observations from successive days.

SPIE, the international society for optics and photonics, was founded in 1955 to advance light-based technologies.Serving more than 256,000 constituents from approximately 155 countries, the not-for-profit society advances emerging technologies through interdisciplinary information exchange, continuing education, publications, patent precedent, and career and professional growth. SPIE annually organizes and sponsors approximately 25 major technical forums, exhibitions, and education programs in North America, Europe, Asia, and the South Pacific. www.spie.org
Tuesday 2/24 – day 2

Optical lithography with and without NGL for single-digit nanometer nodes – Burn Lin, TSMC
The paper began with a discussion of growth in cost per node from the 1.15x per node increase to 1.4x for the latest node. Issues with overlay were really the heart of this paper. The author discussed the many issues that can lead to poor overlay from warpage, back side particles, wafer non linearity due to uneven heating, mask flatness and particles, lens heating and others. The

The move to multi patterning is making overlay an even bigger issue. Overlying multi patterning over single patterning or multi patterning with 3 photo and etch steps on multi patterning with 2 photo and etch steps creates higher order overlay issues.

The authors sees ArFi single exposure limited to approximately an 80nm pitch. Multi pattering gains resolution by pitch splitting but creates cost and overlay issues. He see EUV with an NA > 0.33 as difficult and expensive to achieve as well as k1 < 0.4 being difficult yielding a pitch of 32.4nm, marginal for 7nm, may need some double patterning.

The key to solving the overlay issue according to the author is to go to single exposure and etch at all layers. A table was presented indicating that the least expensive option at N7 is single exposure with Multi beam E Beam (MEB). Interestingly this opinion appears to contrast with the more main stream TSMC approach of using EUV.

The author also discussed Directed Self Assembly (DSA) as a very useful option to reduce costs but one still having CD uniformity plus placement and defect issues.

Also read: EUV Makes Progress and Other Observations From SPIE 2015

Evolving optical lithography without EUV – Donis G. Flagello, Nikon
Nikon has stopped working on EUV leaving it to ASML. I came to this paper very interested to hear what Nikon’s roadmap is to move forward without EUV. I have to say this was one of the more disappointing papers I attended at SPIE. It was long on quirky “Latin like” nomenclatures but short on an actual roadmap.

Relative costs for 193i double and triple patterning versus EUV were presented showing EUV to be more expensive. Continued progress in ArFi scanner throughput was noted with additional increases in wafers per days forecast for 2018. Whereas 3,500 wpd was common in 2010, today 4,000 wpd is common and by 2018 6,000 wpd is forecast.

The author also offered that gains for 450mm are better for ArFi than for EUV.

There was a fair amount of discussion of resolution enhancement techniques that are being sued in optical microscopy and the potential to apply them to lithography. Immersion lithography after all is a lithography application of immersion techniques that have been used in microscopy for decades. This however struck me as a proposal for a research program as opposed to a particle roadmap.

Integration of NAND flash memory ISO multilayer etching to improve productivity – Chang-kwon Oh, SK Hynix
3D NAND is an area of intense interest for me and I am currently working on a blog discussing the impact I expect it to have on the industry.

Some of the key take aways from this paper were that for 2D NAND costs take off at the 1x, 1y and 1z generations. Cell to cell cross talk is also an increasing issue for 1x and subsequent generations.

SK Hynix expects to introduce 3D NAND in 2015.

3D NAND offers improved density, writing speed, endurance and power efficiency. The trade off is productivity, yield and complexity.


The Earth is Not Flat; Neither is IP

The Earth is Not Flat; Neither is IP
by Paul McLellan on 03-29-2015 at 7:00 pm

Chip design is largely about assembling pre-designed IP, either developed in other groups in the same company, or brought in from a 3rd party, or occasionally developed within the SoC design group itself. But that makes it sound like it is a bunch of blocks linked together with some interconnect, but of course another important aspect of real-world SoCs is the hierarchy. The SoC world is not flat just like the real world.

For example, an SoC might instantiate two Ethernet ports but each port actually consists of an Ethernet PHY and an Ethernet MAC. And the MAC might consist of bus interfaces, transmitter control, receiver control and more. Or an SOC might contain several USB ports but each on consists of a USB PHY and a USB controller.


There are several advantages of hierarchical IPs:

[LIST=1]

  • Abstraction: It is quite easy to integrate fully capable functional blocks in your design rather than a laundry list of individual IPs. This is much quicker and more intuitive
  • Compatibility: Does version 10 of the USB controller really work with version 7 of the PHY? Should I use the latest version of both these blocks and hope for the best? These kinds of questions can be eliminated by simply choosing the USB subsystems, where proven configurations with versions that work with each other
  • Dependency management: Bringing in a subsystem automatically brings in all the dependencies that are needed. There is no need for cumbersome dependency discovery, since the subsystem will bring in all the needed dependencies
  • Discovery: By looking at the hierarchies in which a particular IP of interest is used can help with easier discovery of the various components available to the team. For example, if the USB PHY is used in a hierarchy that contains other I/O interface blocks, it is very useful to be able to discover the context in which this block is frequently used. This can aid the design process immensely

    Methodics’s IP management suite ProjectIC has been built from the ground up to handle hierarchical IP subsystems. Each “IP” can either be a genuine standalone design object or a complete hierarchy.
    ProjectIC has many features that support hierarchical IPs:

    • Every IP can have a list of resources—other IPs that are in the system. These resources can also have resources of their own, and so on. Building a hierarchical IP in ProjectIC is as simple as including another IP as a resource. The tool automatically figures out any other resources that are implied by including this IP
    • Building a workspace with a hierarchical IP is handled seamlessly. All the resources that are part of the hierarchy are automatically instantiated in the workspace
    • Resource locations inside a workspace can be controlled with fine granularity
    • The tool automatically checks for circular dependency between resources, resource conflicts etc
    • Container IPs can be used to create hierarchy levels and compatible bundles
    • Each resource in a hierarchy can be independently moved from one version to another. This can be done in multiple different ways—from the command line, from the GUI etc—allowing for maximum flexibility in interacting with resources
    • Several other features like hierarchical releases, property inheritance, IP hierarchy traversal, tree views etc are also fully supported

    On a different topic, earlier this month the Methodics Industry Survey results were pulled together. The big picture results:More than 90% of respondents said IP is reused within their design projects and yet 31.7% are still managing IP manually through the use of spreadsheets, and another 39.7% are managing IP through home-grown solutions. Additionally, 28.3% of respondents said they have no IP defect-tracking solution in place.

    This sort of result reminds me of the story of two Victorian-era shoe-salesmen being sent to Africa. The first replies “no business here, nobody wears shoes.” The second salesman replies “huge opportunity, nobody wears shoes.”

    Only 30% of respondents use a 3rd party IP management solution. If you are not one of them, Methodics has some shoes for you.

    Full survey results are here


  • Passage of Time with Watches

    Passage of Time with Watches
    by Pawan Fangaria on 03-29-2015 at 7:00 am

    During my childhood in my native place in India, although there were good watches around from Seiko, Citizen and some of the Indian companies, I used to see some old men and women never using any watch but still being fairly accurate in perceiving time by just watching the position of sun, or moon, or the shadow formed by a certain object. Well, if we delve into what we call ‘sundials’ which were used by Egyptians, Greeks, Chinese, and others back in 1500 B.C. or before, they worked on the principles of movement of celestial bodies. They were used not only to observe time in a day, but also to record days, weeks, months, years and so on, and to determine arrival and departure of different seasons. The credit of invention of sundials goes to Egyptians.


    Here, I would like to recollect my memoir and illustrate an Indian sundial which I had personally seen in Delhi. Back then, I had just passed out of my 10[SUP]th[/SUP] class and had visited Delhi as a tourist. Above is a picture of ‘Samrat Yantra’, popularly known as ‘Jantar Mantar’ in Delhi; there are some more structures attached to it. Although I couldn’t understand the complex geometry used in calculation of time out of the shadows on these structures, I was told that the accuracy of time was in terms of seconds. They could find out the shortest and longest days of the year. No wonder, today also we have the concept of ‘day light saving’ to adjust our watches to alarm us at the right time. We have evolved to a large extent in terms of watches, but the guiding principles to determine time are the same, based on the movement of Earth, Sun, Moon and perhaps other celestial bodies!

    The evolution of watch industry has been very long, if not the longest. And interestingly, many of the older generation watches are still being used. The first spring-driven mechanical clock came in 15[SUP]th[/SUP] century which was used as a stationary time piece. Then the pocket-able watches, table watches, and stationary pendulum clocks, still driven on springs came between 15[SUP]th[/SUP] and 17[SUP]th[/SUP] centuries. The ‘Nuremberg Egg’ shown in the picture was made in 1510 by Peter Henlein who is considered as the inventor of watch. With every new generation of the watches, they improved in the accuracy of time. In 1761, the British government rewarded John Harrison with 20,000 pounds for improving the accuracy of clocks after “Scilly naval disaster of 1707” which was due to inaccuracy in calculation of positions of the warships.

    Well, if we see early evolution of watches, it appears to have taken centuries for small incremental updates. The first wristwatch appeared in 18[SUP]th[/SUP] century from the houses of Breguetand Patek Philippe. And then Rolextook another century to make waterproof watches. It goes on and on with improvements such as automatic, self-winding machine, battery driven, quartz driven, with additional functions such date, time, calendar, and so on. We could also see some intelligent functions done through watches, as we see them in old James Bond movies! However, the basic mechanism was mechanical and main function was time keeping in all those watches. It seems to be monotonous with so many centuries spent on a particular type of machine dealing with time as its only function, doesn’t it? So, naturally, the style and jewellery became the quotients embedded in high-end watches. We see so many high-end brands of watches today also being carried from 17[SUP]th[/SUP] and 18[SUP]th[/SUP] centuries. Added to them are many new brands too. Their primary function is to tell time, but they are worn conspicuously to reflect upon the personalities of their owners.

    A shift in the watch technology came in 1970s and 1980s when electronic digital watches appeared with LCD and LED displays. The first digital watch, Pulsar was introduced by Hamiltonin 1970 and then other companies such as Casio, Seiko, Intel, and Texas Instruments jumped into the fray. Run on quartz, they brought a revolution in watch industry sending the old mechanical watches out of business. However, indication of time remained as the prime function of watches, although a few built-in databases, dictionaries etc. were added. Display of time on LCD and LED screens with a variety of digital watches became so ubiquitous that it reflected on everything, your pen, key ring, car dashboard, office desk, computer screens, and so on; time was displayed on most of the noticeable objects. That trend has remained till date. The electronic LCD watches started becoming boring and their business was soon out of favour.

    By 1990s, perhaps the need was felt that more functions needed to be added on watches to keep them functionally relevant. With the arrival of mobile technology, most obvious appeared to be the phone communication and some amount of computing done through the watches. Multiple technology companies including IBM, AT&Tand Samsungstarted R&D in this area with AT&T patenting a wristwatch with phone in 1993. In 1998, it was Prof. Steve Mann, Electrical and Computer Engineering at University of Toronto who invented and designed the world’s first Linux wristwatch. For this work, Prof. Steve received the honour of “The Father of Wearable Computing” from IEEE ISSCC2000 in Feb 2000.

    Soon after this invention, in 1999, Samsung launched the world’s first commercial watch phone, SPH-WP10. This watch phone had integrated speaker and microphone and had about 90 minutes of talk time. It had a monochrome LCD screen. Then IBM developed a wristwatch with Linux 2.2, Bluetooth, 8MB memory, accelerometer, and fingerprint sensor. In the following years several other watch phones were launched by different companies, e.g. Fossil’sWrist PDA, Microsoft’sSPOT, Samsung’s next watch phone S9110, Sony Ericsson’s NBW series, and so on. However, the technology appeared to be too clumsy for watch phones and took a backseat.

    What was happening in parallel was the advent of mobile phones. The mobile phones with bigger screen sizes than watches were perceived to be better platforms for integration of other functions including time, computing, music, video, phone, conferences, and so on. The mobile phones surreptitiously came into the market, re-invented themselves into smartphones and stole the show. They snatched the market, not only from the budding watch phones but also from PCs and notebooks. The watch phones were again left in the lurch.

    However, the time doesn’t stand still; watches were yet to see their time. The mobile phone industry with several functions integrated into them gave a significant push to miniaturization in semiconductor ICs and SoCs and also a vast mobile network for data exchange. This ecosystem built by mobile phones again offered a ripe platform for watches to re-invent themselves in the modern context and see their luck!

    The actual journey of watches into the realm of what we call ‘smartwatch’ began in 2012 when Pebblewas unveiled. This smartwatch is compatible with iOS (the operating system used in iPhone) and Android (the Google driven OS used in other smartphones) based devices. It’s laden with features such as call alerts, SMS, iMessage, calendar, activity tracking, gaming, and so on. Interestingly, Pebble generated its initial funds for starting this project through crowd-funding. Today, we have more advanced smartwatches with Apple smartwatch to the fore. There are many others in the fray. And I believe the time for smartwatches has arrived now.

    If we look at the overall journey of watches through the passage of time, not even from sundial, but from an spring-driven watch in 15[SUP]th[/SUP] century to an smartwatch in 21[SUP]st[/SUP] century, what we have covered in last three decades is many times more than what we would have covered in previous five centuries! World is moving much faster now!!