SemiWiki – Page 755 – The Open Forum for Semiconductor Professionals

April 6, 2015September 1, 2024

What is Inside of the Samsung Galaxy S6?

What is Inside of the Samsung Galaxy S6?
by Daniel Payne on 04-06-2015 at 1:00 pm
Categories: EDA, Foundries, Mobile, Samsung Foundry

I’ve always been curious about what is inside an electronic device, and it was seeing the very first TI handheld calculator that got me started into a career as an Electrical Engineer. Next to Apple, the most popular brand in smart phone devices these days has got to be Samsung and they have just launched the Galaxy S6 device. A teardown company called Chip Works did the honors and has some beautiful photographs of what they found inside of the S6.

I’ve owned Samsung phones for the past 6 years, so am very familiar with their product line-up in general. What really sets the S6 apart from other phones are:

8 core processor
64 bit Operating System

In the past many smart phone companies would get to market quickly by using an application processor off the shelf from a company like Qualcomm, however Samsung is big enough that they can afford their own engineering team to design an application processor and they dub their octa-core the Exynos 7420. Apple is also well-known for custom-designing application processors as the A-series.

Even though the application processor brains in the smart phone tend to get top billing, there are a slew of other support chips also required to create a complete system. Inside of the S6 you will also find specialized chips like:

Instead of choosing a touch screen controller from well-known suppliers like Synaptics, Cypress, Atmel or a Chinese company we see that Samsung used STMicroelectronics instead in this model.

Related – Intel Core M vs Apple A8!

14 nm FinFET Samsung technology is used in the Exynos 7420 application processor, a more advanced process than the 20 nm TSMC technology that Apple has in their A8 chip.

Die mark, Exynos 7420

Top-level Metal, Exynos 7420

Here’s a quick comparison of die sizes for the last two generations of S phones from Samsung:

[TABLE] style=”width: 500px”
|-
| Phone
| Chip
| Die Size
| Technology
|-
| Galaxy S6
| Exynos 7420
| 78 mm^2
| 14 nm
|-
| Galaxy S5
| Snapdragon 801
| 118.3 mm^2
| 28 nm
|-
| Galaxy S5
| Exynos 5422
| 135 mm^2
| 28 nm
|-

Cross-sectional photos show some of the 11 layers of metal and FinFET structures:

Cross-section of metal stack, Exynos 7420

At DAC last year in San Francisco we saw one of the first wafers in 14 nm technology from Samsung, and this year we can buy a smart phone like the Samsung Galaxy S6 with 14 nm silicon, so FinFETs are enabling progress in consumer electronic devices already. Intel, of course was first to market with FinFET (aka TriGate) technology, so we should expect to see continued competition for FinFET silicon from TSMC, Intel and Samsung.

April 6, 2015

Security All Around in SoCs at DAC

Security All Around in SoCs at DAC
by Pawan Fangaria on 04-06-2015 at 12:00 am
Categories: EDA, Events, Foundries, FPGA, IP, Semiconductor Services

Last month I was on my way to write a detailed article on important aspects to look at while designing an SoC. This was important in the new context of modern SoCs that go much beyond the traditional power, performance and area (PPA) requirements. I had about 12-13 parameters in my list that I couldn’t cover in one go, so I put the write-up of first six parameters into a blog, “SoCs in New Context Look beyond PPA”. Security is definitely one of the most important parameters in my list, but I couldn’t cover that in the first blog. It was nothing to do with the importance of the parameters, but just a sequencing of those. It’s obvious how intricately our community is looking at the security aspects in SoCs; immediately after that blog was published, the first comment I received is that it missed ‘security aspect’!

Earlier, security was considered to be a software issue that could be patched. But today with the advent of IoT and SoCs encompassing several aspects of the whole system, it’s much more severe extending into hardware and also complicating the software issue with authentication, encryption, traceability, and so on. A hardware security breach stays there; it can’t be patched, so security proofing of hardware has to be considered upfront from SoC design stage. Similarly software architecture has to be considered along with the SoC design.

I’m yet to start writing the second part of my SoC article. But before that, as the DAC 2015 is approaching, I browsed through the DAC agenda. I’m amazed to see that it covers almost every aspect about security beyond what I was contemplating. As always, DAC provides a great indication about the way our semiconductor industry is progressing. I’m convinced that the future of semiconductor world will become fully secure. There are a host of events on security including keynotes, tutorials, SKY talks, special sessions, research paper sessions, and panels. It would be difficult to talk about all of them here, but I will try to highlight some of the important ones that enticed me. While I dive deep into some of those after knowing more about them in the actual DAC presentations, here is a list of items that are worth attending.

Tutorials on June 8, 2015

Building Secure Hardware and Software Systems – 10:30am – 12:00pm, 1:30pm – 3:00pm

Todd Austin from univ. of Michiganand Jin Yang from Intel will talk all about hardware and software breaches that happen today and how to prevent them through pre-emptive and reactive design techniques.

Introduction to Hardware and Embedded Security – 1:30pm – 3:00pm, 4:30pm – 6:00pm

Mark Tehranipoor from univ. of Connecticut, Miodrag Potkonjak from univ. of California, and Ronald Perez from Cryptography Research, Inc. will talk about design and test of powerful security primitives such as Physical Unclonable Functions (PUFs), public PUFs (PPUFs), True Random Number Generators (TRNG), and silicon odometers to meter device usage. Hardware Trojans and Counterfeits detection, prevention and open challenges. Foundations for on-chip security with a novel concept of ‘Root of Trust’ applied to semiconductors and semiconductor IP lifecycle.

There is also a research paper session 39, “Arms and Armor for the FUTURE” on June 10, 1:30pm – 3:00pm that focuses on these concepts and provides an insight into security-enhanced processors mitigating software vulnerabilities, innovative characterization and emulation methods empowering PUFs, hardware verification methods for Trojan detection , and so on.

There is another research paper session 53, “got security?” on June 11, 10:30am – 12:00pm that talks about optical imaging and formal verification methods for hardware Trojan detection, novel watermarking and obfuscation techniques to protect IP at chip and PCB levels respectively, on-chip voltage regulators that suppress side channel information leakage, and a novel TRNG design for FPGAs.

Keynote on June 10, 9:00am – 10:00am

Cyber Threats to Connected Cars: Staying Safe Required More Than Following the Rules of the Road

Speakers: Jeff Massimilla from General Motorsand Craig Smith from Theia Labs/ OpenGarages/ IACT. IACT abbreviates to ‘I am the Calvary’. Craig is also author of the Car Hacker Manual.

Moderator: John McElroy from Blue Sky Productions, Inc. John is also the host of Autoline Daily.

These gentlemen, veterans of cyber security in automotive, will talk about how vehicles can continue to evolve and support internet capability via WiFi and cellular data network, connect to mobile computing platforms via Bluetooth, provide GPS navigation, and automatically link to manufacturers to help with diagnostics. Cars need to be much more secure than computers at home!

Then there are great special paper sessions:

Special session 32: The Fourth Industrial Revolution: Security and Privacy Challenges in Industrial IoT on June 10, 10:30am – 12:00pm

Special session 46: Securing Cyber-Physical Systems (CPS): from Surveillance to Transportation and Home on June 10, 4:30pm – 6:00pm. In this session, speakers from government agency, industry and research institutions will join to introduce security challenges in several critical CPS domains. They will also present promising approaches in quantitative modeling, simulation and analysis of security elements, and in automated security-aware optimization and verification.

Special session 61: Validation, Validation, and Validation: The 1-2-3 of Secure SoCon June 11, 1:30pm – 3:00pm. This session will include both pre-silicon and post-silicon validation techniques including SoC security architectures.

Special session 69: The Lifecycle of Secure Chip Design on June 11, 4:00pm – 5:30pm. This deals with the whole design lifecycle of a cryptographic chip.

Do not forget to attend some of the SKY talks, they are like mini keynotes and are really interesting. There is one, “On the Matter of Trust” on June 11, 3:30pm – 4:00pm. This will be presented by Kerry Bernstein from DARPA (Defense Advanced Research Project Agency). He will talk about various kinds of electronic threats around us and the ideas DARPA is developing to mitigate them.

There is a panel discussion too, titled “Design for Hardware Security: Can You Make Cents of It?” on June 9, 1:30pm – 3:00pm. The panellists include industry veterans, academicians and researchers and it’s moderated by Saverio Fazzari from DARPA. This is an interesting discussion which highlights the vulnerability of hardware to security compromise, but still hardware takes a back seat in dealing with security. What should be done? Is there enough incentive in hardware security? Who should pay?

It’s a great opportunity exploring security issues, challenges, solutions, policies, regulatory, and so on in this DAC!

April 5, 2015

These Energy-Saving, Batteryless Chips Could Soon Power The Internet Of Things

These Energy-Saving, Batteryless Chips Could Soon Power The Internet Of Things
by admin on 04-05-2015 at 4:00 pm
Categories: IoT

Power consumption is always a major concern in the field of electronics, especially as the circuits controlling these electronics shrink in size while also growing in complexity. Utilizing a fairly new, ultra-low power technique known as a sub-threshold voltage mode for transistors operating in the circuit, the company named Psikick has developed what they call a “revolutionary” wireless sensor. Subthreshold sensors have significant power supply voltage (VDD) reduction, it is said to be 100 to 1000 times more power efficient than any other recently designed sub-threshold wireless sensor networks. The Department of Electrical Engineering at Texas A&M University published a paper in Circuits and Systems, 2005 titled, “Low power current mode ADC for CMOS sensor IC,” stating that they had created an integrated sensor utilizing sub-threshold and current mode techniques for low-power operation. The power consumption of their integrated circuit was under 6μW. According to the claims made by the Charlottesville-based company Psikick, this would mean that their wireless sensor technology only consumes between 6 and 60 nanowatts of power. Some of the benefits to such a low power design could include battery-less operation of the sensor, low-power voltage sources such as can be collected from wind, vibration, thermal gradients, solar, piezo actuation, and RF (radio frequency) energy scavenging. The applications for such a device could be limitless, useful in everything from medicine to athletics or the military. Such low powered sensors could be used indefinitely to measure patients heart rates or brain waves from the comfort of their own homes. They could be used in avionics to measure conditions outside the aircraft with little to no power input, or to measure the movements and heart rates of athletes for optimum performance on their field.

Another letter by the Dept. of Electronics & Computer Engineering at the University of Colorado at Boulder, published in Power Electronics in Dec. 2010, titled, “Custom IC for Ultra-low Power RF Energy Scavenging,” describes what makes these low power energy sources possible. They presented a custom integrated circuit including an ultralow power RF rectifying antenna power source and a microbattery for maximum power collection. This energy scavenger circuit operated a “boost converter in pulsed fixed-frequency discontinuous conduction mode to present a positive resistance to the rectifying antenna.” Their subthreshold current source was in the 200 nA range, placing their supply voltage in a range from 2.5 V to 4.15 V. This resulted in a power consumption of between 1.5 and 30 μW, with a higher conversion efficiency at higher voltages. This IC was made two years prior to Psikick’s wireless sensor, utilizing very similar technologies (CMOS, RF scavenging, subthreshold processes, etc.). Although the integrated circuit was designed for RF energy scavenging, the low-power “boost converter” mentioned is also responsible for the application of some other power sources mentioned, like wind, vibration, and temperature. On the homepage for the Psikick sensor, the Psikick team brags that their sensor is “Fully integrated and silicon-proven,” generally meaning that the technologies involved have proven to work as expected. However, no actual numbers are ever mentioned relating to supply voltages, dynamic or static power consumption, or subthreshold currents, with the exception of the 100 to 1000 times lower power claim. While this makes it difficult to determine any of the various technologies employed in the sensor’s development beyond speculation, the hype that Psikick has stirred up relating to their new technology definitely makes their design sound promising.

When a CMOS transistor operates at the sub-threshold voltage many problems start to be relevant. Problems that are normally insignificant or nonexistent when the transistors operate at normal conditions. When VDD is reduced, the dynamic energy also is reduced but the transistor leakage over longer time periods increases the leakage energy. Therefore it is necessary to balance both energies and find the best point of operation, normally at VDD (around 300-500 mV). Another problem is that the pMOS and nMOS thresholds are imbalanced and may lead to the need to change the circuit design to correct this difference. Circuits with several series and parallel transistors are another problem due to the stack effect, the series transistor will have less current when ON than the parallel transistors when OFF, making it necessary to raise the source current. Several parallel transistors are also a problem when the circuit is designed to operate as a static structure, since it will increase the leakage current and make the parallel transistor have a greater current when OFF than the series transistors when ON. Dynamic circuits should also be avoided, because the transistors logic works with subthreshold leakage current and this current gradually discharges the dynamic nodes.

Psikick is aiming to produce an application standard product for each vertical market. This helps on the production side of the chips but it also takes up extra space on the chip size level when they are going for more functions that will not be needed for every job. However this is not the main focus of Psikick since the goal was reduction in power consumed. With the amount of power savings, the use for these chips in The Internet of Things will be interesting to see. With the tiny size of these chips, the potential uses are going to seem limitless. Some such uses might be industrial process control, infrastructure monitoring, precision agriculture, medical biosensing, consumer wearables, smart homes/grids/cities, and many more according to the Forbes article about the new startup.

Some disadvantages to subthreshold processing may include a lowered processing power and a much slower speed. This is due to the much lower power constraints of a subthreshold circuit, and so the chip runs at only a “few tens of megahertz at most,” according to the article by Forbes. This is much slower than the gigahertz speeds at which most of us are used to having our chips run. On the plus side, however, there are many uses for which we do not need a significant amount of processing power but rather require minimal processes under extremely extended intervals. In a case such as this, being able to power a device, some type of monitor or sensor, for days, weeks, or maybe even years on end without ever stopping for a recharge or a reboot is a world-changing technology. Sending patients with bad hearts back home and monitoring their vitals via a subthreshold wireless sensor could not only save lives, but provide comfort while doing it. The opportunities for this new company and their circuit design are potentially limitless, and it will be exciting to see the spread of this new technology.

Article in question for reference: These Energy-Saving, Batteryless Chips Could Soon Power The Internet Of Things

By Adam Westman, Christian Sasso and Tanner Helton

The University of Mississippi Electrical Engineering Department introduced a Digital CMOS/VLSI Design course this semester. As part of this course, students researched a contemporary issue and wrote a blog article about their findings for presentation on SemiWiki. Your feedback is greatly appreciated.

April 5, 2015June 14, 2019

The Changing Foundry Landscape: Trends and Challenges!

The Changing Foundry Landscape: Trends and Challenges!
by Daniel Nenni on 04-05-2015 at 4:00 am
Categories: EDA, Siemens EDA

This will be a year of change for the fabless semiconductor ecosystem, absolutely. Last year we were wondering how Samsung Mobile was going to compete with the China clones and other low end smart phones. We now know the answer to that question thanks to the Chipworks tear down of the Galaxy S6. SemiWiki IP expert Dr. Eric Esteve blogged about it first HEREbut I can assure you we will see more blogs and Forum posts in the coming days because this is REALLY big news. Samsung has not only served notice to the fabless chip companies and mobile device makers, they have also sent a shot across the bow of the the mighty TSMC. Great timing too since I will be moderating a panel at the Mentor U2U Conference here in San Jose next week discussing just that:

The System on Chip (SoC) business seriously challenged the semiconductor foundries back at 28nm with increased integration, higher performance requirements, novel packaging methods, and very aggressive delivery targets. SoCs still drive semiconductor manufacturing technology at an increasingly rapid pace. This panel of experts will discuss today’s trends, challenges, and new applications that may drive future generations of semiconductor design and manufacturing.

And if meeting me isn’t enough, there are two very interesting keynotes as well:

“Secure Silicon: Enabler for the Internet of Things”
Keynote presented by: Wally Rhines, Chairman & CEO, Mentor Graphics
As electronic system hackers penetrate deeper—from applications to embedded software to OS to silicon—the impact of security threats is growing exponentially. Viruses and malware in the operating system, or application layer, are major concerns, but only affect a portion of users. In contrast, even small malicious modifications or compromised performance in the underlying silicon can devastate system security for all users. Growth of the Internet of Things magnifies the impact of the security problem by orders of magnitude.

Since hardware is the root of trust in an electronic product, EDA companies will be increasingly pressured to solve the silicon security problems for their customers. This requires a new paradigm in silicon design creation and verification. The traditional EDA role is to design and then verify that the silicon does what it is supposed to do. Creating secure silicon, however, requires that verification ensure that the chip does nothing that it is NOT supposed to do.

The industry is at the first stage of Secure Silicon awareness; it’s going to become big business as future events unfold. Join Wally Rhines as he examines the growing threats to silicon security and EDA’s possible solutions.

“Mega Trends Driving Architectures of Mobile Computing and IoT devices”
Keynote presented by: Karim Arabi, VP of Engineering, Qualcomm
The mobile computing and communication industry has been characterized by constant changes and rapid expansions. Aggressive silicon integration technology scaling, advanced low power design techniques, efficient mobile wireless and connectivity solutions and advances in a plethora of sensor technology have been critical in enabling mobile computing in a ubiquitous and cost-effective manner. Mobile computing continues to drive innovation in technologies that will enable new use cases and applications in an energy and cost efficient manner. The industry is now evolving quickly to leverage these capabilities to address the emerging wearable and IoT opportunities expected to sustain growth for the next decade. Choice of device architectures and features are impacted by market requirements and mega trends. In this presentation mega trends, opportunities and challenges driving next generation mobile and IoT devices will be reviewed.

This is a FREE CONFERENCE so I hope to see you there!

April 4, 2015June 14, 2019

Variation Alphabet Soup

Variation Alphabet Soup
by Paul McLellan on 04-04-2015 at 1:00 pm
Categories: CLK Design Automation, EDA

On-chip variation (OCV) is a major issue in timing signoff, especially at low voltages or in 20/16/14nm processes. For example, the graph below shows a 20nm inverter. At 0.6V the inverter has a delay of 2 (nominalized) units. But due to on-chip variation this might be as low as 1.5 units or as high as 3 units, which is a difference from slow to fast of 100%. Variation is not so bad at 1V but, for power reasons, everyone wants to get the voltage as low as possible since it is squared in the power equation also reduces leakage. Voltage is like sailing, if you want to win races, you have to sail close to the wind even though it is more difficult.

The problem is on-die variation. We can’t assume that if one transistor is faster than typical that the transistor it is driving is also faster. There are a number of reasons for this but one big one is that optical proximity correction (OPC) means that identical transistors do not end up identical on the mask since that depends on what is around them.

In response, foundries have broken out on-die variation as a separate component in their SPICE models. They created global corners for slow, typical and fast. These global corners, called SSG (slow global), TTG (typical global) and FFG (fast global), only include between wafer variance. On-die variance is separated out as a set of local parameters as part of the SPICE model that work with Monte-Carlo (MC) SPICE around the global corners. Analog designers routinely use these global corners and local parameters to validate cells. These same global corners and local variance parameters can be used to create derates or adjustment factors for static timing and physical optimization of digital designs (and the digital parts of mixed-signal designs).

But how do you put this into the sign-off timing flow and delay models?

Obviously something needs to be done so everyone did something. Cadence, Synopsys and TSMC have all used multiple acronyms: OCV, AOCV, SBOCV, SOCV, POCV and LVF. Too many TLAs (and FLAs).

So how is all this represented? That’s what all the alphabet soup is about. The three main ingredients to the soup are OCV (on-chip variation), AOCV (advanced on-chip variation) and LVF (Liberty variance format). The table below shows the details.

The bottom line is that OCV works well for 45nm and above but isn’t good enough for 28nm and below. SBOCV is TSMC’s name for adding more accuracy, and AOCV is what Cadence and Synopsys call it in their timing tools.

AOCV suffers from a major limitation though. There are only 8 values to cover all the different timing arcs through a cell. Even a simple two-input NAND gate may have 128 different AOCV multipliers: two inputs times 4 input slew rates times rising/falling times 8 output loads. To get it down to 8, the worst-case derates (or near worst) need to go in the file. But this means that AOCV is still unnecessarily pessimistic.

The solution is to use Liberty Variance Format (LVF). Why?

unlike OCV (1 value per process corner) or AOCV (8 values per cell per corner), LVF models all possible conditions for a cell. Every arc, load and slew has unique variance information
it is an independent standard governed by the Liberty TAB (that also controls the Liberty library format) approved in 2013 and revised in summer 2014 to support constraint uncertainty and slew sigma
SOCV (a TSMC format) maps back and forth with LVF since the contents are largely the same, so there is no problem using LVF for designs that will be manufactured by TSMC
PrimeTime (Synopsys) and Tempus (Cadence) both support LVF

The biggest advantage of LVF is that it drives static timing accuracy much closer to MC SPICE, the ultimate benchmark. As a result, it will also produce more accurate slack numbers. On the whole, when compared with OCV, this will improve overall slack as compared with OCV or AOCV.

The graph below shows it. Red is MC SPICE so the goal is to be as close to red as possible. LVF is green and is clearly closer than either OCV or AOCV. LVF’s rich data set enables an STA tool to dramatically improve overall accuracy compared with other approaches relative to MC SPICE.

So, in conclusion, LVF is the clear long-term winner. It will be in full production usage over the course of 2015. It is the most robust solution, and addresses all of the limitations of AOCV. Semiconductor teams that are intent on delivering 16nm, 14nm or 10nm silicon would be well advised to begin investing in an LVF design flow today.

TL;DR Use LVF

Download A Brief Introduction to Liberty Variance Format from CLKda here.

April 3, 2015December 27, 2023

Qualcomm LTE Modem Competitors? Samsung, Intel, Mediatek, Spreadtrum, Leadcore… or simply CEVA!

Qualcomm LTE Modem Competitors? Samsung, Intel, Mediatek, Spreadtrum, Leadcore… or simply CEVA!
by Eric Esteve on 04-03-2015 at 9:35 am
Categories: Ceva, IP

What is common between the 4G LTE modems from Samsung, Intel, Mediatek, Spreadtrum or Leadcore? All these chips are architecture with CEVA XC4000 family supporting 4G LTE-Advanced, LTE, HSPA/+, W-CDMA, TD-SCDMA, and legacy GSM/GPRS/EDGE. Samsung organization is vertical, the company design and manufacture DRAM, NAND and logic IC (System LSI) like Exynos 7420 octa-core application processor and Modem 300 Series, all these chips being integrated into the Galaxy S6 smartphone, as recently shown by Chipworks in this teardown: Samsung Shannon 333 Modem, Shannon 533 PMIC, Samsung S2MPS15 PMIC, Samsung Shannon 928 RF Transceiver and Samsung Shannon 710 Envelope Tracking IC.

Samsung is targeting high end smartphone market enjoying 326 million units shipped in 2014, directly competing with Apple (191 million units in 2014) on this segment. If you look at the modem market share, Apple integrates Qualcomm’s MDM9x35 cellular modem when Samsung integrate their in-house modem into the Galaxy S6 smartphone… except maybe in the US! In fact, In order to work properly on Verizon and Sprint networks in the United States, smartphones still need to support CDMA technology. More likely Qualcomm’s MDM9x35 cellular modem will be integrated into Samsung’s smartphone sold in the US. With more than 500 million units shipped last year, Apple and Samsung cumulated market share in the high end smartphone segment is in the 70-80% range. It’s reasonable to say that Qualcomm own 50% share… and that CEVA powered modem the remaining 50%, on the high end segment.

Global smartphone shipments totaled 1.167 billion units in 2014, but a strong part of these devices were not high price branded smartphones from Apple or Samsung. For example combined shipments of Chinese brands have reached 453.4 million units. And we have seen the emergence of the ‘super-mid’ market segment covered by chip vendors like Mediatek, Spreadtrum or Leadcore. You probably can’t sell many $600-800 smartphone in China, but if a local brand can price it in the $200 to $300 range (which is more or less equal to the Bill of Material for branded smartphone) then you can expect reaching much higher volumes. This was true in 2014, (453 million units shipped by Chinese brands) and will be even more true in 2015. Branded smartphone shipment are expected to stay flat and most of the growth will come from these Chinese brands integrating modem developed by the ‘super-mid’ market actors (see above) in parallel with much lower cost devices.

If we zoom to the smartphone supporting LTE, China’s LTE base is expected to treble to 300 million by the end of 2015, (overtaking the US). Targeting such production level is possible in China as OEMs are able to release LTE smartphone at a fraction of the cost of branded products. For example Xiaomi announced their first CEVA-powered LTE smartphone with Leadcore CPU – called the Redmi 2A – available for $80 at launch! This price is 10 to 15% of the latest iPhone or Galaxy selling price and that makes LTE smartphone affordable for many peoples in China. Reaching this target of 300 million LTE devices in 2015 becomes easier to reach with $80 if not $65 smartphone.
If you need another example, just look at this press release from Spreadtrum:

SHENZHEN, China, April 2, 2015 – “Spreadtrum Communications (“Spreadtrum”), a leading fabless semiconductor in China with advanced technology in 2G, 3G and 4G wireless communication standards, today introduced two new quad-core SoC platforms, the SC9830A, which supports 5-mode LTE, and the SC7731G, which supports WCDMA, both designed with 28nm process technology. Spreadtrum further announced that it has achieved volume shipments of these new smartphone solutions, which are now shipping in handsets launched by leading global brands designing smartphones for both China and global markets.”

Interesting to notice, Spreadtrum has targeted 28 nm process to develop this integrated (CEVA powered modem + Application Processor) solution, not the expensive 16nm FinFet, to serve the cost effective smartphone segment…

It will be interesting to evaluate who is the winner at the end of 2015 in term of LTE modem shipments. The chip maker Qualcomm, serving Apple (and maybe Samsung in the US) among other OEM or CEVA providing LTE solution to Samsung, Leadcore, Spreatrum, Mediatek or Intel through the DSP IP core integrated into the modems developed by these chip makers…

By Eric Esteve from IPnest

April 3, 2015

DAC Keynotes: Mark Your Calendar

DAC Keynotes: Mark Your Calendar
by Paul McLellan on 04-03-2015 at 7:00 am
Categories: EDA, Events, Foundries, IP, Semiconductor Services

DAC starts in San Francisco on June 8th. The kickoff keynote at 9.20am that morning is by Brian Otis of Google. He is a director at Google[x]. According to Wikipedia:Google X, stylized as Google[x], is a semi-secret facility run by Google dedicated to making major technological advancements. It is located about a half mile from Google’s corporate headquarters, the Googleplex, in Mountain View.
Brian is also a Research Associate Professor at the not-so-secret University of Washington in Seattle. His keynote is titled Google Smart Lens: IC Design and Beyond. Google Smart Lens is a contact lens that also continuously monitors blood sugar levels for diabetics. Last July Novartis announced that they were partnering with Google to create a commercial product. One of the things that will change as wearable medical products become widespread is this type of continuous monitoring. Today we have very little information about our bodies when we are sick, and pretty much none when we are healthy.But this is DAC and so is about design. In Brian’s own words:I’ll share thoughts on the scarcity of power, extreme miniaturization, and end-to-end connected systems that span the design space from transistors to the cloud. Along the way, I’ll cover chip design techniques for body-worn systems and wireless sensors and present examples of constantly-connected devices for improving healthcare. These areas present tough unsolved problems at the interface between the IC and the outside world that cannot be solved by transistor technology scaling alone. Novel power sources, low power IC design techniques, microscale user interface technologies, and new system integration techniques will be a few of the enabling technologies for these emerging systems.
Tuesday’s keynote is also at 9.20am and is by Jeffrey Owens who is the CTO at Delphi Automotive. His talk is titled The Design of Innovation That Drives Tomorrow. When people think of high tech devices, the first things that come to mind are not cars, trucks and vans. Today’s vehicles possess more processing power than anything most consumers own or will purchase. A typical car is equipped with more than 50 computers designed to operate at automotive grade capabilities for an extended period of time. Electronics and design automation will play a critical role in shaping the future of automotive by providing design technology that helps save lives, protect the environment and provide a satisfying in-car experience for drivers and passengers alike.Keeping to the automotive theme, on Wednesday morning at 9am there will be a keynote panel Cyber Threats to Connected Cars: Staying Safe Requires More Than Following the Rules of the Road moderated by John McElroy of Blue Sky Productions. The first presenter is John Massimilla of General Motors who has the wonderful James Bond job title as Chief Product Cybersecurity Officer, Vehicle and Vehicle Services Cybersecurity. Next up, Craig Smith of OpenGarages.org a community driven vehicle research and exploration group.Then, on Thursday at 9.15am John Rodgers of University of Illinois at Urbana-Champaign will talk about Electronics for the Human Body. Biology is soft, curvilinear and adaptable; silicon technology is rigid, planar and immutable. Electronic systems that eliminate this profound mismatch in properties create opportunities for devices that can intimately integrate with the body, for diagnostic, therapeutic or surgical function with important, unique capabilities in biomedical research and clinical healthcare. But wait, there’s more.At 9am on Tuesday there is also a visionary talk from Vivek Singh who is an Intel fellow on Moore’s Law at 50: No End in Sight. You don’t need me to give you the background on Moore’s Law. Vivek’s talk will provide some examples of how complex problems have been overcome in recent technology nodes, including those from the field of Computational Lithography. Inverse Lithography and Source Mask Optimization are two such examples that have helped extend the life of 193 patterning. Such innovations, fed by a rich technology pipeline, give us confidence that Moore’s Law will continue.The DAC page with more details of the keynotes is here.

April 2, 2015June 14, 2019

ANSYS Event to Highlight Cutting Edge Technology Development

ANSYS Event to Highlight Cutting Edge Technology Development
by Tom Simon on 04-02-2015 at 5:00 pm
Categories: Ansys, Inc., EDA

If you follow technology news, it would be hard to deny that we live in exciting times. In some ways there is an unparalleled amount of big and cool technology development going on right now. We all have followed the rise of Tesla Motors. They took over a long vacant US big-auto plant in Fremont and are reinventing the US automobile industry. Tesla CEO Elon Musk is also the progenitor of Hyperloop, which promises to bring huge change to terrestrial transportation. Space launches by private companies are something we are hearing about with increasing regularity. Even wild ideas like the levitating skateboard from Back To The Future are starting to move toward reality.

This is not even mentioning the “Dick Tracy” watches that are heading our way. We all know that product design capability is rapidly accelerating. Quite honestly we are finally getting the things that we were promised in Tomorrow Land. Who remembers seeing the ‘video phone’ there at Disneyland in the early 70’s? At the core of all this there is the technology that supports the development of these products; and there are the visionaries that push and apply this technology.

ANSYS is a technology company that provides an amazingly wide array of software for designing things from on-chip inductors all the way up to spacecraft. They are hosting their 2015 Convergence Conference on April 21 2015 in Santa Clara. Not only do they have a good mix of talks based on applications of their design and analysis software, but they have assembled a fascinating line up of keynote speakers. First up is Josh Giegal with Hyperloop. Hyperloop is moving forward in 2016 with the construction of a 5 mile track along California’s I-5 in the Central Valley. Josh’s talk is about their simulation based development process for their complete system. The initial build of the 5 mile loop will not achieve the top speeds they ultimately are planning for, but will allow them to work out the finer points of the system, including passenger loading, etc.

Following Josh will be Thomas Markusic from Firefly Space Systems. (Any Joss Whedon fans out there?) He previously worked at Space-X, but started Firefly to build practical small-satellite launch systems. Thomas’ talk should be fascinating. He likes to talk about rockets as being systems that are highly out of equilibrium. Nature of course hates this, which is what makes rocket science so challenging.

The keynotes come back to earth with Mark Frohnmayer talking about his electric car startup Arcimoto. He is looking for efficient and practical design solutions to produce feasible consumer products. For instance he is opting to use lead acid batteries – proven low cost technology rather that lithium ion.

Finally what wiz-bang line up of new technology would be complete without a discussion on magnetic levitation? Greg Henderson, who founded Arc Pax, will talk about their magnetic hoverboard that is featured on Kickstarter. Quite a line up, and this is before we even get to the other talks by ANSYS and their customers covering numerous additional real world applications for their broad line of multiple physics products.

There will be four tracks in the afternoon: Fluid Mechanics & Multiphysics, Structural Mechanics, and two on Electronics. On SemiWiki.com we usually focus on electronics design, and this ANSYS-wide agenda has plenty of talks directly related to electronics. They include IC and PCB design and analysis talks by Emulex, Applied Micro Circuits, and of course several ANSYS speakers. The topics range from ESD, board and package co-design, signal integrity to electromagnetic design and analysis.

Interestingly the other two non-electronics tracks have some interesting fodder for designers of electronics based products. There is a talk on simulating a li-Ion battery solution. Another talk covers multiphysics simulations for wearable devices. Plus there are a lot more talks that look compelling. One that caught my eye was on the structural analysis of the new San Francisco Bay Bridge design.

All this and a free lunch! The ANSYS Convergence Conference looks like a great event to learn more about applications in, and adjacent to, electronics design. It will also offer excellent networking opportunities and hopefully create formal and informal conversations that could drive exciting new technological development.

April 2, 2015

SEMI Wafers to Wallstreet – New England Forum March 12, 2015

SEMI Wafers to Wallstreet – New England Forum March 12, 2015
by Scotten Jones on 04-02-2015 at 4:00 pm
Categories: ESD Alliance, Semiconductor Services

On March 12 SEMI held a New England Forum breakfast event entitled “Wafers to Wallstreet” with four speakers. The main focus of the discussion was on the “Internet of Things” and the following are my impression from the talks in a bullet point format.

Device Scaling and Performance in the Era of IoT – Gary Rosen, Applied Materials

New devices and technologies are required for IoT.
Ion implant has a growing role in precision materials engineering.
Even though IoT devices may be simple, the servers in the background that support IoT will need a lot of processing power.
Traditional ion implant has been focused on doping, emerging ion implant applications are in precision materials engineering – using ion implant to change materials properties.
Companies create baseline flows and then add ion implants to meet their performance targets.
Hot implant is ion implantation at high temperatures (how high wasn’t disclosed) to maintain the crystallinity of the area being implanted and to achieve high dopant activation.
Cold implant is ion implant at lower temperatures (once again the actual temperature was not disclosed) to increase damage for amrophization implants.
First generation FinFETs have approximately 3 doping implants for each material implant, for generation 2 it will be approximately one to one and for generation 3 FinFETs materials implants may outnumber dopant implants.

Semiconductors Everywhere – Mark Thirsk, Linx Consulting

Electronic systems show a high degree of correlation to worldwide GDP.
Electronic systems sales are growing as a percentage of GDP although they are still very small on a percentage basis (~3%).
Industrial and automotive are showing the best electronics growth at 15% and 9% CAGR respectively. Consumer, wireless and wired communications and data processing are all in the 0% to 3% growth range.
Smart phones and tablets are growing faster than PCs and in some cases replacing them.
The traditional markets for semiconductor are changing with the PC no longer as dominant.
Billion of sensors and actuators will be needed mainly made in older technology.

Semiconductors and Semiconductor Equipment – C.J. Muse, Evercore ISI

This is a demand driven semiconductor cycles, less volatility, more gradual, think it has legs to 2016 and beyond.
Semiconductors are becoming GDP plus growth – GDP +5%, thinks semis grow 6% for 2015 and 2016.
A lot more generalists are starting to invest in semis.
Free cash flow is becoming important; investors are interested in sustained cash flow.
Investors are recognizing the higher margins in analog.
He thinks there is room for semiconductor stocks to move higher.
Smart phones demolished GPS and cameras, think consumer has now bottomed out.
Automotive content is rising.
Thinks there will be more consolidation and m&a.
Growth will be slower but less cyclical.
Analog is moving into the top ten for market caps.
Lines are blurring between analog and digital, IoT will need both.
Thinks Broadcom and Qualcomm are going to need to add analog capability to service IoT applications.
Capital intensity is rising, 40% increase for 10nm over 14nm.
Etch and deposition is a key now, foundry and 3D NAND are growth areas.
Fabless guys are getting squeezed, talk about Apple and Huawei making their own chips.
Thinks China will be a player in 28nm and lagging edge technologies.

A Wall Street Perspective: How Process Complexity, IoT and China – Weston Twigg, Pacific Crest Securities

Thinks costs are increasing 20-30% per node versus historical 5-10%.
Seeing a lot less design starts.
Thinks timing between nodes may slow plus slower ramps, may see less companies make the change to new nodes, more reuse.
Value of local processors is declining, more power in the cloud.
Processor costs were hundreds of dollars and are now evolving to tens of dollars.
Samsung Xian is at 40k wpm of 3D NAND ramping to >= 100k wpm.
Demand is growing fastest in lagging technologies.
China investing heavily, may play well in lagging nodes.

Discussion

Mark – thinks the real value of IoT is when the data gets up to servers and you have the right kind of expert systems.
Security concerns could be a possible headwind for IoT.
IoT can add biometrics for enhanced security.
New fab construction slowing, a lot of repurposing of 200mm fabs, some 300mm fabs on older nodes in China.
C.J. – could there be a shortage of 200mm equipment. Will companies make the investments given the new focus on cash flow. TI analog only at 50% capacity, other analog around 80%.
C.J. – 28nm was a 2 year ramp, 16/14nm will be a 3 year ramp. Thinks 10nm is a key node because it will be a full shrink.
Mark – tier one guys are going down the roadmap but guys like NXP and ST are using older technologies and their fabs are ageing and spare parts are hard to find. Will they go to 300mm and is there a market for less capable 300mm equipment.
C.J. – think China is primarily a threat as a fast follower.
C.J. – thinks Micron will roll up Inotera and Nanya in the next two years.
Weston – Teradyne has said parallel testing has hit a limit and could drive more demand for test equipment.
C.J. – DRAM, Samsung had a one year lead over Micron and 6 months over Hynix, what happens when Micron comes up on 20nm. What happens as 3D ramps (presumably NAND), will there be a drop in margin. Intel qualified into iPhone 6 and Samsung Galaxy, thinks Intel will be a real player in SOC. Thinks 10nm and below for foundry really changes their business model. TSMC has too much pricing power, if Samsung stumbles Intel could be a big player. Thinks Intel could be a player at 10nm and 7nm.
Weston – in response to a question about the next equipment down cycle – 3D NAND and FinFET build outs are driving the current cycle, could be weakness when they end but haven’t see over building that has driven contractions in the past.

April 2, 2015

EDPS: Fins and FinFETs

EDPS: Fins and FinFETs
by Paul McLellan on 04-02-2015 at 7:00 am
Categories: EDA

Look at those dolphins with fins on their backs. Did you know that FinFETs are actually named after them since Chenming Hu and his team though that they looked like a fish’s fin? And since they invented FinFETs they got to name them too. But those dolphins also mean that it is nearly time for this years Electronic Design Process Symposium (EDPS) which is held as usual in the Monterey Beach Hotel. This year it is Thursday and Friday April 23rd and 24th.

I blogged earlier this weekabout the Linley Mobile Conference and the observant among you will notice that they overlap, the second day of Linley is the first day of EDPS.

Apurna Dey of Cadence is the general chair and opens the meeting on Thursday at (I’m guessing, the program doesn’t have any times at all yet) 9am.

The first session is chaired by Dan Nenni and is on FinFET vs FD-SOI. It kicks off with a keynote from Tom Dillinger of Oracle (think Sun) followed by a panel session with Tom, Kelvin Low of Samsung Foundry, Boris Murman of Stanford University, Marco Brambilla of Synapse Design, and Jamie Shaeffer of GlobalFoundries:

The emergence of multiple transistor technology options at today’s deep submicron process nodes introduces a variety of power, performance, and area tradeoffs. This session will start with an overview of the FinFET and Fully-Depleted Silicon-on-Insulator devices (FD-SOI, also known as Ultra-Thin Body SOI), in comparison to traditional bulk planar transistor technology. The session will then delve into a detailed discussion of the architectural and circuit implementation tradeoffs of these new offerings, to assist designers make the right choice for their target application.

That takes us up to lunch. After lunch it is Multi-Die Design Challenges and Applications, which I think is just a long title for 3DIC. The sessions are:

Herb himself on 3D-IC EcoSystem Today and What’s Next
Brandon Wang of Cadence on Versatile 3D-IC Design Environment
Dusan Petranovic of Mentor on Verification and Extraction of 3D Stack Components Interaction
Rich Rice of ASE on Multi-die Packaging—How Ready Are We?

Then a change of scenery with Hybrid Virtual Platforms moderated by Gary Smith (himself, as Regis McKenna’s business card used to say) and John Swan (now of Intel). Sessions are:

Vikramheet Singh of nVidia on Hybrid Pre-Silicon Platforms for Accelerated SW Development
Vinoo Srinivasan of Intel on Hybrid VP – Are they the highbred Virtual Platforms?
Frank Schirrmeister of Cadence on Stop Abstracting! Use the Real Design Earlier for Software Verification Using Hybrid Approaches
Russel Klein of Mentor on The Need For Speed

After that it is off to dinner at the Monterey Yacht Club down on the old wharf. The dinner keynote is by Dileep Bhandarkar of Qualcomm titled The Yellow Brick Road of Semiconductor Technology. The talk will provide a historical perspective on how the computer industry has taken advantage of Moore’s Law and how we got to the era of multicore processors. The talk will also address some of the challenges facing the industry in the future.

And so to bed. Next morning we wak up to Low Power Day. The keynote is by Jim Kardach of FinSix on Low Power Design, Standards and Evolution.

Naresh Sehgal then chairs a session on Low Power Technologies and Ecosystems. Presentations are by:

Steve Carlson of Cadence on Low-power and Mixed Signal Solutions
Pat Sheridan of Synopsys on Power-aware Architecture Design for Multicore SoCs
Bernard Murphy of Atrenta on Low Power on the Bleeding Edge
Prasad Subramaniam of eSilicon on Low Power Design Methodologies

After lunch, Andrew Khang of UCSD gives a keynote on EDA/ESL Low Power Design Trends, ITRS/CAD and Tools. That wins the prize for getting the most acronyms into a title.

There is then a panel session with Brian Fuller of Cadence as the emcee. The subject is Can Power Go Any Lower or Have We Hit Almost Hit the Floor, Especially For IoT Devices?which wins this conference’s prize for getting the most words into a title (they could have got bonus points for spelling out IoT in full). The panel participants are Jim Kardach along with the presenters from the previous session.

Nahresh Sehgal and Apurna Dey close out and send us all back on our way up Highway 1.

Complete program info and a link for registration is here. Be sure and use promo code SemiWiki-EDPS2015 for a reduced rate.