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April 10, 2015

From Medical and Wearables to Big Data, in 日本語/한국어/中文

From Medical and Wearables to Big Data, in 日本語/한국어/中文
by Paul McLellan on 04-10-2015 at 7:00 am
Categories: eSilicon, Semiconductor Services

Whether it’s a tiny always-on medical device or a secure cloud network processing Big Data, the Internet of Things (IoT) is bringing new challenges to IC design. Almost by definition an IoT device contains a microcontroller of some sort along with some way of communicating. Unlike our smartphones where we are reasonably happy if they last all day before requiring a charge, IoT systems, and thus the chips in them, have to last much longer. Current wearables such as Fitbit will last a week but some IoT devices are expected to last much longer, perhaps their whole lifetime, without a charge. Or even to scavenge power from the environment. Under those constraints, every tiny bit of power is important. To make things worse, many of these devices are likely to be “always on” meaning that at least a small part of the design must be permanently powered up to notice when something interesting happens. Both active power and static power are critical for maintaining long battery life. Therefore optimizing for very low voltage as well as very low leakage is important. These devices typically operate significantly below 100MHz.

One of the big challenges in these types of conditions is having memory that works reliably. Most available memory IP is not optimized for these criteria. Most semiconductor foundries prefer to develop and manage the SRAM bitcells. Because SRAM cells are limited by stability (or static noise margin) and write ability (or write margin) the lowest operating voltage (VDDMIN) is carefully specified. The random threshold variations in subnanometer technologies have resulted in serious yield issues for realizing low VDD READ/WRITE operations with a typical 6T SRAM cell. The use of different cell topologies may improve the SRAM stability at low operating voltages.

eSilicon has developed statistical simulation techniques to determine statistical failure probability distributions for low-voltage failure modes for various bitcell topologies. Bitcell read current, read-disturb margin, write margin, minimum data-retention voltage (MDRV), and leakage current are all thoroughly analyzed. These techniques enable quantification of actual failure rates as a function of critical process parameters, temperature, voltage, and design parameters. Effective design optimization for optimum VDDMIN, power, performance, and yield is enabled by these efficient simulation techniques. The result is a series of optimized SRAM architectures that operate below 100MHz, below 0.7V, and at one-fourth the leakage power of other available SRAM compilers at 65nm, 55nm, 40nm and 28nm technologies.

Associative lookup structures lie at the heart of many computing problems and content-addressable-memories (CAMs) provide fast constant time lookups over a large array of data (content keys) using dedicated parallel match circuitry. The two most common search-intensive tasks that use CAMs are packet forwarding and packet classification in Internet routers. For a lot of these applications, ternary CAM (TCAM) is an even more powerful primitive, able to simultaneously search through a large number of subspaces of a higher dimensional space in one shot. eSilicon’s 14/16nm TCAM compiler offers 1 gigasearch/s under worst-case conditions with low- power search features.

eSilicon have created a white paper From Medical and Wearables to Big Data: Differentiated IP for the IoT Spectrum available here.

eSilicon also created a webinar recently on this topic, focusing on ultra-low-power and ultra-low-voltage memory solutions. This webinar was, by far, the most popular eSilicon have done. Interest came from all over the globe. When the replay went up, interest again came from all over the globe (see the map below).

eSilicon decided to do something that they have never done before, they presented the webinar 3 more times in Japanese, Korean and Chinese. So you can watch:

In English with Lisa Minwell presenting, Senior Director of IP Marketing eSilicon
In Japanese 日本語 with Zenda Nguyen, Program Manager, IP Business Unit, eSilicon Vietnam
In Korean 한국어 with Taeho Kim, Country Manager & GM, eSilicon Korea
In Chinese 中文 with Kar Yee Tang, IP Product Marketing Manager, eSilicon

All four videos are available for replay here.

April 9, 2015June 14, 2019

ANSYS Enters the League of 10nm Designs with TSMC

ANSYS Enters the League of 10nm Designs with TSMC
by Pawan Fangaria on 04-09-2015 at 7:00 pm
Categories: Ansys, Inc., EDA, Foundries, TSMC

The way we are seeing technology progression these days is unprecedented. It’s just about six months ago, I had written about the intense collaboration between ANSYSand TSMCon the 16nm FinFET based design flow and TSMC certifying ANSYS tools for TSMC 16nm FF+ technology and also conferring ANSYS with “Partner of the Year” award. Read “ANSYS Tools Shine at FinFET Nodes!”. Just before this Intel also certified ANSYS tools at 14nm Tri-gate process as written in another article, “Intel & ANSYS Enable 14nm Chip Production”. And this week, TSMC has certified ANSYS Power Integrity and Electromigration (EM) solutions for 10nm FinFET process node. It’s amazing progress! Read the press release here.

ANSYS portfolio of products was showcased in the TSMC Technology Symposium held in San Jose, California on 7[SUP]th[/SUP] April, 2015. ANSYS’ RedHawk and Totem were certified by TSMC for 10nm FinFET DRM and Spice models. These tools were certified to provide solutions for static and dynamic voltage drop analysis and advanced signal and power EM verification that are required for ultra-low power and high performance SoC designs at 10nm for mobile, computing and networking applications.

At 10nm process node the devices are left with extremely low noise and reliability margins and FinFET’s structure is typically prone to increasing self-heat.

As shown in the picture, heating happens at the device (FEOL) as well as interconnect (BEOL) levels and hence both need to be considered. At sub-28nm process nodes, as we go down the node, the current density increases and makes the device increasingly vulnerable to EM. In a FinFET the current density can be generally 25% more than that in a planar transistor. Also the narrow 3D fin structure and the lower thermal conductivity of the SiO2 dominated substrate can cause local heat to get trapped.

With such tough challenges and extremely tight window of accuracy, it’s critical to ensure power integrity across the chip, package and board. And an accurate EM analysis at all levels is a must. There are some key critical enhancements added into ANSYS tools to provide the kind of accuracy and versatility needed for the EM, power integrity and reliability solution at 10nm.

To support multi-patterning technology, ANSYS solution provides color-aware resistance extraction and EM analysis capability. And there is a complete system-to-block level EM analysis flow with color-aware metal-fill capability that delivers higher yield and performance along with accurate EM analysis.

To address the increasing difference in the current between signal and power rails, ANSYS solution provides various approaches to apply appropriate EM rating factors for signal and power analysis. At 10nm, there can be measurement issue between the drawn trapezoidal shape and the physical implementation of a wire in silicon. ANSYS provides a comprehensive wire width adjustment solution to compensate for the difference that leads to more accurate results in the EM analysis.

ANSYS solution provides thermal-aware EM methodology. Above diagram shows the Thermal-aware EM Flow at TSMC for the 16nm FF+ process node that uses RedHawk, Totem and Sentinel-TI. RedHawk/Totem along with Sentinel-TI uses foundry data to accurately compute the self-heat temperature on an IP or SoC. The temperature can be analyzed at instance or metal layer basis. A Chip Thermal Model (CTM) is generated for back-annotation into RedHawk or Totem. This methodology helps avoiding over-heating of the device, thus increasing its lifetime and reliability.

With increasing complexity and sizes of SoCs at lower nodes, challenge of managing capacity, performance, and parasitic effects also increases. RedHawk/Totem uses a novel Distributed Machine Processing (DMP) capability that can handle large power delivery network (PDN) and perform flat simulation with high performance and small memory footprint. RedHawk-CPA provides chip-package co-simulation and co-analysis within a unified environment that ensures integrity of power delivery on the complete chip and takes into account the impact of package parasitic, thus avoiding undesired hotspots.

The overall comprehensive solution provided by ANSYS delivers highly accurate results as needed at 10nm FinFET node and also reduces design turnaround time through its innovative methodology, algorithms, and multi-physics simulations. The Power Integrity and EM solutions are ready for 10nm FinFET based early design start. On earlier technologies, ANSYS solution for SoC/IP power integrity, noise, and reliability sign-off has been proven on thousands of successful silicon wins.

April 9, 2015June 14, 2019

Starvision Pro: Lattice Semiconductor’s Experience

Starvision Pro: Lattice Semiconductor’s Experience
by Paul McLellan on 04-09-2015 at 7:00 am
Categories: Concept Engineering, EDA

During SNUG I took the opportunity to chat to Choon-Hoe Yeoh of Lattice Semiconductor about how they use Concept Engineering’s Starvision Pro product. He is the senior director of EDA tools and methodologies there.

Lattice Semiconductor is a manufacturer of low-power, small-footprint, low-cost programmable logic devices. Earlier this month it closed an acquisition of Silicon Image, a leading provider of multimedia connectivity solutions and services for mobile, consumer electronics and PC markets based in Sunnyvale, CA.

One of their products is the world’s smallest, lowest power, most integrated, most flexible mobile FPGA. With up to 4,000 LUTs and key IP for IR, barcode, voice, USB-C, user ID, LEDs, pedometer, and more. Perfect for the IoT and mobile markets!

StarVision Pro provides engineers with the ability to quickly and easily understand and debug mixed-mode designs and to integrate IP building blocks into their complex SoCs and ICs. Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, parasitic) as well as with different design languages and netlist formats.

Choon is responsible for design enablement at Lattice, including tools, methods, flows, PDKs, license queuing and so on. Lattice has been using Starvision Pro for a couple of years. They use it primarily for better visualization of chip level design. These are difficult to work with in a “classical” schematic tool since the designs are a mixture of actual gate-level and transistor-level schematics along with Verilog. Starvision Pro helps to improve productivity at chip level design debugging as it gives the designers system-level visibility which is important since FPGA design is a mixture of full-custom and RTL with a number of different variants of the flow.

Choon expects to expand the use in the future, and is looking at various ways that different products and flows could benefit.

Here in a single table is a concise summary of the features of Starvision Pro.

Lattice Semiconductor’s website is here. Concept Engineering’s page on Starvision Pro is here.

April 8, 2015

Archives from TI’s Baseband Glory – Part 1

Archives from TI’s Baseband Glory – Part 1
by Majeed Ahmad on 04-08-2015 at 7:30 pm
Categories: Arm, EDA, Mobile

In 1992, nearly two years after Britain’s Acorn Computers joined hands with Apple and VLSI to create Advanced RISC Machines or ARM, the semiconductor upstart landed its first major licensing breakthrough. In retrospect, while Apple’s Newton handheld computer had played a key role in creating the ARM venture, Texas Instruments Inc. was the most important early licensee that ARM had snagged.

ARM7 was integrated with TI’s DSP for baseband in Nokia phones

ARM’s founding CEO Robin Saxby later acknowledged that it was really the TI’s license that put ARM on the semiconductor map. TI, the sixth largest chipmaker in the world at that time, was a licensing coup for ARM because it offered an entree into the vast market for embedded control in the automotive industry.

Meanwhile, TI in Europe, who was working closely with Nokia for developing mobile phone chips, saw potential in ARM’s CPU-light product and brought Nokia into the ARM fold. The collaboration between ARM, Nokia and TI eventually led to Thumb-capable ARM7TDMI chip that Nokia used in its 6110 GSM phone introduced in 1994. Nokia wasn’t happy with the code density of the ARM7 processor, so ARM developed Thumb as an alternative instruction set which addressed the code density issue.

Robin Saxby: TI license was a powerful endorsement for ARM technology

The Thumb chip provided low power in a 16-bit architecture that took less space, memory, and power than competing core architectures. The ARM processor core was integrated with TI’s DSP in a baseband solution and was used in Nokia’s 6110 handset. The 6110 mobile phone became hugely successful at the time of GSM’s early take-off. The 6110 design-win gave TI the ability to push its chips into other mobile phones, and that gave ARM the market backing for its processor architecture.

Nokia’s 6110 handset provided enormous boost to ARM and TI

By the late 1990s, ARM had a share of nearly 97 percent in that rapidly growing market. The only two major cellular phone makers that didn’t use ARM cores were Hitachi and Siemens. Eventually, TI became not only ARM’s single largest licensee, but also went on to gain 60 percent market share in mobile phone chips. TI had just about sewn up the mobile handset silicon market by devoting vast engineering resources to Nokia for the development of platforms based on its chips.

It was during this time that TI began to focus on its DSP technology for other electronic products such as modems, PC peripherals and television sets. In 1994, for instance, TI launched a multimedia processor, the first single-chip solution that combined parallel DSP and RISC parts. The confidence that came with the baseband triumph was now branching into other semiconductor markets.

Majeed Ahmad is the author of Nokia’s Smartphone Problem: The End of an Icon?

April 8, 2015

New oscillator for low-power implantable transceivers

New oscillator for low-power implantable transceivers
by admin on 04-08-2015 at 10:00 am
Categories: IoT

Due to the limitations of implanting a device in the human body, the devices have limited power storage. Using CMOS technology, different circuits and systems design techniques have to be in place to achieve an energy efficient communication interface. This CMOS technology, created by Arash Moradi and Mohamad Sawan, helps to get rid of most of the external bulky components. Two of the main challenges the creators faced were to reduce the size and power consumption of the transmitter front-end to maintain real-time, long-term data transmission. The main issues of this article are the size and battery power of a voltage controlled oscillator as a medical implant. This voltage controlled oscillator was created to provide frequency deviation of frequency-shift-keying modulation in medically implanted RF transceivers. Crystal-less and inductor-less voltage controlled oscillators will help implement this type of device as an implantable and create VLSI systems with different frequency ranges.

The designers’ voltage controlled oscillator is a low-power differential rail-to-rail quadrature voltage controlled oscillator that is composed of a 2-stage quadrature oscillator. Each stage of the oscillator acts similar to a bi-stable circuit triggered by the output of the other one. No external clock signal is required and the device only needs a small silicon area and a low current consumption. As to not affect the oscillation, the startup circuit is designed to initiate the oscillation and is then automatically disconnected from the oscillator’s circuit. The designers claim that this is the first design of a fully-integrated low-power quadrature voltage controlled oscillator that is capable of providing rail-to-rail, differential and quadrature version of a variable-frequency signal, simultaneously.

Challenges, such as determining the parasitic capacitance and resistance within the prototype, played major roles in changing the behavior of the expected output signals. Producing the input signals, including the enabling or disabling of different blocks, with proper falling and rising time and providing the power supply will have to be properly planned. The designers may add more control signals in future prototypes so that it can be used for several communication applications with different frequency and current ranges, such as providing the optimum carrier frequency for wireless power transfer using inductive links.

The designer’s results and design used TSMC 90nm CMOS technology. The value of the current consumption for the transmitter was mainly due to the output driver including a power amplifier. The poly phase filter stage and modulation need no DC current consumption. A low power budget was needed for the whole transmitter to provide a data rate of 20Mb/s which is better than other similar circuits. The accomplished power amplifier was not fully optimized and there was a tradeoff between power consumption and provided output voltage amplitude. The proposed circuits, which were implemented in 90nm CMOS technology, enhance the data rate capability and power efficiency of wireless implantable devices and improve the figure of merit comparing with previously published works.

In implantable medical devices, wireless link technology is increasing. However, wireless connections may consume 90% of a device’s total power. Development within CMOS technology can provide a potentially better circuit that may consume less power due to having to implement less components inside of the device. An optimum solution would be to have an implantable medical device in which the device consumed as minimum amounts of power as possible.

Consuming small amounts of power could lead to not having to replace the device as much or undergoing invasive procedures in order to charge the battery of the device. According to the researchers in a paper published for IEEE, the quadrature voltage controlled oscillator operates at 915 MHz and consumes 580 uA from a 1V power supply while showing good phase noise immunity and a fast settling time. There are many positives to the proposed design of this low power oscillator. All over the globe, patients with an implantable medical device could go potentially years without having to undergo surgery to replace their device or to have their device recharged. Along with gathering data on medical patients, the device could also be used to monitor the habits of animals. The animals could be monitored for much longer periods of time with a device that would be less likely to be unattached due to fighting or swimming. If possible, one solution could be the usage of wireless charging in which the patient could charge their medical device without having to visit a doctor or hospital. Other solutions could include thermocoupling devices as well as kinetic battery chargers. The only problem with thermocoupling devices is their poor efficiency. The more intricate the device becomes, the more the medical costs of the device, surgeries, and replacements become, and more power will be consumed by the SOC. Thus, as the device becomes more complicated, thermocouple devices might not be the best solution. For the case of animals, a kinetic charger could be used. The difficulty with using a kinetic charger would be the use of a magnet which could interfere with the intended operation of the device.

Though there seem to be many benefits, it also comes with some disadvantages. This great device could not be used around the world due to the price of medical attention, such as the surgeries, that would be needed to replace or recharge the device. Along with price factors, the more intricate these devices become, the more issues that may arise. These issues would likely have to do with the rise and falling time of the device, the parasitic capacitances, and the delay times associated with the components of the device. The wireless transmitter and receiver would need to be implemented in such a way that it should not interfere with the human body or any other device a person typically uses, such as a phone or possibly a radio. Also, designers should be aware of potential issues such as interfering with radio and other types of waves in the case that a wireless charging device could be used. Using CMOS designs and tactics, these types of devices and components could be implemented using minimal power usage, minimal components, and minimally invasive procedures for implementation.

Article in question for reference: New oscillator for low-power implantable transcievers

By Tyler Bigham and Coleman Irby

The University of Mississippi Electrical Engineering Department introduced a Digital CMOS/VLSI Design course this semester. As part of this course, students researched a contemporary issue and wrote a blog article about their findings for presentation on SemiWiki. Your feedback is greatly appreciated.

April 8, 2015August 22, 2024

FinFET vs FDSOI – Which is the Right One for Your Design?

FinFET vs FDSOI – Which is the Right One for Your Design?
by Daniel Nenni on 04-08-2015 at 4:00 am
Categories: EDA, FD-SOI, FinFET, Foundries, GlobalFoundries, STMicroelectronics

As a professional conference goer I can see definite trends when it comes to topics and attendance. Thus far this year I have seen a double digit increase in attendance, which is great. The question is why? Why is the fabless semiconductor ecosystem leaving the safety of their cubicles and computer screens in droves to mingle amongst the masses? The answer I believe is that modern semiconductor design is moving faster than ever before and people are scrambling to keep up, absolutely.

When it comes to choosing a topic and organizing a session I have the advantage of SemiWiki analytics. I see what thousands of semiconductor people search for, read, and share, which is why the first session I did for EDPS was an introduction to FinFETs in 2013. Last year it was all about IP Integration issues and this year it is the design issues between FD-SOI and FinFET. Tom Dillinger of Oracle will keynote, below is the abstract and session summary. After the keynote there will be a panel discussion with Tom, Kelvin Low of Samsung Foundry, Boris Murmann of Stanford University, Jamie Schaeffer of GlobalFoundries, and Marco Brambilla of Synapse.

EDPS is more of a workshop than a regular conference. The advantage is that a workshop is smaller and more interactive. Not only do you get to see experts speak and interact with the audience, you get to have breakfast, lunch and dinner with them as well.

FinFET vs FDSOI – Which is the Right One for Your Design?
The emergence of multiple transistor technology options at today’s deep submicron process nodes introduces a variety of power, performance, and area tradeoffs. This session will start with an overview of the FinFET and Fully-Depleted Silicon-on-Insulator devices (FD-SOI, also known as Ultra-Thin Body SOI), in comparison to traditional bulk planar transistor technology. The session will then delve into a detailed discussion of the architectural and circuit implementation tradeoffs of these new offerings, to assist designers make the right choice for their target application.

This session will delve into the design tradeoffs associated with leading semiconductor manufacturing nodes, covering advanced bulk planar, Fully-Depleted SOI, and FinFET device options.

The kickoff presentation will establish a technical foundation for these processes, followed by a discussion of hands-on experiences from experts who are leading advanced chip designs and process implementations in these technologies. After the kickoff and brief presentations from the expert panel, attendees are encouraged to participate in a question-and-answer session, to explore specific process selection and implementation tradeoff decisions.

The kickoff will start with an introduction to bulk planar, FD-SOI, and FinFET devices – i.e., device cross-sections (and the associated parasitic elements); device fabrication options; and, sources of device variation. The compact models for these device types useful for circuit design and simulation will be reviewed. Advanced process technologies introduce additional device and circuit layout considerations – e.g., layout dependent effects, layout parasitic extraction (and parasitic reduction) around the device, and the importance and impact of lithographic uniformity in circuit layouts.

The kickoff will then move to circuit-level design considerations for library logic cells, for these different process options. Analog cells also have a key impact upon technology choice, and will be discussed as well (albeit briefly).

Finally, the kickoff will cover broader design methodology tradeoffs for these process options, specifically methods for making path-level and block-level power/performance optimizations. The design implementation methods for power, performance, and area (PPA) closure are key differentiating features of these technologies.

With this background, the expert panel will discuss some of their recent design and development experiences – choosing the optimum technology, making global and local implementation choices to meet PPA goals, and accommodating process technology variation in design closure.

April 7, 2015

TSMC Processes Galore

TSMC Processes Galore
by Paul McLellan on 04-07-2015 at 10:00 pm
Categories: Foundries, TSMC

Today was TSMC’s 2015 North American Technology Symposium. They talked about a lot of things but perhaps the most important was that they gave a lot of details of new processes, new fabs, and volume ramps.
Continue reading “TSMC Processes Galore”

April 7, 2015

US is the Ultimate Leader in Semiconductor Business

US is the Ultimate Leader in Semiconductor Business
by Pawan Fangaria on 04-07-2015 at 6:00 pm
Categories: EDA, Foundries, IP

Last year in November when I looked at the world’s top20 semiconductor companies with Samsungand TSMCbeing at the second and third rank respectively, first being Intel, I computed the sales numbers of the companies based on their countries and found that Taiwan and South Korea accounted for 34.5% of the total sales of the top20 companies. That provided a well founded perception that these countries in Asia were leading the semiconductor business. I blogged about it “Look Who is Leading The World Semiconductor Business” and received comments from the community that it’s no surprise, companies in South Korea and Taiwan have been leading it since long. Well, South Korea and Taiwan, in fact APAC region does lead in foundries. A blog on 300mm Fab Capacity provides actual data about that. However, look at the following bar chart from an IC Insights report.

The companies headquartered in US have the lion’s share of 63% sales in fabless IC, and that is going to further increase after completion of Qualcomm’sacquisition of CSR, the second largest fabless company in Europe and Intel’s acquisition of Lantiq, the third largest fabless company in Europe. Also US leads in IDMs with more than 50% market share. The total shown in the graph does not include foundry sales, so I’m not talking about that, because then TSMC can definitely change the equations. Bye the way, in this chart, Samsung’s sales from its Austin facility has been counted as sales from South Korean companies.

There are a couple of point to note here, South Korea has just half of US market share in IDMs, and Japan, Europe and Taiwan are nowhere near US market share in IDMs. China has negligible presence in IDM. Although Europe will have improved figures in IDMs after completion of NXP’sacquisition of Freescaleand Infineon’sacquisition of International Rectifier, it will still be much lower compared to US market share in IDMs. In case of fabless business, South Korea and Japan have negligible presence and others including Taiwan are much lower compared to US market share in fabless. Europe’s just 3% share in fabless market will further erode after CSR and Lantiq will start being counted as US headquartered companies.

Now let’s take a closer look at 300mm Fab Capacity blog. I am reproducing that bar chart here –

It’s apparent that based on headquarter location of companies, US is just next to South Korea in 300mm wafer capacity. There is a large difference between headquarter figure (28%) and fab location figure (15%) of US fabs. The reason is simple; keeping the fabs out of US locations provides significant cost advantage to US companies. Also South Korea and Taiwan definitely have significant cost advantage in this capital intensive foundry business.

One more indicator about US lead in R&D of semiconductors was mentioned in my earlier blog, “Who Leads Semiconductor Innovation”. In this it was clear that US semiconductor companies, led by Intel, spent the most on R&D activities for semiconductors. They also have largest R&D Expense / Sales ratios. That reminds me about one of our forum discussions in Semiwiki on patents and innovations. There, it was evident that sales are important and equally important are investments into R&D to further grow the sales; both need to complement each other. The US is doing well in that aspect. There are companies outside US as well which are doing well in these aspects. However in my view a cluster of such companies is in the US and that creates an innovative and developing environment there.

April 7, 2015

Breakfast was Fab: West Coast Wafers to Wall Street

Breakfast was Fab: West Coast Wafers to Wall Street
by Paul McLellan on 04-07-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

SEMI describes themselves as “the global industry association serving the manufacturing supply chain for the micro- and nano-electronics industries.” That is a pretty broad remit. One of the things that they do as a neutral party is produce the World Fab Forecast. This is actually a bottom-up database that tracks fabs as they are built, equipped, ramped to volume, upgraded and expanded and, eventually, closed. Of course this is of great interest to people selling the equipment and material required, but also it impacts the entire semiconductor ecosystem. This is especially true in the fabless/foundry ecosystem. If TSMC builds a 16FF+ Gigafab then Apple, Qualcomm, nVidia, Xilinx and lots of others are affected, not to mention Samsung, Global Foundries, UMC and Intel who compete with them.

Christian Dieseldorff maintains the database and also presented at the latest SEMI Silicon Valley SEMI Breakfast Meeting. The forecast covers 3 years of detailed information with a future forecast of 1½ years. To give an idea of how extensive the database is, it covers 1174 fabs, what are officially called “front-end facilities” to distinguish them from test, package and assembly and are nothing to do with FEOL or what we call front-end in EDA. They are owned by 500 companies. There are 58 future facilities starting high-volume manufacturing (HVM) in 2015 or later, with 218 facilities currently either in construction or equipping.

Another aspect to be tracked is consolidation. Recent events (many of which we have covered here at Semiwiki) affect 46 fabs from 4” to 12”. Here they are:

Fujitsu winds down chip production
Global Foundries “buys” IBM’s semiconductor business
Grace and Hua Hong merge
Cypress and Spansion merge
Infineon buys International Rectifier
Triquint and RFMD merge (Qorvo)
Freescale and NXP (will) merge

Where are all the big fabs? In 2015 there are 1999 fabs equipping with 16 of them investing over $800M including Samsung, SK Hynix, Sandisk/Toshiba, TSMC, Intel, GloFo and SMIC.

Fab equipment has been a rollercoaster. But actually as a rollercoaster it would be a bit boring since it is too predictable, two years up, followed by two years down. This has gone on every 4 years since 1999. But it looks like this year will be the second up year and, for the first time in living memory, 2016 should be an up year too.

One area where historically there has been overinvestment in fabs has been DRAM. In the last few years this has moderated resulting in DRAM prices firming (which is a large part of the recent growth in the overall semiconductor market). In fact there were 40 dedicated DRAM fabs in 2007 and now we are down to 15. But the capacity of new fabs is huge compared to the old, with the 5 new fabs this year adding over 30K wpm with the 10 closing dropping about the same amount.

One area with a big decline is not the number of fabs or capacity but the number of companies building fabs. In the 2004-7 era there were nearly 50 companies building fabs but in the 2014-16 era that is down to 13. Obviously this is largely due to fables (and fab-lite) but also consolidation and companies going out of business too.

One new phenomenon is the IoT market. As I have said before, this is primarily a market for old processes, and old processes typically run in old fabs which are mostly 8”. In fact in 2007 there were 200 8” fabs with a capacity of 5.7M wpm, which dropped to 183 by 2013 with a capacity drop of 11% to 5.1 wpm. However, capacity will increase 4% by 2018 to 5.4M wpm although the number of fabs will again drop to 180.

Bottom line is that fab expansion rates slowed to below 2% in 2012 and 2013. They should increase around 3% year on year from 2015 to 2018. This reflects growth of the overall semiconductor market of 9% in 2014, forecasts for 3-8% in 2015 and 3-9% in 2016.

April 6, 2015March 23, 2022

How Pebble Reinitiated the Inning for Smartwatch

How Pebble Reinitiated the Inning for Smartwatch
by Pawan Fangaria on 04-06-2015 at 7:00 pm
Categories: Mobile

The effort for adding phone function into watch had started much earlier in 1999 when several tech companies joined the crusade to enter the big watch market. Notable among them were Samsung, IBM, Microsoft, Fossiland Sony Ericsson. The effort lasted for about a decade before showing its signs of fatigue. Microsoft SPOT (Smart Personal Objects Technology) closed in 2 years after its launch in 2006. Sony Ericsson’s MBW series was a little known that contained a small OLED display and worked with Sony Ericsson phone via Bluetooth. It vibrated on an incoming call, displayed caller identity, and notified on new text messages. However it was priced very high to the tune of $400. Samsung tried its next version S9110 in 2009 which was thinnest of all other smartwatches at that time and had a touch screen, Bluetooth, email and MP3 support. However, these smartwatches couldn’t takeoff, mainly because of their bulkiness, frequent changing, extra service subscriptions in some cases, and so on. The companies started focusing on the flourishing smartphone market instead of investing into smartwatches.

Between all this scepticism over initiation of a new smartwatch market was this 22 years old engineering graduate in systems design, Eric Migicovsky quietly developing a smartwatch. The Allerta inPulsereleased in 2010 is not known to many of us. It was actually developed by Migicovsky and his team before he started Pebble Technology. The inPulse worked with BlackBerry smartphone at that time. This is the time Migicovsky groomed himself in real smartwatch technology and its requirements, but he was not so lucky in the first-time business. Every business has its own challenges. A large inventory of inPulse watches was ahead of their sale and couldn’t sell. He couldn’t get further funding after his initial fund from a venture capital firm, Y Combinator and a few angel investors. But these challenges also provided him good learning about future strategies to work upon.

Firm in his ideas about a smartwatch that will be appealing to people to have it on their wrists, this time Migicovsky initiated a kick-starter campaign in April, 2012 to crowd fund his project on Pebble smartwatch. It was like a pre-booking for the $150 smartwatch at discounted prices of $99 for first few hundred backers and then at $115. The campaign had an stellar success; within a month it raised more than $10 million, more than 100 times the initial target. This was the most successful crowd funding of that time that set this record with about 69 thousand people investing into the Pebble project. The Pebble smartwatch started shipping in early 2013 that reached one million in number by the end of 2014.

The hidden advantage which is apparent in this kind of funding is that you already have your customers, backers and well wishers lined up; the tall challenge here is to convince them into your project. You directly talk to your customers at first hand and build the strongest support group. Migicovsky was able to do that, he knew exactly what is needed for a smartwatch and created the much coveted, long awaited new smartwatch market. Interestingly, he used an army of about 70 bloggers for the campaign to reach to every single potential customer.

So, what were those specific features in Pebble that rejuvenated the fatigued smartwatch market and gave it a fresh breathe? Pebble created an entirely new market for smartwatches. One of the very important mantra Migicovsky used is to let the watch adopt people’s habits instead of asking them to adopt the watch. In his view the most important core functions for the watch were notifications and phone calls. He exactly deciphered this from the fact that people looked at their smartphones for messages and phone calls for about hundred times a day. What if they could do this just by looking at their wrist watches instead of lifting the phone every now and then? Again for this much favour done by a watch on a wrist, one shouldn’t be paying a hefty amount like $400. Another important clue Migicovsky took it that these watches shouldn’t trouble people to charge them every day or even worse, twice a day. A smartwatch should work like any other watch for long on a single charge. The battery in Pebble lasts for about seven days on a single charge.

The credit for the long battery life goes to e-paper display, the feature in operating system on Pebble that lets other apps run in the background, and no packing of stuff that are not meant for a watch. The advantage of e-paper display is that it can be perfectly viewed in the direct sun light. Pebble has sports activity tracking, fitness tracking features, other activity tracking like sleep or walk detection, calories etc., notifications for phone calls, text messages, emails, etc., remote control for smartphones (where one could dismiss any phone call or notification from the smartwatch), and so on without any burden on battery life. The sensors for these activity tracking are actually inside the watch which can work from wherever it is.

It’s a small size watch (1.26”) with ultra-low power transflective LCD, vibrator, magnetometer, accelerometer, and ambient light sensors. It’s versatile to connect with any iOS as well as Android device (including smartphones and tablets) using Bluetooth 2.1. In a later upgrade it supports BLE 4.0 as well. It’s waterproof and can be used by divers. The Pebble team used all the feedback received on inPulse to improve this blockbuster smartwatch called Pebble.

While Migicovsky primarily focused on the core functions of Pebble, he developed an SDK (Software Development Kit) called PebbleKit for app developers in the community who could use it as an open platform and develop innovative apps that could ease and automate several of our daily activities. This was another innovative idea of pooling innovations from the community which could go much beyond a single person’s imagination. Today, Pebble has built a large community of more than 25000 developers who have already built more than 6000 apps and watchfaces for Pebble appstore, and still continuing. Many companies including Mercedes-Benz, GoPro, iControl, and others also have joined the initiative. The idea from Mercedes-Benz includes an app which can make your wrist shake when it sees any obstruction on the road while driving. The PebbleKit provides a complete customizable wearable platform for the watch; the app store has a watchface generator where images can be uploaded to generate an specific watchface. Pebble team is also building an operating system, the platform designed specifically for wearables.

Pebble Steel with a thinner body, Corning Gorilla Glass, and tactile metal buttons was released last year at CES 2014. Pebble Time was announced this year in Feb, again through a kick-starter campaign which reached $14 million by the beginning of March setting another record while the campaign still continued. Pebble Time will have 64 color LCD, a microphone and a more ergonomic and thinner chassis. It includes a new interface designed around a timeline, similar to Google Now. Pebble Time is reported to be selling at $199.

Pebble Time Steel is another latest in Pebble smartwatches that is tipped to have room for a larger battery to last for 10 days. It’s the top model of Pebble in stainless steel which is yet to start shipping in second half of this year and is expected to be priced at $299.

Recently, along with Pebble Time Steel, Pebble team brought their open wearable platform to next level by announcing an open hardware platform for wearables, called “Smartstraps”. By using this platform, a developer can design and develop a new strap that can connect to a special port in the watch to add new features like heart rate monitor, extended battery life, GPS, and others, thus keeping the smartwatch in itself small and slim.

In August 2013, Eric Migicovsky, the founder of Pebble Technology was selected as one of the remarkable 35 innovators under 35 for all of his innovative work on smartwatches.