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Synopsys Earnings Call Q1 2015

Synopsys Earnings Call Q1 2015
by Paul McLellan on 02-20-2015 at 7:00 am

 Synopsys announced their results yesterday. Their 2014 already ended, this is the end of their fiscal first quarter. On the call were Aart, one of Synopsys’s two co-CEOs, the other being Chi-Foon Chan; and Trac Pham, the new CFO on his first earnings call.

Synopsys’s results were good. A quick look at the results. Revenue was $542M so comfortably above a $2B/year run-rate. Non-GAAP EPS was $0.80. They also raised future guidance. They see the environment as solid.

But as usual my interest is not so much short-term financial measures but discerning longer-term trends in things like process, foundry availability, sea-changes in EDA methodology and so forth.

“The number of active FinFET designs and tapeouts to date grew nearly 15% in just the last quarter, to almost 200. The breadth of our FinFET proven tools and IP gives us a notable competitive advantage, as evidenced by Synopsys being relied on for approximately 95% of these designs.”

I think “relied on” is just a wiggle word meaning that they used a lot of Synopsys tools, but since they probably also used Virtuoso and Calibre, I think Cadence and Mentor could say they were “relied on” too. Also, designs and tapeouts “to date” grew to 200, not just last quarter.

“We’ve taped out more than 30 FinFET chips.” So with the previous bullet, that means there are 170 FinFET designs in progress, around 30 of which started last quarter.

“We’re engaged in numerous 10 nanometer partnerships with early adopters”. “Through our TCAD technology, we’re already collaborating with silicon providers and research consortia such as imec on 5 nanometer and 7 nanometer.” One key question is whether FinFETs will work at 7nm or whether we will need to go to gate-all-round or some other technology.

“Our flagship VCS functional verification product is the primary simulator for 80% of advanced designs.”
That is a big percentage, given that both Cadence and Mentor also have credible offerings in the same space.

“Synopsys is the number one supplier of interface, analog, memory, and physical semiconductor IP.” In fact they are the #2 supplier of IP behind ARM.

 “Our HAPS FPGA-based prototyping solution does just that, and has proven itself in the marketplace. Q1 was its highest revenue quarter ever, and with more than 5,000 HAPS systems installed at customers today.”
Later Aart said that this was being driven by the needs of software development. “The challenge with that is of course that the software guys would like to start modeling and trying out their software before the chips are ready.”

There were a couple of questions about IC Compiler II which Aart characterized as growing market share. But Cadence also talked about digital design as an area where they were investing additional resources and also growing share. Aart said that some of this is just the Lake Wobegon effect “EDA is the industry where all the children are always above average, and all the share gains are above average.”

“The Coverity integration of infrastructure and sales has gone well, and our initial financial expectations are on track. We saw 32 new logos in the quarter, and executed an important agreement with a large, U.S. energy company.” Coverity is used for analysis of software especially in safety and security critical applications. Analysts reckon this area is growing at around 20% per year. In the questions Aart said they were on-track to be profitable in the second half of this year and over $100M in 2016.

“One customer accounted for over 10% of revenue”.
Everyone knows it is Intel. It is a big number since 10% revenue last quarter is over $54M.

 “We ended Q1 with approximately 9,300 employees, with more than one-third in lower-cost geographies.”So over 3100 employees in India, China and other similar countries. “You can see that the headcount did decrease from Q4 to Q1. A large portion of that was due to the voluntary retirement program and the small layoff we had, but also the delayed hiring.”

There is a lovely transcription error in one of the questions which talks about moving from the “plainer world to FinFETs”. I think I’m going to start calling “planar” transistors “plainer” from now on. Those FinFETs are so exciting for EDA.


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