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April 14, 2015

Grenoble Comes to San Francisco

Grenoble Comes to San Francisco
by Paul McLellan on 04-14-2015 at 7:00 am
Categories: Foundries, STMicroelectronics

The headquarters of ST Microelectronics is officially in Switzerland, but in many ways the center of gravity is in the Grenoble area. You may have heard of Crolles where ST does process development, manufacturing and more, which is about ten miles north-east of the city. As a result, along with the CEA-LETI and Grenoble Institute of Technology (INP) being there, an ecosystem of small and medium sized companies (SME) in electronics and semiconductor has grown up. These are pulled together into an umbrella organization called Minalogic that stands for Micro-Nanotechnologies et Logiciel Grenoble-Isère Compétitivité which is obviously in French but the only word that may not be obvious is “logiciel” which is the French for software.

With 300 members, the Minalogic competitive cluster in Grenoble brings together major corporations, small and mid-sized businesses, universities and research centers, government agencies and organizations and investors from the public and private sectors. Minalogic’s goal is to foster research-led innovation in intelligent miniaturized products and solutions for industry. Since the creation of Minalogic in 2005, 388 projects have been certified and financed for total funding of €765 million (local and national funding), with a total R&D budget of €2 billion.

Why am I telling you all this? Because Minalogic is coming to DAC. The president of Minalogic is Philippe Magarshack who has been in a number of positions at ST over the years driving their CAD and technology strategies. Currently he is formally EVP and CTO of embedded processing solutions.

The “excuse” for the party is the celebrate the launch of Silicon Impulse, the new design center hosted by CEA-LETI to facilitate access to advanced technologies such as FD-SOI. The focus is very much Internet of Things (IoT) as Leti’s CEO Marie-Noëlle Semeria said when it was announced:With Silicon Impulse’s one-stop-shop platform, 28nm FD-SOI heterogeneous, low-power design becomes a reality for the IoT community. Silicon Impulse helps Leti’s partners introduce innovative products that deliver optimal performance for these applications, and benefit from the most advanced technologies. The center combines Leti’s large portfolio of leading-edge technologies and novel low-power design solutions with a unique service for speeding integration of FD-SOI and other more advanced technologies (ReRAM, MEMS, 3DVLSI, Silicon Photonics), enabling heterogeneous low-power co-integration.

The EDA Showcase France will be held at the W Hotel at 4pm on Monday 8th June. That is just across the street from the Moscone Center where you will probably already be. You will be able to meet many of the Grenoble companies since they are exhibiting at DAC: Asygn, Defacto Technologies, Docea Power, Edxact, Infiniscale, IROCtech, Magilem, Xyalis.

There will be an introductory speech by Philippe, a presentation by Jan Rabaey of UC Berkeley, the Berkeley Wireless Research Center, and more, on Design Trends and EDA Challenges from Connected Objects to Cloud Computing, followed by a networking reception until 6pm.

So save the date. And if you decide to go then there will be an opportunity to RSVP nearer the time. The Minalogic website is here (in English as well as French).

April 13, 2015June 14, 2019

Advances in Nanometer Analog and Mixed Signal Design!

Mentor’s annual user group meeting at the Doubletree Hotel in San Jose, CA is coming up on Tuesday, April 21[SUP]st[/SUP]. This complementary event provides a unique opportunity to share design techniques and exchange ideas with other users and experts in the design community. As you may have read I am the star of the show; moderating a panel on The Changing Foundry Landscape: Trends and Challenges. But there are some other events there that should be of interest. And did I mention this is a complementary event with complementary food and complementary drink? The Doubletree puts out a nice spread, absolutely.

Featured Sessions – Analog/Mixed-Signal (AMS) Verification Track

Advances in Nanometer Analog/RF/Mixed-Signal Verification
Presented by: Ravi Subramanian Ph.D., General Manager – AMS Verification, Mentor Graphics
The analog, mixed-signal, and RF (AMS/RF) content of semiconductors is growing faster than any time in history, and is at the center of the semiconductor industry’s next major cycle. This wave is largely being driven by the rise of nanometer mixed-signal application specific standard products (ASSPs) targeted at new consumer, mobile, automotive, IoT, and datacenter applications. Performance targets for PLLs, ADCs, I/O circuits, PHY transceivers, image sensors, and embedded memories are becoming more stringent in the presence of higher device noise, lower supply voltages, less predictable process corners, and ever-increasing parasitics. This talk introducesimportant proven new approaches that have been successfully deployed in leading design teams to help analyze a variety of physical and electrical effects- spanning parasitics, coupling, noise, distortion, variability, power etc. – via innovative circuit analysis techniques. Specific case studies will be shown to illustrate the approaches used to target specific problems, and the underlying technology to help achieve this success.

Remember, Ravi was CEO of Berkeley Design Automation when they were acquired by Mentor. Ravi is very approachable and you will not meet another semiconductor executive with more hours logged in front of customers and partners. I worked closely with Ravi managing the strategic foundry relationships for BDA up until the acquisition so yes I know this by experience.

Device Noise Analysis of Precision Analog Circuits with the Analog FastSPICE Platform
Presented by: Dr. Boris Murmann, Associate Professor, Stanford University
Device noise, including thermal and flicker noise, are significant limiters on the performance of precision analog circuits and in particular in switched-capacitor circuits found in CMOS mixed-signal ICs. This paper reviews design challenges with these circuits from a theoretical perspective and provides best practices and simulation examples using the Mentor Analog FastSPICE (AFS) Platform. AFS delivers foundry-certified SPICE accuracy with industry-leading performance and full-spectrum device noise analysis. Circuits discussed range from track-and-hold circuits, to integrators, to SC delta-sigma ADCs.

I have worked with Boris before and will see him again at the EDPS Workshop panel I’m chairing next week: FinFET vs FDSOI – Which is the Right One for Your Design? It is all about WHO you know in this industry and you should definitely get to know Boris.

Design and Circuit Verification Challenges of Inter-Die Interfaces for 2.5D/3D IC Architectures
Presented by: Miguel Miranda Corbalan Ph.D., Staff Engineer, Qualcomm
One of the key challenges in 2.5D/3D IC architectures is the high-speed I/O interface between multiple dies/tiers. The design and characterization of these interfaces have significant circuit verification accuracy and performance requirement in order to achieve data rate and signal integrity specifications on par with single die SoC implementations. Challenges over and above single die implementations include power and signal integrity control over off-die interconnect structures. This paper describes the nanometer circuit verification requirements for power and signal integrity verification of a high-speed two die system. We present results from the methodology deployed at Qualcomm® using the Analog FastSPICE™ Platform from Mentor Graphics®. This methodology resulted in SPICE accurate simulation results, validated versus silicon measurements, with 4x speed-up compared to a traditional multi-threaded SPICE simulator enabling the successful verification and optimization of the high-speed I/O architecture.

I have not met Miguel but we are connected on LinkedIn so he has that going for him.

Verification of Mixed-Signal Interaction of Analog-Centric ICs
Presented by: Senthil Vinayagam, Principal Design Engineer, Cobham Semiconductor Solutions
Analog-Centric ICs used in automotive, aerospace, defense, and medical applications have become more and more mixed-signal designs with analog functions strongly coupled with complex digital control logic. The interaction between analog and digital blocks in these ICs can include feedback loops that pose a significant verification challenge. Traditional methodologies, verifying separately the functionality of the analog and digital blocks, is no longer sufficient and may leave hidden-bugs in the IC undetected, resulting in silicon re-spins. This presentation describes the verification of an ADC, designed for high-reliability telecommunication and imaging applications, using the Eldo circuit simulator and Questa ADMS mixed-signal simulator from Mentor Graphics.

I do not know Senthil nor are we LinkedIn but you can count me in on anything automotive or medical.

Featured Keynotes

“Secure Silicon: Enabler for the Internet of Things”

Presented by: Wally Rhines, Chairman & CEO, Mentor Graphics

“Mega Trends Driving Architectures of Mobile Computing and IoT devices”

Presented by: Karim Arabi, VP of Engineering, Qualcomm

View AgendaandRegister Today!

April 13, 2015

Silicon Valley, It’s About Culture

Silicon Valley, It’s About Culture
by Arthur Hanson on 04-13-2015 at 4:00 pm
Categories: General

Spreading the culture of Silicon Valley is the best way to take the US and the world to a better place. This culture is already spreading, but many organizations and especially governments are doing everything possible to hold on to the past to the detriment of all. Silicon Valley/US businesses have made the strongest statement that can be made by keeping and investing money overseas ($2.1 Trillion). This is the ultimate indictment of a government that displays a gross contempt as steward of the people’s money and resources. It is not only taxes, but regulations and laws that act as taxes that are becoming a detriment to the lead Silicon Valley has given the US.

Silicon Valley embraces the best and fastest way of moving ahead and improving our lives with the least downside of any other competing cultures. The points below are the basic framework that makes Silicon Valley and the tech sector tick. It isn’t just about silicon, it’s about the business and social process that has extended its reach into every corner of our society.

Efficiency is the number one factor driving our tech sector. Less power, materials, space, waste, cost, time and especially less holding on to the past. Automation of everything from design to manufacturing takes this a step further. Delivering more is the next factor: More performance, functions, intuitiveness, migration paths and above all better results.

What makes much of this possible is more acceptance of failure as when venture capital firms are willing to accept an eighty plus percent failure rate. It is the ability of Silicon Valley to manage and work with failure in a way that creates some of the greatest displays of the human spirit to reach even higher each time they exercise it. This allows more dreams to be put into action and as a result far more dreams become reality. This culture has taken systems that were large, expensive and limited to powerful, inexpensive commodities that fit in the palm of our hand.

The Silicon Valley culture of labor flexibility, transparency, allowing failure, ever increasing performance at ever lower cost at an accelerating rate now needs to be taken to government if the US and many other countries are to survive and prosper in a world with ever increasing challenges. We can no longer afford a government that literally becomes more wasteful and failure oriented. Almost iron clad security for employees and departments combined with a lack of transparency has led to increasing waste, inefficiency, failure and sometimes, sadly, even outright fraud. Bureaucracy in many cases has increasingly become more about survival and growth than results. It’s time to demand value and results by having our government adopt the Silicon Valley culture of accelerating value and results at ever lower costs.

Transparency is the foundation of integrity, honesty and fairness and no tool empowers this like the net, even when the government has made every effort to hide its actions from the people. Our government’s failure has led to the world’s most expensive medical, education, military, and legal system with as many people in prison as China and Russia combined. We can’t be that evil can we?

The top companies in Silicon Valley have made the most important vote of and all and that’s with their money. No business person would ever want to give money to an organization that wastes eighty percent of it. They fully know this is a detriment to the health of society and much of the accelerating government spending and waste is actually detrimental to society. The government’s answer to almost any problem is to throw money at it even as their actions cause the problem to go from bad to worse.

It’s no wonder Silicon Valley doesn’t want to feed this government culture that is becoming more and more about failure, waste, inefficiency and most sadly of all, outright corruption. No system is perfect, but our government has been in a state of decline for years.

The Silicon Valley culture is by far its most important product and it is far too important to mankind to leave its spread to chance. Only rarely is the government able to manage failure in a positive manner and this is the most valuable process the government should learn from Silicon Valley. The greatest document ever written is our Constitution and Silicon Valley is our greatest hope to embody the ultimate potential of the human spirit. US businesses have made a 2.1 trillion dollar vote for what the best and brightest think our government should do. This is not only about money, but lives and bringing out the very best in our people. It’s not about taxes, it’s about value and a government that isn’t delivering. At one time our government served the people, it’s time for the government to again serve the people and not itself. It’s a simple decision between the culture of Washington and the culture of Silicon Valley.

I feel these links should be a reference of what’s possible, just one of many solutions and what our true debt actually is.

http://www.forbes.com/sites/johngoodman/2015/03/31/singapore-a-fascinating-alternative-to-the-welfare-state/2/

reference link http://www.usdebtclock.org/

April 13, 2015

Silicon Catalyst’s Launch Party at Avaya Stadium

Silicon Catalyst’s Launch Party at Avaya Stadium
by Paul McLellan on 04-13-2015 at 7:00 am
Categories: Events

There is a new stadium in town. No, not Levi’s Stadium where the 49ers play, that one is already a year old. There is Avaya Stadium over near San Jose airport. 1123 Coleman Avenue if you want to be precise. This is a purpose-built soccer stadium where the San Jose Earthquakes play. Their season just started in February.

But on Thursday April 30th it is a different type of event: the Silicon Sunrise event for startups, hosted by Silicon Catalyst, with assistance from Alix Partners, JBK, Lonergan Partners and the Global Semiconductor Alliance (GSA). So if you have anything to do with silicon, which I’m sure you do, then come along.

The evening lasts from 5-8pm and there will be brief presentation by Silicon Catalyst at 6.15pm. It will actually take place in the bar, which is the largest outdoor bar in North America and has 45 different beers on tap. You can also tour the brand new stadium. Silicon Catalyst are expecting several hundred people to be there so it will also be a great networking event.

So who are Silicon Catalyst? They are an incubator for silicon-based hardware companies. There are many incubation programs for software companies, maybe two or three thousand around the world today. But really, all it takes for software incubators is a small space, and internet access and sometimes some good advice. The entrepreneurs provide the rest. It is not so easy for startup hardware companies. They need design tools. Manufacturing. IP. This is where Silicon Catalyst comes in.

Their website goes into more detail:Incubation in Silicon Catalyst lasts up to 24 months. We provide EDA tools, and IP when you start out. Our industry partners and mentors provide insight into your future markets, and will hopefully become your customers or acquirers. We provide PDK access and shuttle runs when you’re ready. And when you get those first chips back, you’ll find yourself in a fully equipped test lab. All of these services are coming from global technology leaders in our industry. We’ll do the rest too – if you need space, we have it in Silicon Valley. If you are located elsewhere, that it OK and you can still send staff temporarily or permanently to take advantage of the networks that make Silicon Valley what it is. And everybody likes a graduation party. Yours will be different, though. You’ll already know your customers and potential acquirers, and you’ll have plenty of opportunity to meet with future investors along the way. In exchange for the effort, resources, and dedication, Silicon Catalyst receives common stock equity in each admitted startup. We believe common equity, rather than preferred, aligns us quite well with the interests of entrepreneurs. We’re your partner, and we’re on a adventurous journey together.

Silicon Catalyst have put together an ecosystem of partners to support the customers in the program. For example, Synopsys is donating free design tools, as is Keysight EEsof (was part of Agilent), and TSMC will provide free prototype shuttles. When has that ever happened before? They will announce some new partners at the event too.

If you are a starting a company in this area, here is how it works. Silicon Catalyst is focused on seed stage high technology companies developing intellectual property as a product, or complete solutions based on silicon. You must be building a strong team, proprietary technology, and pursuing real markets. Silicon Catalyst will invest up to $500K and help you secure other funding opportunities, but they often work with VC, strategic investors, and angel groups to add to this. Their industry partners also have the option to negotiate with you to invest initially or as you progress towards working prototypes and application demonstrations.

There is an online application process at the Silicon Catalyst website, but the easiest way to find out more this month is to come along to Silicon Sunrise and talk to them informally over a beer (or 45). If you are going to come then please RSVP here.

April 12, 2015

Beyond CMOS: Three Industry Teams Aim at Next Generation of High-performance Computing

Beyond CMOS: Three Industry Teams Aim at Next Generation of High-performance Computing
by admin on 04-12-2015 at 10:00 pm
Categories: EDA

Given the current limitations with CMOS designs, such as low temperature thresholds and efficiency in power consumption, there is a vast need to expand into superconducting computers in order to manage consumers’ need for power and performance. Although supercomputers require extremely low temperatures, they are capable of considerably higher Floating Point Operations per Second (FLOPS) with similar power requirements. The current goal within superconductive computing is to reach an exaFLOPS, however petaFLOPS are the best presently attainable. In order to keep the superconductive metal oxides running at optimal temperatures, cryogenics were introduced.

IARPA has contracted IBM, Raytheon-BBN and Northrop Grumman to develop a small, yet scalable, superconducting computer in the cryogenic computing complexity (C3) program in order to expand the current capacities of high performance computing focusing on cryogenic memory and logic, communications, and systems (Keller, 2014).

Operating electronics at cryogenic temperature improves their performance, as well as lowering noise, allowing them to run at higher speeds, and increases efficiency (Kirschman, 2009). In superconducting computers, the use of super-cooled copper wire has the ability to allow current flow almost indefinitely. Therefore, the switching voltage is significantly reduced (Pop, 2014). The threshold voltage is the minimum gate source voltage that is needed to create a conducting path between the source and drain terminals. Superconducting computers operating at low temperatures require significantly lower threshold voltage. If the design begins to heat up, the supply voltage will not reach threshold voltage which results in sub-threshold leakage. In a device, when high temperatures are reached, leakage in p–n junctions become excessive which may render the device useless (Krischman, 2003).

Reducing the threshold voltage also reduces the heat of resistivity and capacitance which allows for smaller designs without the risk of leakage. Thus, engineers introduced the idea of cryogenic memory. In the beginning stage of the C3 program, the three teams will develop components for the memory and subsystems (Keller, 2014). Cryogenic memory is still in its infancy; however, this program is designed to flesh out its varying possibilities for high performance computing. While not much is currently known, cryogenic memory allows for memory and caches capable of supporting the processing power by the CPU of a superconducting computer (Anthony, 2014). With the use of recent ideas of energy efficient cryogenic memory and superconducting logic without static dissipation, the teams will use these ideas to meet the energy demands of today’s high-performance computers (Keller, 2014).

Liquid nitrogen, as a means of cooling both components and memory, is most readily available and is capable of temperatures below -196 C; however, it is not quite cold enough to reduce resistivity to zero (Kross). While liquid nitrogen is effective, there are other alternate sources for cooling. Liquid helium offers the coldest but is finite and not as abundant as nitrogen. Liquid hydrogen can also reach colder temperatures than liquid nitrogen; however, it is combustible at one thousand and sixty five degree Fahrenheit (NOAA). With these draw backs, liquid nitrogen proves to be the cheapest and easiest to obtain material to cool these super computers (Kross). Nonetheless, to progress further there needs to be some better way to cool superconducting metals more efficiently without risking an explosion.

Apart from expanding cryogenic memory, the second main focus of this program is the logic, communications, and systems desired to build superconducting logic circuits that demonstrate the potential of the technology for high-performance computing (Keller, 2014).

As designs are getting smaller the supply voltage was lowered in order to reduce electric fields within the design (Stockinger, 2001). Reducing electric fields mitigates the impact of wires in close proximity. Compared to semiconducting computers, such as CMOS designs, getting temperatures low enough to reduce resistivity would also cause the design to break down (Krischman, 2003). One reason for using Silicon is because of its durability compared to other semiconductors. For example, compared to Germanium, Silicon is used more in electronics because it can withstand higher temperatures (GSU, 2000). However, as temperatures decrease towards approximately 40 K for Silicon, an effect called freeze-out begins to occur. Freeze-out is where dopants are not sufficiently ionized which causes a defined lack of carriers. Dopants usually require some thermal energy in order to ionize and produce carriers in semiconductors; therefore, significantly cooling the superconductive metal oxides becomes the major challenge (Krishcman, 2003).

Electronics has come a long way since the first computers, but we still have not met our goals yet. Right now engineers are trying to achieve speeds that process at the rate of the human brain. Without proper cooling methods and power distribution, achieving a supercomputer of this caliber will be difficult.

By Aaron Carnahan and Thomas Garner

The University of Mississippi Electrical Engineering Department introduced a Digital CMOS/VLSI Design course this semester. As part of this course, students researched a contemporary issue and wrote a blog article about their findings for presentation on SemiWiki. Your feedback is greatly appreciated.

References:
Georgia State University. (2000). Silicon and Germanium. Retrieved from http://hyperphysics.phy-astr.gsu.edu/hbase/solids/sili.html

Kirschman, R. K. (2003). Extreme Temperature Electronics. Retrieved from http://www.extremetemperatureelectronics.com/

Pop, Sebastian. (2014). Cryogenic Memory and Superconductors Allow Supercomputer to Reach 1 Exaflop. Retrieved from http://news.softpedia.com/news/Mysterious-Supercomputer-Will-Use- Cryogenic-Memory-and-Superconductors-to-Reach-1-Exaflop-466602.shtml

Kross, Brian. Is there anything colder than liquid nitrogen?. Retrieved From http://education.jlab.org/qa/liquidnitrogen_02.html

Keller, John. (2014). Beyond CMOS: three industry teams aim at next generation of high- performance computing (HPC). Retrieved from http://www.militaryaerospace.com/ articles/2014/12/iarpa-c3-contracts.html
Kirschman, Randall. (2009). Cryogenic Electronics. Retrieved from http://www.cryogenicsociety.org/resources/cryo_central/cryogenic_electronics/

NOAA. HYDROGEN, REFRIGERATED LIQUID (CRYOGENIC LIQUID). Retrieved from http://cameochemicals.noaa.gov/chemical/3606

Stockinger, Michael. (2001). 2.1 Subthreshold Leakage. Retrieved from http://www.iue.tuwien.ac.at/phd/stockinger/node13.html

April 12, 2015

Safety Dominates Agenda in DAC’s Automotive Track

Safety Dominates Agenda in DAC’s Automotive Track
by Majeed Ahmad on 04-12-2015 at 4:00 pm
Categories: EDA, Events

The connected car movement is in full bloom, making headlines in the trade media on how the cutting-edge electronics will transform the twenty-first century driving experience. However, a closer look at the Internet of cars juggernaut shows that safety and security of the networked vehicle are still a major stumbling block.

Design Automation Conference (DAC) — June 7-11, 2015

The Automotive Track at the upcoming Design Automation Conference (DAC) in San Francisco to be held on June 7-11, 2015 just affirms how crucial safety and security are going to be in the connected automotive platforms. Another prominent highlight of the DAC program for automotive seems that it’s evenly divided between hardware and software aspects of car safety and security.

For instance, Jeffrey Massimilla, Chief of Cybersecurity at GM, is going to talk about cyber threats to connected cars. He will also join a technology chat along with Craig Smith, the author of Car Hacker’s Manual, and John McElroy, the host of Autoline Daily, the first webcast of automotive industry news and analysis. The session will provide a detailed treatment of how connectivity features like Bluetooth, GPS, LTE and Wi-Fi create entry points for hackers.

John McElroy will host a chat on connected car technologies

Jeffrey Owens, CTO of Delphi Automotive, will elaborate on how electronics and design automation are playing a critical role in shaping the future of automotive in another keynote titled as “The Design of Innovation That Drives Tomorrow.”

Next, DAC’s Automotive Track brings ISO 26262 certification to the technology limelight; a whole session is dedicated to the nitty and gritty of robust chip solutions for connected vehicles. Maik Herzog of Infineon Technologies AG will be the keynote speaker at this session about the physical design of automotive ICs, which will also encompass advanced verification tools for the brave new world of ISO 26262.

Infineon’s EDA expert Maik Herzog will talk about the brave new world of ISO 26262

There are going to be three conference sessions. The first one is about modeling, simulation and testing in automotive embedded systems. The session will feature three talks from Infineon’s Moomen Chaari, Kenji Nishimiya of Honda R&D and Armin Wasicek from University of California at Berkeley.

The second conference session is about energy efficient, safe and secure automotive software and systems. The session features six speakers and 21 authors, and will present new results on embedded automotive systems, architectures and algorithms. For instance, there will be a talk about a novel algorithm related to heating, ventilation and air conditioning (HVAC) systems for improving the energy management of electric vehicles.

The third and final session will cover the different facets of automotive embedded software. Cars have now several millions of lines of software code that run on a highly distributed architecture consisting of as many as 100 electronic control units (ECUs) connected by a heterogeneous communication subsystem consisting of CAN, FlexRay and Ethernet among others. The session will discuss various aspects of automotive software—model-based design, component integration and timing analysis.

Majeed Ahmad is former Editor-in-Chief of EE Times Asia and author of six books about wireless and smartphones. His latest book The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future is about the Internet of Things and connected wearable devices.

April 12, 2015

Sidense NVM Scores Qualification on GLOBALFOUNDRIES 28nm SLP and HPP

Sidense NVM Scores Qualification on GLOBALFOUNDRIES 28nm SLP and HPP
by Tom Simon on 04-12-2015 at 7:00 am
Categories: EDA, General, Sidense

A tremendous number of chips being designed for today’s products require some sort of onboard data storage. The size of these needs range from a handful of bytes, for trim and calibration storage, to something much more substantial like boot code storage. In both of these examples the storage ideally should be nonvolatile, with the option of writing during test and calibration, and possibly several more times over the life of the product. Furthermore, this capability should come with no additional process changes such as special layers or masks.

Design teams have several choices for their on-chip storage requirements. The simplest is mask ROM, but it sacrifices several of the useful traits called for above. First off, it must be made part of the mask when the chip is designed. This limits its use for calibration, unique ID’s or for microcode that might require updates. On the plus side, its useful life is extremely long, eliminating concerns about reliability.

At the other end of the spectrum is NAND flash memory. It often gets ruled out for on-chip uses firstly because it requires modifications to the process and adds additional masks. Also because its ability to retain data relies on storage of a charge in a floating gate, it is prone to errors after repeated writing or even reading. Therefore, for applications that require high reliability NAND flash memory can be a concern.

Because of these and other reasons another type of memory is used for frequently for on-chip storage. One time programmable (OTP) nonvolatile memory (NVM) offers many advantages for storing trim and calibration data, unique hardware addresses, encryption keys, and microcode. By using antifuse technology that selectively breaks down gate oxide, it avoids the potential localized physical damage issues that come from ‘blowing’ fuses in conventional fuse technology. They have fast read times that can make them suitable for code execution use. And, the available storage can be managed to provide the functionality of “few times programmable”. Of course they cannot compete with the re-write levels of NAND flash.

Even though OTP NVM uses conventional CMOS process layers and masks, it needs to be qualified for a given process to ensure the antifuse devices work with during the program and read operations.Sidense, a leading supplier of OTP NVM, has just announced that their SHF family is now qualified on GLOBALFOUNDRIES’s 28nm SLP and HPP processes. 28nm is fast becoming one of the most versatile and widely used process nodes. This is due to its low relative cost and flexibility. The 28nm node is being used for a broad range of products, including networking, wireless, automotive and IoT.

Sidense says their SHF family is available on a wide selection of processes in sizes from 1 Kbit to over 1 Mbit. This makes it suitable for calibration data, encryption keys, ID tags and code storage. This family uses a so called 1T, or one transistor, bit cell to save space and simplify design. SIdense points to the SHF family adoption for use in HTDV processors, PMIC’s, wireless chip sets, and communications and network processors.

Qualification of OTP NVM architectures on a specific node is a significant undertaking that involves cooperation between the foundry and OTP vendor, in this case, GLOBALFOUNDRIES and Sidense. After the design of the bit cell, all the other OTP NVM supporting IP needs be implemented on the target node. This includes the integrated power supply (IPS) that helps eliminate the needs for external supply pins and routing for the programing voltage by generating the necessary voltage internally using the chip supply. On top of this there are addressing and interface blocks in RTL that support the OTP memory core.

Test chips were run at GLOBALFOUNDRIES and then characterized for performance and reliability. After silicon results verified performance of the Sidense SHF family OTP NVP, the two companies announced completion of the qualification process. OTP NVM is one of those things that by itself does not garner a lot of attention. However it is a key enabling technology for many of the growing applications of semiconductor products. Having OTP NVM available on new nodes is ultimately critical to the advancement of many end user products.

April 11, 2015

TSMC Unleashes Aggressive 28nm Strategy!

TSMC Unleashes Aggressive 28nm Strategy!
by Daniel Nenni on 04-11-2015 at 10:00 pm
Categories: Foundries, TSMC

The most interesting presentation at the jam-packed TSMC Symposium last week for me was “Advanced Technology Updates” by Dr. BJ Woo. Coincidentally, I met with BJ during my last visit to Fab 12. Much of what we discussed was about TSMC being more aggressive this year but I wasn’t able to really connect the dots until her presentation. The example I will use here is 28nm but it certainly applies to all of the TSMC process nodes moving forward.

First let me tell you that BJ is engaging and a very credible semiconductor executive. She spent the majority of her 30 year career at Intel in Santa Clara designing both DRAM and microprocessors (she has 13 patents). In 2009 BJ joined TSMC taking responsibility for the advanced technology roadmap at 28nm and 20nm and today is Vice President of Business Development.

According to recent press releases and the resulting comments by analysts, who don’t know any better, other foundries are eating away at TSMC’s 28nm stronghold. Articles like that will get you lots of clicks but they are misleading. Remember, there are two versions of 28nm: gate-first and gate-last HKMG. Moving a TSMC gate-last 28nm design that is in production with 90%+ yield to a new gate-first process is absolute madness. Even moving a production design to a new gate-last process that is supposedly “T” compatible (UMC and SMIC) is risky. But of course it will happen because if you are negotiating a better price from one vendor you have to actually be in the position to use another vendor to even be at the negotiation table.

Having the best yielding process does not just give you the lowest cost, it also gives you better design margins and that is the point TSMC made at the symposium. Today TSMC has five versions of 28nm: HP (high performance), HPM (high performance mobile), HPC (high performance computing), HPL (high performance low power), and LP (low power). Two additional processes were added: HPC+ which is an even faster version of HP and ULP which is ultra-low power for IoT and other battery powered applications.

28HPC+ is more compact with 9 and 7 track cell libraries versus 12 and 9 track for 28HPC. The design rules are the same but it has better design margins which offers 15% more performance. 28ULP looks a lot like 55ULP and 40ULP that are already in production. Compared to the associated LP processes, ULP processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption resulting in a 2x-10x increased battery life. IoT and wearable devices are the target applications for ULP processes of course.

The other big 28nm announcement that BJ made is that the TSMC 28nm is now qualified for automotive work which is an industry first. Given the growth of electronics in our cars and the coming autonomous vehicles this is a very big deal for sure.

In the same vein, BJ also talked about a new 16nm process coming called 16FFC, the C meaning compact. It is a more economical version of 16FF+ aimed at cost and power sensitive markets. Power is said to decrease by more than 50% and the pricing will be very competitive for mainstream markets.

Again, when I met with BJ she said TSMC would be very aggressive moving forward and she had a definite twinkle in her eye and now I know why. What a great year for the fabless semiconductor ecosystem, absolutely!

Xilinx at NAB: Any Media Over Any Network

Xilinx at NAB: Any Media Over Any Network
by Paul McLellan on 04-11-2015 at 7:00 am
Categories: FPGA, Xilinx

The NAB (National Association of Broadcasters) show has just started, April 11-16th in Las Vegas. It covers a very broad range of topics:
As the premier trade association for broadcasters, NAB advances the interests of our members in federal government, industry and public affairs; improves the quality and profitability of broadcasting; encourages content and technology innovation; and spotlights the important and unique ways stations serve their communities.

That is a big range from content to technology. House of Cards to network interface cards.

Xilinx will be there. Programmable logic devices are a key component in a lot of video transmission technologies, being a good combination of flexibility, performance and power. When standards have not totally settled down, programmability is essential, but just using general purpose microprocessors and software consumes too much power, and simply is not high enough performance for many video applications anyway.

In fact Xilinx just launched its next generation of Video over IP connectivity solutions to address the industry’s transition to all IP-based networks. The transition to IP-based technologies is creating huge opportunities for cost savings, video production efficiency, and scalability, but its newness is also creating some confusion and hesitation by some vendors in terms of protocol selection. A programmable Xilinx device in conjunction with an Ethernet PHY offers a firmware upgradeable Video over IP platform that supports any media over any network with cores and reference designs enabling fast time-to-market and low risk deployment.

Xilinx defines and deploys Video over IP protocols for contribution and distribution networks with the provision of IP cores and reference designs. These cores encapsulate multiple compressed JPEG 2000 or MPEG transport streams, or uncompressed SDI streams onto 1Gb and 10Gb Ethernet IP networks, and offer optional Forward Error Correction (FEC) to recover lost packets and provide robustness in media transmission.

Xilinx will be at NAB on booth N5616 demonstrating their video technology cores and full reference designs. Of course all these demonstrations run on Kintex or Zynq programmable platforms.

6G & 12G SDI —this will showcase reference designs that enable developers to implement the latest SMPTE standards for SDI
HDMI—IP cores for both HDMI 1.4 Tx/Rx and HDMI 2.0 Tx/Rx
4K Video Processing—the new Real-Time Video Engine reference design. It also features a motion adaptive deinterlacer, scaler, and OSD at 4K.
SMPTE ST 2059 & ST 2022—demonstration of the upcoming ST 2059 IP core
intoPIX TICO—the intoPIX TICO mezzanine compression provides up to 4:1 visually lossless compression.
Omnitek PCIe Streaming DMA Controller
NGCodec HEVC Encoder—this will implement an HEVC encoder using the HDMI IP cores.

It is not just Xilinx who will be there, but also their partners showing solutions based on Xilinx fabrics: CoreEL are at SU12203, Fidus at N4739, inrevium at N4739, intoPix at C8425a, Omnitek at 3114, Barco-Silex at C8427b and Pathpartner at SU10826.

Xilinx’s specialized broadcast page is here. NAB’s own webpage is here. If you are at NAB then come by booth N5616 and see what any media over any network means.

April 10, 2015

Cu-Pillar in Advanced Logic Devices

Cu-Pillar in Advanced Logic Devices
by Arabinda Das on 04-10-2015 at 7:00 pm
Categories: EDA

In 2001, flipchip with solder bump was already a dominant technology and it was replacing wire bonding as the main interconnection choice for a growing number of devices. It was offering fine pitch interconnections for increased I/O counts. In the solder bump process, a bump is formed on the chip and on the package substrate and they are connected by reflow. During the reflow the solder bumps collapse and do not retain their height in two directions. Moreover, the solder bumps occupy a larger space than the pitch of a pad on the chip. These problems frustrated two researchers in IBM and they came out with an alternative solution, called copper pillars (US 6229220 B1).

Their main idea was to have a conducting post that has two metal layers and the lower one has a melting point that is greater than the first layer. According to the teachings of the patent, the difference of melting temperature between these two materials must be greater than 20 C. The lower layer is in contact with the chip substrate and the upper layer with the package substrate. The lower layer could be made of Cu and the upper layer consists of solder. This difference in melting temperature between the two layers is the main innovative concept of the patent. This would help to retain the height of the conducting post during solder reflow. The patent also outlined an integration process to fabricate Cu-pillars, which came to be known as IBM’s Cu-pillar process. This process is widely used in the industry with minor variations. A few years later around 2007, Intel also introduced their concept of Cu-pillars (US7276801B2), which is slightly different from the IBM process-flow. The basic difference is that the conductive pillar is encapsulated with a diffusion barrier as a protective layer.

Very quickly, many researchers started working on this concept and they realized that the bump-pad height, the bump composition and the bump-pitch had an influence on the stress that was transferred to the underlying dielectrics, especially if the dielectrics were made of low-k materials. The stress was coming from the differential thermal expansion coefficient between the Si substrate and the organic printed circuit board. This discovery led to the major improvements in underfill materials and under bump metallization (UBM). The semiconductor industry quickly realized the advantages of this new technology; including: a bump-pitch in the order of 50 µm that could be achieved and thus open up the possibility of higher density of connection. The stand-off height was definitely an edge compared to the conventional C4 solder bumps and facilitated void free underfill. The biggest advantage was the superior electrical and thermal conductance of copper pillars than that of the solder material.

At 65 nm node, two companies introduced copper pillars; the first one was from Intel (Intel Pentium 65 nm D 920 processor) and the second one was ST-Ericsson (ST-Ericsson 65 nm, DB5730 Baseband Processor). Surprisingly, this technology did not take wings as the technology advanced to the next node. At 45/ 40 / 32 nm technology node, several advanced logic processors flooded the market. But only two companies Intel and Texas Instrument employed the Cu-pillar integration scheme. A list of the 45 nm node devices analyzed at TechInsights is given below along with a remark about their packaging process.

The situation is quite different for devices below 30 nm node. There are fewer device makers who can employ this technology beyond 20 nm. Most of the devices are manufactured either by TSMC, by Samsung or by Intel. Intel has continued to use copper pillars in all its technology nodes since the 65 nm node. Samsung is still using solder bump technology even for their 20 nm logic device; while TSMC has adopted Cu-Pillars in their packaging modules and no company is using wire bonding technology in its advanced logic devices.

The copper pillars of two highly successful processes in the industry are shown below. Figure 1 is TSMC’s 28 nm node and the Figure 2 is Intel’s 22 nm node. The biggest difference between the two processes is that Intel’s 22 nm bond pad is made of Cu, while the bond pad of TSMC’s 28 nm device is formed in Al.

Figure 1: TSMC 28 nm, Cu-Pillar process on Al bond pad, showing the Cu-pillar pitch

Figure 2: TSMC 28 nm, Cu-Pillar process on Al bond pad, showing the Cu-pillar structure

Figure 3: Intel 22 nm, Cu-Pillar process on Cu bond pad, showing the Cu-pillar pitch

Figure 4: Intel 22 nm, Cu-Pillar process on Cu bond pad, showing the Cu-pillar structure

There are some similarities and differences between the two processes. The cross-sections show that TSMC’s process uses fairly perpendicular copper pillars as compared to Intel’s process. The ratio of Cu to solder is smaller for the Intel process as compared to TSMC process. Intel prefers to employ a narrow neck and a broad shoulder. But both of them employ very relaxed pitches, probably to have a void free underfill. The general process flow is the same and the main steps are given below:

— Pattern the bond pads,
— Deposit the passivation layers on top of the bond pads
— Pattern the openings in passivation to expose the top surface of the bond pad.
— Deposit a polyimide layer on top of the passivation and on the exposed bond pad
— Pattern polyamide to have an opening
— Deposit a barrier layer followed by a seed layer (Cu)
— Apply photo-resist and pattern to form a mold for the pillar
— Electro-deposit the pillar material using the seed layer as a nucleation site
— Cap the Cu-pillar with Ni to prevent oxidation and for adhesion with solder
— Deposit solder on top of the Cu-pillar
— Remove the photo-resist and pattern the barrier layers using the pillar as a mask

The differences are mainly in the geometrical aspects and are summarized in the table below:

Table 1: Cu-pillar dimensions and materials for TSMC and Intel

The Cu-pillar dimensions of these two processes are not at the frontiers of what the Cu-pillar can deliver in terms of fine pitch or standoff heights but these Cu-pillar processes are the fore-runners of the industry. They are designed to dissipate heat effectively and have robust reliability for high performance processors. Adoption of the Cu-pillar is inevitable for advanced logic devices because Cu-pillar technology is one of the key enablers of 3DIC integration. In the future, if Cu-Cu bonding becomes the mainstream then the solder cap on the Cu-pillars will eventually be eliminated. Cu-pillar bump technology is needed for through-silicon-vias (TSV) and for other advanced packaging methods.

That is the reason, why the most recent 20nm DRAM device from Samsung is employing Cu-pillars. Recently, Dr. Kevin Gibb from TechInsights blogged that Samsung’s latest DRAM is TSV enabled (TechInsights – Samsung 20 nm DDR4 TSV Enabled DRAM).Adopting Cu-pillars is the first step for TSV bonding. Companies will realize the superior performance of Cu pillars to solder bumps and will feel the need to adopt the process. Several players for the same process will lead to a greater variety of Cu-pillar designs and the manufacturing cost will be lowered.