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Using NoCs to Reduce Power

Using NoCs to Reduce Power
by Paul McLellan on 02-11-2015 at 7:00 am

 Earlier this week I moderated a webinar at Sonics entitled NoC 102: Using SonicsGN to Address Low Power Requirements. Drew Wingard, the CTO of Sonics, presented it. It goes without saying that power is a major concern in SoC design, not just with chips for battery powered devices but also tethered devices. A major cost of ownership issue in datacenters is how much power the equipment takes and how much power the air-conditioning takes to get the heat out again.One particular challenge is that the number of power domains is increasing. These are either islands at different voltages for power reasons, or regions that can be powered down when idle (such as the transmit/receive blocks in your cell-phone when you are not making a call). Increasingly it is not feasible to keep all of a chip powered up at the same time, the challenge of dark silicon. If everything is on at once the chip will breach its thermal envelope.The clock can consumes as much as 30% of the power on a chip so reducing power in the clock itself, and associated with the clock is important. Synthesis will do some fine-grained clock gating for you, replacing muxes recirculating registers with clock-gates. But coarse grained clock gating further up the clock tree (at the block level for example) is even more important. NoC designs typically achieve 99.5% or even 99.9% gating, perhaps 16 free running registers out of 40,000. That leads us to Rule #1:The NoC must support both automatic coarse-grain and fine-grain clock gating which should be architected into the design, don’t just rely on synthesis
Next, power domains. Reducing the voltage reduces dynamic power (a lot, the voltage is squared in the power equation). Reducing it to zero also saves on leakage power which is a big issue in the planar processes that many designs are still done in. If domains that are powered up and down together can be grouped it can save a lot since there are typically fewer signals crossing the boundary compared to gating at the boundary of the blocks themselves. This leads us to rule #2:The NoC must allow “domain boundaries” within the network

  • Different clocks for different parts of the network
  • Different voltage supplies for different parts of the network
  • Portions of the network can be idled or even switched off

One of the challenges with powered-down blocks is putting them to sleep and waking them up. Historically this has often been done by software. But this has two problems: the software is hard to get right, and just to be running software requires the high-powered microprocessor to be running.If the NoC knows the power state of all the blocks it can handle a lot of this in hardware without the microprocessor needing to be powered up. Blocks that have been idle for a long time (no messages) can be powered down, and then when a message arrives it can be buffered while the block is woken up (it takes time to wake up a block since it can’t simply be turned on at full-power from one moment to the next due to inrush current which risks causing voltage droop all over the chip). So rule #3 is: The NoC must be aware of the power state of network components

    [*=1]Allows network interfaces to tell power manager when it is safe to switch off a block
    [*=1]Catch traffic early that accesses powered down parts of the SoC

And rule #4 is:Integrate auto-wake-up features into Network

    [*=1]Network requests wake-up of necessary power domains, without software assistance

You can watch a replay of the webinar here.

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