SemiWiki – Page 747 – The Open Forum for Semiconductor Professionals

May 6, 2015June 14, 2019

Ask me about Mentor at DAC!

If you’ve been following DAC general chair Anne Cirkel’s weekly blog, you know the conference program is now final. There’s much to suggest it will be a great DAC, including a record number of submissions in several content categories and a compelling lineup of keynoters. The week will start with an update on Google’s smart contact lens project and end with a MacArthur genius. If you haven’t already registered, you should, and not just to see the luminaries on the main stage. You can register for the conference here.

Fireside Chat with Wally Rhines
Join us for a more informational interaction with Wally Rhines, CEO of Mentor Graphics. Come to the DAC pavilion to be part of an onstage chat where SemiWiki.com Founder Daniel Nenni engages him in a wide ranging conversation spanning his career, the path he sees for the industry, and the changing role of design automation. Please be prepared to ask you own questions.
Monday June 8th @ 4pm

Turns out some of the best and brightest at Mentor will be at DAC this year. They represent a wide cross section of the company, both in terms of seniority (yes, of course, CEO Wally Rhines has a prominent slot) and subject matter (topics range from automotive reliability to automated voltage-aware DRC, trends in functional verification, and tutorials in next-gen lithography).

The DAC site does a great job of giving you multiple ways to access the program, and that should be your first stop for planning your time at Moscone. However if you’re a Mentor-phile and want to see how the most diverse of the Big 3 EDA companies will be represented in San Francisco, scan through the listings below. There will also be several Mentor presenters at the Designer and IP track poster session on Tuesday, and lots more information (and Lego Mixels giveaways!) at Mentor’s booth.

Despite its multibillion dollar size, EDA is a fairly close-knit, friendly industry, one marked by technologists with deep expertise that takes years of formal and informal training to acquire. If you are curious if one of the presenters below might be answering a specific question in a session put it in the comment section and I will be sure to get an answer for you. It’s in everyone’s interest — Mentor’s presenters and DAC’s attendees — to have the seats full at the conference, and if some old-fashioned pre-conference matchmaking can help make that happen, I’m more than happy to help.

Monday, June 8
● John Park, 2.5D/3D Memory & Logic Integration: Tools, Methodologies, Requirement and Infrastructure, tutorial
● Wally Rhines, Fireside Chat, Pavilion panel
● Andres Torres, Understanding the Impact of Next Generation Lithography on Design, tutorial

Tuesday, June 9
● Harry Foster, Trends in Functional Verification: A 2014 Industry Study, SKY talk and tech paper
● Andrew Patterson, The Convergence of Multiple Vehicle Networks: How to Select One Network Over the Other and the Ensuing Challenges, special session

Wednesday, June 10
● Robert Bates, Developing to ISO 26262 Compliance for Component Reuse, special session
● Mathew Hogan, Are You Ready for The Rigors of Automotive Reliability?, tech panel
● Valeriy Sukharev, Interconnect Reliability Modeling and Analysis for Multi-Branch Interconnect Trees, tech paper
● Andres Torres, Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts/Vias, tech paper

Thursday, June 11
● Janusz Rajski, Nilanjan Mukherjee, and Elham Moghaddam, Design for Low Test Pattern Counts, tech paper

See you in San Francisco! It would be a pleasure to meet you!

May 6, 2015

Love IP Party at DAC 2015

Love IP Party at DAC 2015
by Paul McLellan on 05-06-2015 at 7:00 am
Categories: IP

Once again there is a Heart of Technology event at DAC. It is the Love IP Party on Monday evening. Full details at the end of this entry, but first a bit of context. Heart of Technology was started by Jim Hogan who probably doesn’t need much introduction to anyone who has worked in EDA for any length of time.

I met with Jim, along with Randy Smith and Jill Jacobs, to talk about Heart of Technology and why Jim started it. He said it started in 2007 at the depths of the recession when a lot of people were struggling. Jim had previously given money to San Jose State (his alma mater) but decided that maybe prioritizing getting people food was more important. He also realized that a lot of good causes, such as the food banks, were just not well-equipped to put on significant sized events, whereas Jim knew lots of marketing people in the EDA and IP industries who knew the ropes, plus he knew lots of musicians, including himself, to provide the entertainment. It that sense HOT is a sort of “charity accelerator.”

As Jim puts it:At the heart of technology are people with passion for innovation and change. HOT harnesses that power to go beyond code and silicon and fund programs to help raise awareness of charitable causes that add to the betterment of life in local communities.

So the first event was held at South First Billiards in San Jose to raise money for Second Harvest Food Bank. Subsequent events have benefited Court Appointed Special Advocates (CASA) of Travis County TX (DAC was in Austin that year, which is in Travis County), CASA of San Francisco, a luau at Jim’s house that benefited FleaHab Sober Living Environment of Santa Cruz County. Most recently there was a Rock for CASA holiday event held at Ken Potts’ Doc Auto in Santa Cruz, this time to benefit CASA of Santa Cruz Country. In total over $100,000 dollars has been raised to benefit local charities.

HoT is not just a one-man operation. Now many other people are involved to organize and publicize the events, and a whole group of EDA and IP companies sponsor the events.
This years DAC event will be on Monday 8th of June from 7-11.30pm. It will be at Jillian’s, which is in the corner of the Metreon just opposite Moscone West. The party features fabulous food and an open bar with 17 microbrews on tap and specialty cocktails.

Jillian’s also has lots of pool tables, in fact the largest number in San Francisco, so there will also be the first Spyglass Pool Competition. To enter go to the Atrenta booth earlier in the day and pay your $20 entrance fee.

And that is not the only competition. There will also be a costume contenst. Wear your grooviest outfit and show off your Summer of Love style! Prizes to the hippest outfits. So get your hippie vibe on along with your Birkenstocks and join the fun on stage. Special recognition for original clothes of the day.

[TABLE] align=”center” style=”width: 500px”
|-
| 7pm
| Doors Open
|-
| 7-7.45
| The Sonics on stage with cool jazz
|-
| 7.30
| Pool tournament starts, silent auction starts
|-
| 7.45
| Welcome
|-
| 8-8.45
| Groovy Love brings the party on stage
|-
| 8.45-9.05
| Summer of love lookalike and costume contest
|-
| 9.05-9.30
| Heads tales games with the Big Kahuna
|-
| 9.30-10.15
| Groovy Love back on stage
|-
| 10.30
| Announcement of pool competion winners
|-
| 11.30
| Event ends
|-

This year the event will benefit the San Jose State University Guardian Scholars Program which helps kids who are coming out of the foster care program with nothing, and want to attend college (well, specifically SJSU). As they say on their web page:The SJSU Guardian Scholars Program (GSP), part of the Educational Opportunity Program, is committed to helping students exiting the foster care system, wards of the court, under legal guardianship or unaccompanied homeless youth. Our mission is to guide determined and ambitious Guardian Scholars through their academic and personal journeys by providing comprehensive support.

Please join our generous sponsors and distinguished guests at the Love IP Party. Entry is open to all DAC attendees, but a donation of $50 or more to the Guardian Program at San Jose State University will ensure you a spot at the party. Guests who have provided donations are assured entry into the party and will receive a one-of-a-kind event t-shirt.

More details on the SJSU Guardian Scholars Program is here.
The Love IP Party page with full details is here.

Peace, love and IP. Groovy baby.

May 6, 2015

What is Real SAMV71 DSP Performance in Auto Audio?

What is Real SAMV71 DSP Performance in Auto Audio?
by Eric Esteve on 05-06-2015 at 2:33 am
Categories: Arm, Automotive, Foundries, IP

Why selecting ARM Cortex-M7 processor based Atmel SAMV70/71 for automotive entertainment application? The top three reasons are the Cortex-M7 clock speed (300 Mhz), the integration of a floating point (FPU) DSP and, last but not least because Atmel SAMV70/71 has obtained automotive qualification. If you dig into SAMV70/71 features list, you see that this MCU is declined into several versions integrating Flash: 512 KB, 1024 KB or 2018 KB. And if you compare with the competition, this MCU is the only Cortex-M7 supporting the 2 MB Flash option, being automotive qualified and delivering 1500 CoreMark (thanks to the 300 MHz clock speed when the closest competitor only reach 240 MHz and deliver 1200 CoreMark)…

In fact which makes the SAMV70/71 unique are the FPU DSP performances. Let’s make it clear for the beginning, if you search for pure DSP performance, it will be easy to find standard DSP chip offering much higher performance, like for example Analog Device AD21489 or Blackfin70x series. But the automotive market is not only very demanding, asking for specific qualification, it’s also a very cost sensitive market. A simple calculation shows that, would you select AD21489 DSP, because you have to add external flash and a MCU, the total BOM would be x4 if not x5 compared with the SAMV71 price. Let’s keep this AD21489 as a reference in term in performance, and take a look at DSP benchmark results, coming from third party DSP experts “DSP Concept”.

Before analyzing the results, we need to describe the context:

FIR is made on 256 samples block size
Results are expressed in term of clock cycles (smaller is better)
All DSP are floating-point except Blackfin
Clock cycles count is measured using Audio Weaver

Some more explanation, this FIR is used to build equalization filter, the higher Taps count the better will be the equalization filter. If we look at the “50 Taps” benchmark results, the SAMV71 (Cortex-M7 based) exhibits 22734 clock cycles (about three times more than the SHARC21489). The Cortex-M4 needs 50% more, which is not surprising, but you have to integrate a Cortex-A15 to get better results, as both Cortex-A8 and Cortex-A9 need respectively 30% and 40% more cycles! And when looking at standard Analog Devices Blackfin DSP, only the 70x series is better by 35%… the 53x being 30% worst.
Now, if you want to build a graphic equalizer, you will have to run Biquad. For example, if you want to build 8 channels and 6 stages graphic equalizer, your DSP will have to run 48 Biquad.

Again the context:

Biquad is made on 256 samples block size
Results are expressed in term of clock cycles (smaller is better)
All DSP are floating-point except Blackfin
Clock cycles count is measured using Audio Weaver

In fact the results are very similar to the FIR benchmark results: only the Cortex-A15 and the SHARC21489 exhibits better performances. The integrated FPU DSP (into the Cortex-M7 core) is using 2x the number of clock cycles when compared with the SHARC21489. If you compare the performance per $, the Cortex-M7 integrated in the SAMV71 is 50% cheaper! Let’s say that using a SHARC DSP certainly makes sense if you want to build high performance home cinema system, but if you target automotive, better to select a FPU DSP integrated together with Flash (512KB to 2MB) and a full featured MCU.

Atmel SAMV71 is specifically dedicated to support automotive infotainment application, offering Dual CAN and Ethernet MAC support and this complete features list:

10/100 Mbps, IEEE1588 support
12 KB SRAM plus DMA
AVB support with Qav & Qas HW support for Audio traffic support
802.3az Energy efficiency support
Dual CAN-FD
Up to 64 SRAM-based Mailboxes
Wake up from Sleep or Wake up Modes on RX/TX

Don’t forget that when you have built this automotive high end radio you still need room for Ethernet MAC and AVB support… And the SAMV71 only consume 68% of the DSP resource, leaving well enough for AVB and Ethernet MAC.

More information about this DSP benchmark can be found on DSP Concept web here.

From Eric Esteve from IPNEST

May 6, 2015

What is Real SAMV71 DSP Performance in Auto Audio?

What is Real SAMV71 DSP Performance in Auto Audio?
by Eric Esteve on 05-06-2015 at 2:33 am
Categories: Arm, Automotive, Foundries, IP

Before analyzing the results, we need to describe the context:

FIR is made on 256 samples block size
Results are expressed in term of clock cycles (smaller is better)
All DSP are floating-point except Blackfin
Clock cycles count is measured using Audio Weaver

Again the context:

Biquad is made on 256 samples block size
Results are expressed in term of clock cycles (smaller is better)
All DSP are floating-point except Blackfin
Clock cycles count is measured using Audio Weaver

Atmel SAMV71 is specifically dedicated to support automotive infotainment application, offering Dual CAN and Ethernet MAC support and this complete features list:

10/100 Mbps, IEEE1588 support
12 KB SRAM plus DMA
AVB support with Qav & Qas HW support for Audio traffic support
802.3az Energy efficiency support
Dual CAN-FD
Up to 64 SRAM-based Mailboxes
Wake up from Sleep or Wake up Modes on RX/TX

More information about this DSP benchmark can be found on DSP Concept web here.

From Eric Esteve from IPNEST

May 6, 2015

New Vivado release goes from Lab to UltraScale

New Vivado release goes from Lab to UltraScale
by Don Dingee on 05-06-2015 at 1:00 am
Categories: FPGA, Xilinx

Xilinx users will welcome the brand-new release of Vivado Design Suite 2015.1. For openers, device support for the latest FPGAs in the UltraScale family – XCVU440, XCVU190, and XCVU125 – has been added in the release, and early access code for the XCVU160 is available from a local Xilinx FAE. Installation has been streamlined, removing the need for root or sudo privileges on Linux for the suite, with a new dedicated script for handling cable drivers manually as an option if needed. Borrowable, floating FlexLM license support is improved in this release, and a new standalone hardware microserver (it’s small, less than 1% of the code for the total product) handles remote debug over Ethernet, easing distributed development.

One of the biggest new features in this version is actually … a variant with fewer features, available free of charge. Sometimes, all one needs to do is program and debug a part, like in test or academic environments. Now, a new lightweight edition – Vivado Lab Edition – does just that and nothing else. It comes in a 75% smaller, 1GB download, doesn’t require license keys or activation, and supports all the same Xilinx devices of the full suite.

For development users who crave the full-price Vivado Design Suite and the latest feature enhancements, this release has those as well. The need for speed has been addressed, with improved simulation script algorithms that speed up compile time by 2 to 2.5x. This and other improvements yield 20 percent faster simulations than previous Vivado releases, and an order of magnitude improvement in simulator disk footprint. Using the Vivado TCL store infrastructure, this version integrates with Aldec Riviera-PRO for more advanced simulation, as well as with simulation flows from Cadence, Mentor, and Synopsys.

With the extensive changes in the UltraScale clocking structure and far more clock regions in the part, the likelihood of clock domain crossings (CDCs) in a large FPGA design continues to increase. CDC detection in this Vivado release now spots 16 typical topologies, with summaries by clock pair or by rule type with cross probing to schematic and RTL.

There are also new enhancements for Zynq-7000 All Programmable SoC developers, with additions to analyze performance of the processor subsystem (PS) and the bandwidth used between the PS, the programmable logic (PL), and external memories. System model designs with AXI traffic generators are also provided for the ZC702 and ZC706 evaluation boards.

The partial reconfiguration feature introduced previously has been further expanded, including UltraScale support. There are numerous improvements in IP and its integration, and changes specific to IP leveraging UltraScale features. Among new IP in the release is a block for UHD-SDI video in several SMPTE formats.

Noteworthy is for the full-featured Vivado Design Suite 2015.1, 32-bit operating system support has been removed. This allows performance optimization for design entry and implementation to move forward. Vivado Lab Edition 2015.1 is still supported on older development hosts such as Windows 7 and Red Hat Enterprise Linux 6.

Vivado users should head for http://www.xilinx.com/download to get their new version, including the hardware microserver, documentation navigator, and license management tools. A short video highlighting many of these changes is also available at

What’s New in Vivado 2015.1

May 5, 2015July 18, 2025

SoC’s Shift Left Needs Software Integrity

SoC’s Shift Left Needs Software Integrity
by Pawan Fangaria on 05-05-2015 at 3:00 pm
Categories: EDA, Synopsys

Since Aart de Geus, co-CEO and co-founder of Synopsys, gave his keynote at the Synopsys User Group (SNUG) conference in Silicon Valley last March, I’ve been hearing a lot more about the “Shift Left” in semiconductor design. Although I couldn’t attend Synopsys’ 25[SUP]th[/SUP]SNUG, I found some short videos on the Synopsys website in the News Room that summarized key ideas that were discussed there, including this “Shift Left.”

At the SNUG Designer Community Expo, Synopsys’ Phil Dworsky, Director of Strategic Alliances, interviewed Aart de Geus and Andreas Kuehlmann, GM and Sr. VP of Synopsys’ Software Integrity Group. Here are my key takeaways from these videos –

When Aarttalked about SoC design and verification shifting left in his keynote address, he meant something big. It wasn’t simply doing more things faster to accommodate larger SoCs in the same schedule; of course that task itself is not so simple with today’s SoCs containing several functionalities, multiple heterogeneous IP blocks, gate counts running into billions, and a huge heap of software sitting on top of it. Synopsys has already taken a leap in providing SoC design acceleration and productivity through its powerful platforms for designing and verifying SoCs, and developing and re-using IP. Recently, Synopsys introduced IP accelerator kits that enable IPs to be quickly developed and verified in larger designs. Aart says IP is a never ending investment area for Synopsys. That being said about what is already happening; the big question now is how to gain 100 times more productivity from here. That’s where the software comes into the picture. Today, designs are driven by software; there are more software engineers than hardware engineers in semiconductor companies. In Aart’s words, “most of the chips are supercomputers already.” So, the focus is software; that has to be disciplined, strengthened and made robust. It’s software that will take us to larger contexts of designs. Of course, the software development has to be augmented with what we’ve learned from hardware design.

It’s something being pursued on a major scale at Synopsys. Synopsys has even modified its logo. If you haven’t noticed it already, read the line “Silicon to Software” below the logo itself. Aart’s keynote includes more details on the strategy behind this change. It will be interesting to follow how Synopsys executes on this new theme.

In the other video on the News Room page titled, “Silicon to Software,” Andreas Kuehlmann talks about what EDA has done for the electronics hardware industry over the last 30 years and how that relates to what Coverity(now part of Synopsys) has been doing for the last 10 years in the software domain. Comparatively, hardware design is much more rigorous; there is sign-off at every stage whereas there is no sign-off of software. Patches are implemented when any problem arises. Enabling developers to find bugs with respect to security and quality early in the development cycle will enable a “Shift Left” in software, as well. But this is a practice that has yet to be adopted into the culture of most software organizations. It has to be a daily routine for software developers and Coverity tools can significantly help there.

Today, IC design includes static and dynamic sign-off tools. Software needs similar solutions to help developers make sure that their applications are secure and provide the intended value to customers. With Coverity’s methodology, developers can make software quality measurable and enforceable through a quality matrix.

See the actual videos “Design Flows: Shifting Left”and“Silicon to Software”here on the Synopsys New Room website. Choose the title from the list of videos at the bottom of the page and click on the video icon; it’s readily viewable without requiring registration.

Also view Aart’s full keynote, “Silicon to Software: Shift Left!”

Lessons learned from hardware design must be applied to software development. That’s how software integrity will be realized. I expect we’ll be hearing a lot more about this at future SNUGs.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

May 5, 2015

MIPI CSI-2 and DSI IP? Better with FPGA Prototyping Set

MIPI CSI-2 and DSI IP? Better with FPGA Prototyping Set
by Eric Esteve on 05-05-2015 at 7:00 am
Categories: EDA, FPGA, S2C EDA

Sourcing MIPI CSI-2 or DSI IP to a respected IP vendor is mandatory to build a peripheral IC or a SoC targeting mobile application as the chip maker simply can’t afford to do a re-spin because of Time-To-Market imperative. Buying this IP to a vendor also offering MIPI powered FPGA Prototyping Platforms is even better! Northwest Logic was one the first IP vendors to develop controller for MIPI camera (CSI-2) and display (DSI) specifications and they know that their customer very first need is for silicon proven solution and right after to benefit for a FPGA Prototyping Platforms integrating MIPI D-PHY and CSI-2 (or DSI) controller. That’s why S2C and Northwest Logic have built such a partnership. The cores are now a part of S2C’s expansive library of Prodigy Prototype Ready™ Interfaces, see picture:

A fully defined MIPI D-PHY interface requires one clock lane and four data lanes using in the above board Meticom MC20901 as a Rx D-PHY chip and Meticom MC20902 as a Tx D-PHY chip. Let’s take a short look at these Meticom FPGA to D–PHY bridge ICs allowing for example connecting MIPI (CSI-2) powered camera controller to MIPI (DSI) powered display controller through any FPGA only supporting LVDS or CMOS I/O, but not MIPI D-PHY:

S2C’s MIPI D-PHY Prototyping Kit includes one S2C MIPI D-PHY Interface Module, one OV2710 Camera Module, and one 70WW2A WVGA Display. The MIPI Module supports the fully defined MIPI Rx Interface and MIPI Tx Interface through an MMCX connector. MIPI D-PHY Interface Module occupies one Logic Module connector and can be used on S2Cs Prodigy Virtex-7 Series Logic Modules.

The MIPI D-PHY Interface Module features:

5 Pairs MMCX for MIPI Rx
5 Pairs MMCX for MIPI Tx
MC20901 conversion of SLVS input to LVDS output up to 1.4Gbps
MC20902 conversion of LVDS input to SLVS output up to 1.4Gbps
Support Bus Turnaround option on Channel E
On board level shifter circuitry to support 1.2V~1.8V I/O
On board I2C Interface to Camera and Display
Occupies one LM connector

As you can see on the above graphic extracted from the “MIPI Ecosystem 2015” survey from IPnest and simplified to only show the most used interfaces in mobile phone and tablet, for multimedia (Camera, Display, Soundwire, SLIMBus), storage (UFS, UniPro and M-PHY) and RF (RFFE, DigRF and M-PHY) the winners are…
… Camera (CSI-2, CSI-3) and Display (DSI and DSI-2).

If you want to figure out which of the camera and display specification release are the most used, just look at the difference between D-PHY and M-PHY adoption rate, keeping in mind that M-PHY should also be used with UFS and DigRF on top of CSI-3 and DSI-2. Clearly D-PHY is the most used of the MIPI PHY specification and by consequence the winners are DSI and CSI-2.

Accelerating TTM is crucial in such a fast-moving market like mobile. The chip maker will use an already proven solution (Northwest Logic has used the S2C’s MIPI D-PHY Prototyping Kit to validate their own IP design) and will be able to jump-start his own FPGA Prototyping Platforms by using S2C’s prototyping kit.

You better understand why when Northwest Logic and S2C have developed a demo to showcase the effectiveness of the integrated solutions (above), this demo was based on CSI-2 and DSI. Simply the most used MIPI specifications! The video captures video data through a camera using a CSI-2 interface, stores the data into DDR3 memory, and then transfers the data via a DSI channel and display. The demo utilizes Northwest Logic’s MIPI CSI-2 camera controller, DSI display controller and DDR3 controller IP cores. The demo features support for multi-lane MIPI CSI-2 and DSI operations and pause capability.

This demo will be featured at this year’s Design Automation Conference, June 8-10, in the S2C booth #3108.

Link for S2C’s MIPI D-PHY Prototyping Kit

Availability
S2C’s MIPI D-PHY Prototyping Kit is available now.

From Eric Esteve from IPNEST

May 4, 2015September 1, 2024

Smartphones in Q1. Sammy Back On Top

Smartphones in Q1. Sammy Back On Top
by Paul McLellan on 05-04-2015 at 7:00 pm
Categories: Mobile, Samsung Foundry

Because it is such a major impact on the semiconductor industry, being the largest and fastest growing market ever, I follow the ups and down of the mobile industry. So what happened in Q1?

Total shipments are up 2% to a record (for Q1) 440 million units but that is down 16% from Q4 which remains the biggest quarter ever.

First thing is that Samsung is back at #1 which I predicted last time I wrote about mobile. This is not due to the new Galaxy models (S6 and S6 Edge) which were only announced in the quarter and were not actually available until April. Samsung is up 11% sequentially and analysts put them around 83 million units. With the new Galaxies reportedly selling well I expect Samsung to pull ahead of Apple even more next quarter.

Wireless Networks Chronicle: The Rise of LTE

Wireless Networks Chronicle: The Rise of LTE
by Daniel Nenni on 05-04-2015 at 7:00 am
Categories: Mobile

Aaron Bartlett, a respected semiconductor industry executive, thinks that “Age of Mobile Data: The Wireless Journey to All Data 4G Networks” is the best book he has come across since Walter Isaacson’s biography on Steve Jobs. There is no dearth of books on wireless networks and Long Term Evolution (LTE) technology so what is so special about this book?

In a nutshell, as Bartlett puts it, the artful integration of the technology and history makes a tremendous story on an industry that is practically driving the growth of chip industry in the post-PC era. Wireless networks in general, and LTE-based 4G networks in specific, create a labyrinth of technology jargon that can overwhelm wireless engineers. Age of Mobile Data doesn’t attempt to offer all the technology details because that would make a very thick document.

Instead, the book chronicles the pre-4G, 4G and post-4G wireless technologies with a past, present and future storyline. “The whole story presented is easy to read,” acknowledges another reader Bernhard Walke. “The author is extremely knowledgeable on many historical facts.”

The book details wireless technologies like LTE in a story-like format

The intimate knowledge of LTE-centric wireless networks is now a must for engineers and technology professionals because smartphone and 4G wireless networks are serving as the key growth engine for the technology world. The book a story-like account that saves readers from dry technical details and keeps them engaged with a fascinating tale of technology evolution.

Age of Mobile Data provides a detailed treatment of the major building blocks of the data-centric LTE networks as well as a blueprint of evolving 5G technologies. Furthermore, its shows how cellular networks like LTE are converging with Internet of Things (IoT) platforms like smart home and connected cars.

Key technologies like MIMO are explained in graphic details

The book first covers early mobile data networks like ARDIS and Mobitex and provides a detailed treatment of GSM’s mobile data offshoot: GPRS. Age of Mobile Data then focuses on three generations of wireless networks that feature mobile data as a pure-play: 3G, 4G and even 5G. While doing so, the book explains the key industry concepts like LTE, MIMO, HetNet and small cells in graphic details. Moreover, to offer a complete picture to its readers, the book delves into how Wi-Fi networks are complementing cellular systems amid an exponential increase in mobile data traffic.

Book provides a glimpse of 5G blueprints

Age of Mobile Data is written in the business language to make it more readable for people who don’t have the engineering background. The book is especially aimed at managers in IT, retail and service industries who have to deal with 4G network technology one way or the other. It’s a must read for managers tasked with formulating the 4G network strategy.

Age of Mobile Data: The Wireless Journey to All Data 4G Networks is available in both paperback and e-book formats at leading channels.

May 3, 2015

A Perfect Catalyst at the Right Time

A Perfect Catalyst at the Right Time
by Pawan Fangaria on 05-03-2015 at 7:30 pm
Categories: Mobile

There cannot be a product without a need. The need is the first essential aspect which has to be created or at least felt and then comes a slew of motivator factors including style quotient and fashion statements. It’s possible that a genuine but ill conceived need can be undermined by an overwhelming fashion statement although under-serving that need. This is exactly what happened with the smartwatch trial by tech companies against the behemoth Swiss watch market in 1999. The message of the need of an smartwatch couldn’t penetrate the ambience of the watch market hegemonized by Swiss fashion statements. Advancement of smartphone also played spoilsport against smartwatch. The need of smartwatch was ill conceived in a sense that the same could be effectively fulfilled by an smartphone. Hence the smartwatch took a beating from both sides; it was perceived neither as a need nor as a fashion statement.

More than a decade later what Pebble did is the first essential thing; it demonstrated the need of an smartwatch and that was very rightly embraced by the people. They came forward to support the Pebble kick-starter campaign. Hence the smartwatch market was re-created and several other companies re-entered the fray again with their smartwatches. However, most of them were focused on the need; it was natural of them as they were already beaten by the fashion giants.

However, the watch market beyond the usual time keeping is dominated by fashion. The fashion is so strong that they deserve a separate, focused, and highly decked up worldwide event “The Baselworld Watch and Jewellery Show” every year. So, now you can guess; the other part of the smartwatch, the fashion was equally or even more important. The platform of smartwatch market was beckoning for addition of that glamour element into the smartwatches. As the smartwatch platform was readily available, it was the most opportune time for Apple to fill that gap for smartwatches to be glamorous and fashionable along with even higher level of fulfilment of the need as perceived by the people.

The Apple Watch is not just a catalyst for the smartwatch market; it’s a crusader for the established luxury watch market. Although they didn’t talk much about the Apple smartwatch at the last ‘Baselworld Watch Show’ in March 2015, the makers of luxury Swiss watches are really concerned about it. The Tag Heueris more open in recognizing the threat from Apple Watch, and forthcoming in making strategies with Inteland Googleto diffuse the tension. I will talk about the Tag Heuer story later, now focusing on what Apple Watch has done to galvanize the smartwatch industry and at the same time to keep itself ahead of the others in the watch industry. Just read its tag line, it doesn’t add the word ‘smart’ before ‘watch’, it’s an Apple Watch against all odds.

Yes, it’s a catalyst for other smartwatches to join the bandwagon. It makes sense for an army to follow a leader when it’s like a war between an smartwatch market and a luxury watch market. In last few months, we have started hearing about several smartwatches which were in hibernation. Some of them have good potential to come along in the leading lane. I will talk about them sometime later. Today is the time for the Apple Watch. It’s not possible to cover the whole of Apple Watch in one article, but let’s see some of its glimpses here.

The Apple watch has everything that a smartwatch should do, plus some more creative features, which Apple says are for better human care. The Watch is perfectly synchronized with the iPhone (communicating over Wi-Fi and Bluetooth) to check notifications including text messages, phone calls, and e-mails, and so on. When the watch is in a recognized Wi-Fi zone, and your iPhone is dead, the watch can perform your essential on-line functions like the iPhone. It can also be used to pay your bills with credit cards, just wave your wrist wearing this watch. The watch also has a microphone and a speaker. Apple’s digital assistant Siri can be used to dictate a message to be sent.

What is human in the watch? Well it continuously monitors your heart rate; it has several activity tracking features such as your walking time, sitting continuously, exercising etc. You have an option to set it up to remind you to get up from your chair after some time, walk around for a while, and come back. Things like that can make you more disciplined to maintain your health. It also has a separate app for complete workout for an active exercise schedule. There are many other useful pre-installed apps for various purposes.

An awesome feature is animation. You can animate your emotions through pictures of heart, face, hand, palm or finger movements and send it to the other watch. If the watch on the other side is also an Apple watch, then the live animation during its drawing can be also shared at the other end. You can also send your heartbeat along with an animated heart that can be felt by the other person through gentle taps on her wrist and the heart appearing on the screen.

On any incoming message, call or alarm, it gently taps on your wrist along with different kinds of low volume chimes with different types of notifications. It’s unlike a rude vibration felt on your wrist. You can also send the watch in quiet mode by pressing your palm against its screen. There are many other features that make the watch human friendly and more exotic. There are interesting watch faces such as solar, astronomy, chronology, and so on. Well, I am not making an Apple watch selling pitch here, so am not going into its laundry list of features; may be for some other time.

Coming back to the smartwatch market that been created by Apple. Now that an smartwatch has style as well as functions, if you have $500 to spend, do you think you will buy a mechanical luxury instead of a modern luxury like Apple watch that is intelligent? Well, mechanical luxury also has its value, but that will become more of an antique value rather than a modern luxury. There will be snobbish people who would still buy Swiss mechanical luxury, but that percentage will go down significantly.

I think Apple marketing has conducted a deep study of changing consumer behaviours and preferences, and done an excellent job coming up with such a piece. Today’s style quotient does not go by value such as gold or diamond studded in antiques, unless that is meant for a bride and a groom at the time of their marriage in countries like India. The style quotient has changed over time; today style has tech quotient embedded in it. That reminds me about an advertisement on TV sometime ago, in which a few teenage girls each having stylish smartphones were teasing a middle aged person holding a feature phone. The tech quotient is embedded in our lives in a big way today. The youth looks at style as well as intelligence in the things they use daily and they do not believe in hoarding something they don’t use.

Apple has a great field day today. In most probability it will prove success to Apple as well as other smartwatch makers who can work smartly to combine these two things – style and functions that were needed but no one could perceive them until today.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com