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Semiconductor Expert Forum

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ARM & Cadence IP Partnership for Faster SoC Design

ARM & Cadence IP Partnership for Faster SoC Design
by Eric Esteve on 03-18-2015 at 9:50 am
Categories: Arm, Cadence, EDA, IP

IP vendors always try to create differentiation, especially when designing protocol based IP. You can differentiate by building the most performing controller but you will probably miss the expectation of these customers who don’t search for performance but just compliance to a specific standard. Or the vendor may want to design features rich controller supporting every possible capability included in the protocol specification but in this case not addressing customer demand for a compact IP optimized for area and power…

What could be the common requirement, for customer designing SoC addressing various market segments like mobile, consumer, networking, storage, automotive and the Internet of Things (IoT)? Time-To-Market (TTM) is the answer! If you are able to provide pre-integrated IP solutions, not only silicon proven but also validated in a design environment similar to this your customer will follow, available on a single development platform, then you will bring TTM advantage through faster integration of the most important IP.

Designing a SoC means using foundation IP (libraries and memory compilers), integrating CPU and probably GPU core(s) and interface IP (USB, PCI Express, DDRn or LPDDRn, etc.). Cadence offers a wide interface IP port-folio, ARM Ltd is the CPU (GPU) IP core leader supplier (and also #1 IP vendor, by the way). If these two companies build an agreement based on pre-integration of their respective IP, running interoperability of these IP and going up to test chip design, such cooperation may really offer TTM advantage to SoC design team. Extracting from the join Press release, this sentence clearly describe the scope of agreement between ARM and Cadence:

“This multiyear agreement provides reciprocal access to relevant IP portfolios from the Cadence[SUP]®[/SUP] IP Group and ARM. Additionally, the agreement grants both companies rights to manufacture test chips containing Cadence IP and ARM IP and to provide development platforms to customers. The ability to test the IP interoperability in silicon is intended to enable Cadence and ARM to optimize performance and interoperability within systems on chip (SoCs) while accelerating time to market for customers in markets such as mobile, consumer, networking, storage, automotive and the Internet of Things (IoT).”

If you evaluate the TTM impact, it’s clear that this engineering time spent in advance by IP vendors to optimize performance and interoperability during the Test Chip integration phase just become a net time benefit for customer SoC design team. This team should shorten the design phase by an equivalent amount of time during SoC integration. Moreover, the agreement allows ARM (resp. Cadence) to design development platforms built around ARM (resp. Cadence) test chip integrating IP from both sources and to deliver this platform to ARM (resp. Cadence)’s customers.

As mentioned by Pete Hutton, executive vice president and president of product groups, ARM: “This agreement expands upon the successful EDA Technology Access and EDA Subscription Agreements ARM signed with Cadence last year to further enable our customers’ designs to reach peak performance and power efficiency.”

And Martin Lund, senior vice president, IP Group at Cadence points the TTM advantage: “This new agreement allows customers of both companies to get to market faster with pre-integrated IP solutions and continue pushing the envelope on low-power and high-performance SoC design.”

If we look back in the 2000’s the IP market has been completely re-engineered for quality: all the providers not able to meet customer demand for high quality IP have disappeared or been acquired. Then at the end of the 2000, the mantra became “Integrated solution” for interface IP and “one-stop-shop” for most of the IP. If one-stop-shop can help saving legal or purchasing resource, the impact on chip integration is weak.

IP vendors understood at the beginning of the 2010’s the need for providing development platforms, virtual prototyping and hardware prototyping systematically. The goal was to improve TTM by improving software development. Chip integration is the heart of SoC development but little has been done since 2000, or at function level (integrated interface IP and PHY and controller IP interoperability), but not at SoC level. This partnership between ARM and Cadence is one step beyond in the race for faster TTM as it helps improving the SoC integration itself, and this agreement is the first of this kind…

By Eric Esteve from IPNEST

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SEMI: All This and Breakfast Too

SEMI: All This and Breakfast Too
by Paul McLellan on 03-18-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

Are you interested in any of these?

  • Internet of Things
  • Trends and Forecast for Fabs
  • Inflections Points
  • Semiconductor CAPEX
  • Cost Effective Scaling
  • Prospects for 450mm
  • Future of EUV
  • Mobile Machine Learning
  • Robotics/Drones
  • Cybersecurity
  • Used Equipment Markets
  • World Fab Databases
  • Free breakfast

No? Then I think you got the wrong website to be visiting. This Friday 20th March at 7.30am (yes, but there will be coffee to wake you up) is the SEMI Silicon Valley Breakfast Forum. This time it is subtitled Wafers to Wall Street, a Semiconductor Outlook. The meeting will take place at SEMI’s headquarters at 3081 Zanker Road (map). Registration and breakfast from 7:30am and the meeting proper starts at 8am.


The presentations are:

  • Dean Freeman of Gartner on The Impact of IoT on Semiconductors
  • Christian Dieseldorff of SEMI on SEMI’s World Fab Forecast, Trends and forecast for spending, capacity and more
  • Patrick Martin of Applied Materials on The Role of Materials in Scaled Architecture
  • John Pitzer of Credit-Suisse on The Semiconductor Outlook: Bigfoot, UFOs, Sustained Upturns
  • Samir Kumar of Qualcomm on How today’s processors will power other devices beyond phones

Each presentation is 20 minutes. The meeting will wrap up by 10.30am.

More details including a link for registration are here.

About SEMI
SEMI is the global industry association serving the nano- and microelectronic manufacturing supply chains. Our 1,900 member companies are the engine of the future, enabling smarter, faster and more economical products that improve our lives. Since 1970, SEMI has been committed to helping members grow more profitably, create new markets and meet common industry challenges. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information on SEMI, visit www.semi.org.

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Webinar: Choosing IP for your next IoT Design

Webinar: Choosing IP for your next IoT Design
by Daniel Payne on 03-17-2015 at 8:00 pm
Categories: eSilicon, IoT, Semiconductor Services

My favorite IoT device is a cycle-computer from CatEyeand it has GPS for tracking my bike routes, and an LCD display that shows me speed, cadence, heart rate and time. After each ride I connect my CatEye device to a USB connector, upload my data to Strava.com, and then see how I’m doing versus other cyclists and my own personal records. This computer holds a charge of some 12 hours, doesn’t require any phone to operate, and is wireless, so you don’t see any wires stringing around my bike frame. Even the heart sensor is wireless, thanks to bluetooth.

I can only imagine the kind of IP that CatEye and other companies must choose to get their products to market quickly and capture the loyalty of consumers looking to get and stay healthy. The folks at eSiliconinvited me to a webinar last week on the topic of IP and IoT designs, and I learned quite a bit. Analysts estimate that the IoT market could create $300B to $19T in revenue with 25B to 100B devices by 2020. Segments for IoT devices and services include opportunities for many semiconductor products in diverse markets:

  • Connected Vehicles
  • Healthcare
  • Smart Homes
  • Wearable
  • Computing
  • Industrial Internet
  • Communications
  • Smart Cities

Depending on the IoT application you could use a range of process technologies from 180 nm all the way down to 14/16 nm, it all depends on the power, performance and area required.

Related – IP for IoT: Thanks for the Memory

Microcontrollers are often used in IoT devices and you can select the best MCU by choosing from 8 to 64 bits, clock speed, embedded FLASH, OS, radios, and process nodes.

What eSilicon has to offer your IoT team are ASIC design services along with IP. They have online tools for multi-project wafers, IP libraries, and tracking of manufacturing. They use their own IP for client designs that require ultra low voltage (ULV) and ultra low power (ULP). IP blocks for IoT devices include:

  • ULP/ULF SRAM & ROM
  • Pseudo DP SRAM
  • Low leakage SRAM
  • 65 nm, 55 nm, 40 nm, 28 nm
  • Planar CMOS and FDSOI technologies

Related – eSilicon Just Taped-out a SonicsGN-based SoC. And it’s not a Secret

For high-performance networking, communications and networking devices their IP blocks are:

  • TCAM
  • Multi-port & Asynchronous Register Files
  • SRAM, ROM
  • Memory PHYs and interposer design
  • 28 nm, 16 nm, 14 nm, 10 nm
  • Planar CMOS and FDSOI technologies

Requirements for IP that are both ULV and ULP are not met with the standard IP offered by most vendors and foundries at the 28 nm node, so eSilicon has IP and the ability to customize the IP to meet the needs. One client chip that eSilicon designed was in 28 nm technology, had 16.84 million gates and used about 42 Mb of memory. They were able to analyze and optimize the IP to show an 8X reduction in standby power and 20X improvement in idle power by using customized IP.

For a Medical IoT application eSilicon was able to provide a 40 nm Single Port SRAM that was not available anywhere else:

Another specialty SRAM instance was for a 1K x 24 size operating at just 720 mV and 36 MHz, using 55/65 nm technology.

Related – IP Market at your Desk!

Ternary CAMs are used in high-performance networking applications in the Cloud, and eSilicon has created a family of CAM compilers to work with multiple technologies.

Summary
For IoT designs you can get to market more quickly by re-using specialized IP or even consider using ASIC design services from a company like eSilicon. View the entire 35 minute webinar online for more details.

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Exploring IP You Didn’t Design Yourself

Exploring IP You Didn’t Design Yourself
by Paul McLellan on 03-17-2015 at 7:00 am
Categories: Concept Engineering, EDA

Starvision Pro from Concept Engineering is a bit like one of those Leatherman multi-tools, it has a huge number of different functions, some of them fairly specialized but nonetheless incredibly useful. Many of these functions are unique to Starvision Pro, with nothing else like it on the market. Some new videos, produced by EDA Direct, who are Concept Engineering’s US distributor, show some of these applications.

Designing an SoC these days is mostly about IP assembly. This means that design teams acquire IP blocks which they did not design themselves and so are not familiar with. Working on these blocks, to customize them or even just understand them, requires the capability to manipulate them in various ways quickly and efficiently.

The first video is taking in a large complex netlist and pruning it down to something more manageable for detailed analysis. Large netlists create confusion and are simply less productive when all you want to do is find a single trace, a single critical path or a small sub-chunk of a module. Starvision Pro has an incremental design navigation feature called cone-extraction which allows you to focus on the part of the netlist in which you are interested while hiding the rest of the netlist that is not of immediate interest. In a special cone-window you can explore the connectivity up and down the hierarchy or, with a flat netlist, nagivating through the sea (ocean) of logic gates. The chunk/fragment/partition/pruned netlist can also be saved as a Verilog or SPICE netlist for further simulation.

Click on the picture below for the video (9 minutes)

Next up, how to take a flat netlist and add hierarchy. Why might you want to do that? If you have received 3rd party IP then it might not have enough hierarchy to make the design easy to understand or manipulate. Never fear, Starvison Pro can make it easy to turn flat into hierarchical quickly.

Click on the picture below for the video (8 minutes)

Finally, processing post-layout parasitic files like DSPF/SPEF. You often find yourself trying to read lines of text and figure out the connectivity between different nets with lots of parasitics. Starvision Pro lets you read the file and
view the entire connectivity of the parasitic network in the form of a schematic. YOu can not only examine the schematic but the tool helps you debug the RC network net by net.

Click on the picture below for the video (6 minutes)

The video gallery, containing all these videos and more, is here.

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Mapping Focus and Dose onto BEOL Fabrication Effects

Mapping Focus and Dose onto BEOL Fabrication Effects
by Tom Simon on 03-16-2015 at 7:00 pm
Categories: Coventor, EDA, Events

With today’s ArF based lithography using 193nm wavelength light, we are hard up against the limitations imposed by the Raleigh equation. Numerous clever things have been devised to maximize yield and reduce feature size. These include 2 beam lithography, multiple patterning, immersion litho processes to improve NA, thinner resists, etc. While we wait for EUV to become feasible, those responsible for manufacturing current production chips work with tuning the dozens of aspects in the existing lithography and fabrication process.

We have talked before about the utility of modeling what happens during the IC fabrication process. The ability to simulate the outcomes of fabrication steps is enormously valuable. Coventor’s Semulator3D is a proven tool for performing these simulations. They have a number of white papers on their website that go through the process step by step. The BEOL paper that they feature on this page highlights a tri-layer mask process that uses a thin photo-resist to improve transfer of the aerial image. The latent image is also improved by the middle anti-reflective layer which avoids reflected interference patterns in the resist. These can notably affect edge definition and can undercut the resist at the bottom.

The Coventor Semulator3D shows exactly what happens during processing. This is invaluable in determining the reliability and electrical properties of the resulting wafer. However the developed resist image depends on a myriad of factors. So before we can look at the effects of wafer processing, we need to have a good starting point with physically accurate resist geometry. Focus and dose both have profound effect on the resist sensitization. This is often visualized with a Bossung curve such as that show here from Chris Mack’s excellent lithography lecture series.

Let’s say we wanted to model the whole process from litho to fabrication. This is exactly what Coventor, Panoramic Technology and ASMLdid in material they showed at SPIEa few weeks ago. They used HyperLith from Panoramic Technology to predict the resist contours at a variety of doses and defocus values (0 to +/-50nm). We can see the wide variation in resist quality. Then they took this output and ran it through Coventor’s Semulator3D to see what the resultant wafers would look like.

Coventor can run simulations using their SWA (side wall angle) Variation and look at results with a range of side wall angles. The tradeoff here is line width versus line spacing. If the line widths are too small you have opens in the interconnect and high resistance that can affect circuit operation. If the line to line spacing becomes too small it’s possible to get shorts or proximity failures.

The flow that was used in their SPIE material shows a matrix of dose and defocus values that is then run through Semulator3D with SWA variation. This provides a comprehensive set of data to help understand yield effects. I was lucky to speak with Bill Clark who works in Semiconductor Process and Integration Engineering at Coventor after the SPIE conference. He explained in more detail how this data was prepared. The resist masks came over from Panoramic’s Hyperlith as STL files. Then in Semulator3D they used the Expiditer option to perform batch runs on the dose and focus values with SWA Variation. The output is available in CSV for further processing as needed. Or as you can see the results are available to examine visually.

According to Bill, this demonstration shows a unique approach to better analyzing effects that occur during lithography and fabrication. Hopefully using analytical software in this fashion will help improve visibility into the manufacturing process with the goal of improving yield.

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FD-SOI Foundry

FD-SOI Foundry
by Paul McLellan on 03-16-2015 at 7:00 am
Categories: FD-SOI, Foundries, STMicroelectronics

At the end of last month during ISSCC there was a forum organized by the SOI Consortium. It took place in San Francisco at the Palace Hotel (which, if you have never been there, is famous for converting its old entryway for carriages into an amazing dining room, and for a bar with a huge painting by Maxfield Parrish of the Pied Piper valued at over $5M, up a little from its original price of $6K). There were presentations on:

  • FD-SOI advantages for applications and ecosystem, Philippe Magarshack, STMicroelectronics
  • 28FD-SOI: Cost effective low power solution for long lived 28nm by Kelvin Low, Samsung
  • Synopsys FD-SOI IP Solutions, Mike McAweeney, Synopsys
  • FD-SOI: Ecosystem and IP Design, Amir Bar-Niv, Cadence
  • FD-SOI Promises for 100Gb/s and Beyond Optical Transceiver, Naim Ben-Hamida, Ciena
  • 28nm FD-SOI Design/IP Infrastructure, by Shirley Jin, Verisilicon
  • Driving Profitable Innovation and Rapidly Growing Ecosystems with a Semiconductor Start-up Incubator,Mike Noonen, Silicon Catalyst
  • RFSOI: Redefining mobility and more in the front-end, Mark Ireland, IBM
  • Towards a Highly-Integrated Front-End Module in RF-SOI using Electrical-Balance Duplexers, Barend Van Liempd, imec
  • RF SOI: from Material to ICs – an Innovative Characterization Approach, Mostafa Emam, Incize
  • ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration, Laura Formenti, STMicroelectronics
  • SOI: An Enabler for RF Innovation and Wireless Market Disruption, Peter Rabbeni, GlobalFoundries

There was also a panel discussion moderated by our own Dan Nenni.

See also RF on SOI at GF


When FD-SOI was first being talked about it was perceived as a purely STMicroelectronics initiative. The whole world was going FinFET except for ST. But since then there have been a regular stream of announcements as the ecosystem expanded. GlobalFoundries announced that they had licensed FD-SOI in 2013 (but have not really said anything since). Samsung announced that they had licensed FD-SOI in June last year just before DAC. In January at the Tokyo forum Sony announced a chip they had built on FD-SOI. At Embedded World Freescale (soon to be merged with NXP) announced they were designing chips in FD-SOI. And on Dan’s panel Cisco discussed their own experiences. Ciena also presented their experiences at the San Francisco forum.


Since Samsung are a foundry, Kelvin Low’s presentation was one of the more important. If FD-SOI is going to be relevant then it needs to have availability from multiple sources. Samsung are clearly looking at 28FD-SOI as an extender for planar 28nm:

  • lower power
  • similar manufacturing cost (FEOL is simpler, which offsets higher substrate cost; BEOL is identical)
  • cheaper cost per transistor than FinFET
  • higher performance
  • easy port of designs from planar

These attributes make it a great basis for internet of things (IoT) applications which do require low power but don’t need the complexity of 14/16nm FinFET.

Kelvin said that the process had passed wafer level reliability (WLR) qualification in September last year. Samsung themselves are providing the foundation libraries and basic IP support. IP vendors are providing higher level IP (much of it at the RTL level of course) and design partners are providing ASIC design services.


All the presentations from the forum are here (or will be, some are not yet received).

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Apple Leaks Chip Sources?

Apple Leaks Chip Sources?
by Daniel Nenni on 03-15-2015 at 10:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

Take a look at the figure below and tell me this information did not come from inside Apple. The question is: Was it voluntary or involuntary? Inquiring minds want to know! There are some minor surprises which I will get to in a minute but the actual source information is spot on to what I have heard the past few quarters. This spicy little piece of information comes from the SemiWiki Semiconductor Process Technology Forum by the way. SemiWiki has always been about crowdsourcing and you will not find a better semiconductor crowd than on SemiWiki.com, absolutely.


In the fabless semiconductor industry there is always a lively debate on who will supply chips to whom. For Apple at 20nm it was TSMC versus Samsung. The Taiwan Press said TSMC and the Korean Press said Samsung. Even after it was clear that TSMC had won the A8 business the Korean press still said Samsung was supplying 20-30% of the chips. The Apple A9 has been all over the map. My prediction was that Samsung would get the A9 since their 14nm LP was ahead of TSMC by 3-6 months and TSMC would get the A9x which jibes with the figure above. I also believe that TSMC has the A10. Samsung having the A10x with 10nm is news to me. It was my understanding that Apple was still evaluating 10nm processes. The 10nm PDKs just came out so I would not bet on this one yet.

The other surprises for me are with the specific process nodes. The A9x should not be using TSMC 16nm, it should be TSMC 16FF+, and the A10 should not be 16nm FF+, it should be a new and improved Apple “tuned” version of 16nm. One interesting note, GlobalFoundries is mentioned as a second source for 14nm but not 10nm and obviously Intel Custom Foundry is nowhere to be seen but more on that later.

Notice that the figure says iPad & MAC for the A9x and A10x? Not really a surprise. In fact, I say it’s about time! Sign me up for six of those as long as they are iOS compatible. I really, really, really am sick of Microsoft Windows!

For the Apple iWatch I agree completely. The S1 is a scaled down version of the A7 which is Samsung 28nm. Given that, it is easy to assume the S2 is a scaled down version of the A8 which is TSMC 20nm.

The baseband processors for the next two versions of the iPhones (iPhone 6s and iPhone 7?) are a bit of a surprise as well. Not the vendors so much (QCOMM and Intel) but the fact that Apple does not have them integrated into the A9 and A10 SoCs. To me this is a total technology fail on their part. And it is not only cost but also power and packaging. As THE leading SoC design company Apple should be publicly shamed for this unless I’m missing something here. Why would Apple not integrate the baseband processor like Qualcomn, MediaTek, and other SoC companies already have?

The takeaway I have from this figure is that Apple is intentionally splitting orders amongst the foundries, not necessarily based on technology, but for business reasons. Clearly Apple wants multiple wafer sources and they will do whatever it takes to make that happen.

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Will the IC Market Growth Rate Stagnate in 2015?

Will the IC Market Growth Rate Stagnate in 2015?
by Pawan Fangaria on 03-15-2015 at 7:00 pm
Categories: Foundries, Semiconductor Services

In my last blog here, I talked about last 30+ years of semiconductor IC market. While we have seen this market growing at CAGR of ~9% over last 30+ years, the CAGR of current decade is expected to be at just ~4%. Although the base size of the overall semiconductor IC market is quite healthy, expected to be at ~$378B by 2019, we cannot hope for high growth rate from here. My belief about this proposition becomes stronger when I see a detailed report about the growth of major product categories in IC market, published by IC Insights here.


This report shows that IC market growth in 2015 will be a tad below at 7% compared to 8% in 2014. And only 11 product categories out of 33 will show growth rate higher than the 7% average of total IC market. This is less of a worry than what is being revealed when I look at the relative growth of individual product categories between 2014 and 2015.

True, there is growth seen in automotive ICs, 32-bit MCUs that support driver information system and semi-autonomous driving system, and NAND Flash that support mobile systems. However, look at their growth rate figures in 2015 compared to 2014; they are just about 1 to 3%. Whereas there are others that are staying above average 7% growth rate of total IC market, but their growth rates in 2015 have declined significantly compared to 2014. DRAM growth has declined from 33% to 14%, Power Management Analog growth has declined from 16% to 8%, and Amplifiers/Comparators growth has declined from 11% to 7%.

If we look at the line below 7%, we see similar situation. Tablet MPU growth has declined from 9% to just 3%, Industrial Special Purpose Logic growth has declined from 10% to 5%. We do not see growth of any category rising except 16-bit MCU and Wired Communication.

An interesting inference from the data at the end of the table, where product categories with de-growth are projected, is that they are improving; improving in the sense that their de-growth numbers have reduced although they are still in negative. Only Wired Communication – Application Specific Analog has dramatically recovered from -30% to 2%.

Looking at these figures, I think we are going to see ~5% CAGR in future, 5-10% in good times, 0-5% or even negative in bad times. It may be open to debate as we have not seen the IoT market yet. Automotive market is supposed to be the leading one in terms of percentage growth; the initial numbers of automotive ICs in 2014 and 2015 are here to see!

Can we say the IoT market will bring high growth rate of more than 10% CAGR? I do not think so. IoT itself will grow at a rate of ~22%, but that may take a decade to become a critical mass in itself to become a deciding factor. The semiconductor market with the reference of IoT can be better discussed after this decade. Comments welcome!

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Lake Tahoe: The Center of ESD Innovation

Lake Tahoe: The Center of ESD Innovation
by glforte on 03-15-2015 at 1:00 pm
Categories: EDA, Siemens EDA

Almost anyone that is active in IC design will be “in touch” with Electrostatic Discharge (ESD) at some time (pun intended). Preventing ESD related IC failures remains something like black magic—at least it’s easy to get that feeling when you are trying to debug ESD failures. I/O and ESD layouts that resulted in excellent robustness in one IC product might suddenly create havoc in a slight product variation. Designers have been hired and fired over ESD.

Have you run into an ESD related problem recently? What did you do: check with a colleague, the internet, online forums, or your old university courses notes on semiconductors?

Worry no more! Every year the world’s experts on Electrostatic Discharge gather in a highly interactive conference called the International ESD Workshop (IEW). This year it’s at the majestic Granlibakken Conference Center and Lodge in beautiful Lake Tahoe, California from May 3 – 7, 2015. This setting provides the perfect opportunity for participants to meet in a relaxed, invigorating atmosphere and engage in discussions about the latest research and issues of interest within the EOS/ESD community.

The IEW facilitates interactions among industry leaders through invited seminars, technical sessions, special interest groups (SIGs), discussion groups (DGs), and invited speakers. This year the focus is on Power Management for EOS/ESD, and EDA EOS/ESD Tools Best Practices and Experiences, but many other topics are included as well.

Scheduled poster sessions form the core of the technical program. These are preceded by a brief introduction by the authors in a plenary “teaser” session. The teasers encourage participants to select the posters of greatest interest. Meet and chat with the authors, while you expand your knowledge and network in the subsequent poster discussion session. This format provides an ideal forum for learning and exchanging new ideas. Topics covered in the poster sessions include IC EOS/ESD design, verification, test, multichip and system level ESD.

The discussion groups, held in the evenings, are a unique part of our interactive workshop. While each EOS/ESD topic discussion is facilitated by an expert on the subject, the main discussion will take place among the DG participants. The discussion groups will address topics such as 3D-IC, ESD Compact (SPICE) Models, ESD FOS (From Outside to Surface), Latch-up Testing and other interesting topics. The IEW also provides a similar forum for Special Interest Groups (SIGs), on selected subjects that may extend beyond the IEW time frame. Some SIGs have been successfully meeting for several years.

A number of stimulating state-of-the-art EOS/ESD seminars and invited talks are also scheduled. Come and listen to presentations discussing power management, EDA best practices and other exciting topics. As a break to EOS/ESD discussions, and to provide an opportunity to enjoy the spectacular surroundings, an afternoon is reserved for recreation with fellow attendees. This is a great way to become better acquainted with your EOS/ESD colleagues.

Come and meet experts, share your views, ask questions, and extend your network with EOS/ ESD experts from industry and academia. Above all, learn how to efficiently deal with today’s EOS/ESD challenges and prepare for tomorrow in an informal and interactive atmosphere. We sincerely hope that you will join us in Lake Tahoe for the 2015 IEW to ensure that ESD is no longer black magic. http://www.esda.org/iew.htm

Matthew Hogan (Mentor Graphics), IEW 2015 General Chair
Bart Keppens (SOFICS), IEW 2015 Publicity Chair

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Shifting Chip Design Left!

Shifting Chip Design Left!
by Daniel Nenni on 03-15-2015 at 7:00 am
Categories: EDA, Synopsys

In the traditional sense “Shift Left” is the process of making things simpler in an effort to make things faster. Shift Left was the theme of theDVCon keynote last week delivered by Synopsys co-founder and co-CEO Aart de Geus which is right on topic when it comes to modern semiconductor design and manufacturing, absolutely.

KEYNOTE: Smart Design from Silicon to Software

In our current semiconductor design community, the word “change” is, to say the least, an understatement. From a dizzying array of emerging “smart” niche end-products to major market trend shifts to ecosystem reconfigurations at every level, the world around us is morphing at an unprecedented pace. The challenge for IC designers to keep pace has never been greater. The good news is that we’re up for it! In his presentation, Aart will address the business and technology trends that are stretching designers’ concerns beyond the traditional sand boxes of design and verification.

First you should know that more than 1,200 semiconductor professionals participated in this event which is an all-time high. I was there, it was packed, I ran out of business cards yet again. Synopsys put out a nice lunch with great speakers from Freescale and Xilinx but Aart stole the show of course and he stayed afterwards for questions which is nice.

The premise of Aart’s keynote is that design schedules are not really changing but more work is being done within the same schedules. The big change I have seen is what I call the “Apple Effect”. In order to get a bite of the billions of dollars of Apple semiconductor ecosystem business you must synchronize your product schedules to the yearly iPhone release date which is just in time for the holiday shopping season.

The entire fabless semiconductor ecosystem pretty much accommodates Apple now including chip companies, foundries, IP providers, and even EDA companies. I welcome this added discipline (no more slipping product schedules) but the added pressure is seriously stressing the ecosystem. What does not kill us makes us stronger, right?

The point of Aart’s keynote that resonated strongest with me, along with IP re-use, was the requirement of eliminating point tools to shift your design schedule left: “In order to shift left you must have predictability through a highly connected design flow”.This is something I have heard since the beginning of big EDA but it has yet to come true. That is of course before multi-patterning, FinFETs, full coloring, and who knows what other design horrors 10nm and 7nm will bring us. Well, I have a pretty good idea but that is another discussion all together. The bottom line is that synthesis must be aware of the entire “design coherent system” if you want to Shift Left in the coming process nodes.

Coincidentally, one of the most viewed wikis on SemiWiki is the EDA Mergers and Acquisitions wiki. It is a VERY long list now and as you will see Synopsys is actually many different point tool technologies (400 million lines of code according to Aart) integrated into a seamless synthesis driven flow. It will be interesting to see what new point tool companies will be at DAC this year. They certainly are a dying breed and that makes me wonder what the future has in store for EDA. Certainly not what I had predicted in my first blog ever: EDA is Dead.