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Vertical NAND Flash

Vertical NAND Flash
by Paul McLellan on 03-23-2015 at 7:00 am
Categories: Coventor, EDA

You may know that up until now NAND flash has been a planar technology. But just as with SoC processes where we have had to go vertical to FinFETs, NAND flash has reached the limitations of scaling in the 20nm nodes and is also going vertical. It is not just a lithography issue but there are also reliability and voltage scaling issues. The solution is to stack memory cells vertically, increasing cell density without needing additional area for the memory array. These approaches are called either 3D NAND flash or Vertical NAND flash.

Coventor have put together a solution based on Terabit Cell Array Transistor (TCAT) technology, using SEMulator3D to evaluate process variations in the NAND string formation, especially during channel etching and contact formation. This SEMulator model has been reverse engineered from publicly available information such as conference papers and published SEM images. SEMulator3D is a predictive 3D modeling platform ideal for this sort of analysis due to its predictive modeling performance and accuracy.


Each memory cell is a gate-all-around device consisting of a metal gate atop a charge-trap flash stack, surrounding the string’s polysilicon channel; a gate-last flow is used for integrating the metal gate. The gates of neighboring NAND strings are tied together to form horizontally-oriented wordlines, which can be accessed at the edge of the flash device through contacts arranged in a staircase-like structure. See the diagram above.

I talked to Sandy Wen of Coventor about the new white paper that she has written on this work. Before joining Coventor, her background was in process equipment, in particular etch, where she worked for Applied Materials and for LAM Research. She is about to start a new project since her maternity leave starts imminently.

So how do you build such a complex 3D structure? The details are all in the white paper but the 50,000′ view is in the pictures below.

Using the model it is possible to investigate stability, sensitivity, and yield issues. For example, a parallel DOE of 180 runs was executed using SEMulator3D’s Expeditor batch processing capability. Etch process parameters such as nitride taper, lateral etch bias and oxide-to-nitride selectivity were varied, and the resulting channel cross-sectional areas were measured.The resulting virtual metrology data demonstrated the narrow process window for this cyclic etch. To ensure the channel etch reaches the bottom contact, the sidewall angle for each nitride layer must be maintained at 89° or 90°, while the polymer removal must be kept high enough to enable the etch to reach the bottom. When the sidewall angle for the nitride is 88°, the channel etch does not reach the contact bottom, and it has zero channel-to-ground contact area. In contrast, increasing the lateral etch bias in the polymer removal cycle can ensure that the etch reaches the channel bottom, but it comes at the expense of dimensional expansion at the top of the plug, another unacceptable feature.


If this was a real process being designed, rather than a model that has been reverse engineered, this sort of analysis using virtual metrology would save a huge amount of wafer-processing resources and, since it doesn’t require a full cycle through the fab, is also much quicker in getting defining the boundaries for the various parameters for train-and-error processing using real silicon. This is just one of the areas investigated in the white paper.

The bottom line is that, as with all advanced processing such as FinFETs, the interactions between different modules and understanding defect evolution has become increasingly difficult. Virtual fabrication techniques allow issues to be anticipated early, reducing development time and saving silicon runs.

The white paper can be found here.

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Apple’s Ax Chronicle

Apple’s Ax Chronicle
by Majeed Ahmad on 03-22-2015 at 7:00 pm
Categories: EDA, Mobile

In April 2008, Apple baffled the semiconductor industry by acquiring the system-on-chip (SoC) pioneer PA Semi for US$278 million. The acquisition, took place at the height of the iPhone fever, left the technology and trade media with an endless suite of guessing games. In the end, it was just about Apple’s quest for having better chips for the mobile devices.

PA Semi co-founder, Dan Dobberpuhl, was a pioneer in microprocessor design and had contributed to the landmark T-11, Alpha and StrongARM processor developments at DEC. After leaving DEC in 1998, He had founded SiByte, which developed the first multicore SoC device and was later sold to Broadcom for US$2 billion.


Dobberpuhl’s PA Semi served as a foundation for Apple’s SoC ambitions

When Apple unveiled the iPad in January 2010, Steve Jobs specifically called A4 the best and most complicated chip that Apple had ever designed. Initially, industry observers perceived the A4 as just another SoC that hooked up various IPs available from different companies. But then in April 2010, The New York Times reported that Apple has acquired the Austin, Texas-based chipmaker Intrinsity for an undisclosed amount.

That was about the time when people in the semiconductor industry connected the dots and began to understand Jobs’s claim of Apple’s long-term processor strategy for the iPhone and iPad. The story about the making of Apple’s first in-house SoC goes back to September 2008 when Samsung inked a deal with chip design house Intrinsity to develop a FastCore version of the Cortex-A8 which they called as Hummingbird. Meanwhile, Apple was looking for a way to speed up the Cortex-A8 CPU for its upcoming iPad.

According to some industry reports, Samsung asked Intrinsity to develop a FastCore version of the Cortex-A8 for Apple’s for A4 while utilizing it for its S5PC110 and S5PV210 chips after splitting the cost. Hummingbird was a ground-up, cycle-accurate, high-performance remake of ARM’s Cortex A8 architecture to get the CPU core’s clock speed comfortably up to 1GHz. The ARM-based small chip shop from Texas had brought to Apple that PA Semi couldn’t: a CPU core.

Apple A4 SoC: In January 2010, Apple introduced the A4 chip manufactured at 45nm process; it incorporated clock speed and RAM data bus enhancements that enabled it to drive the increased resolution of iPad. The A4 chip combined a single Cortex A8 CPU core to a single-core PowerVR SGX 535 GPU and either 256MB or 512MB of RAM. Apple also put the A4 chip in iPhone 4 and Apple TV.

Apple A5 SoC: In March 2011, when Apple introduced the more powerful iPad 2 device, it was powered by the dual-core A5 chip that featured twice the CPU power and eight times the GPU performance of the A4 chip. The A5 chip married a dual-core Cortex A9 CPU with a dual-core PowerVR SGX 543MP2 GPU and 512MB of RAM. It was subsequently used in the iPhone 4S handset and the iPad with Retina Display.

The progression from A4 to A5 revealed Apple’s strategic focus on the GPU part

Apple A6 SoC: in September 2012, Apple shipped iPhone 5 with A6, a new chip featuring an entirely custom “Swift” core design and manufactured at 32nm process. The A6 SoC married two of Apple’s custom-designed Swift CPU cores to a triple-core PowerVR SGX 543MP3 GPU and 1GB of RAM, roughly doubling the performance of the A5 in every respect. The most striking feature of A6 SoC was the in-house designed CPU: Swift.

Apple A7 SoC: In September 2013, nearly three years of releasing its first custom A4 chip, Apple launched the first 64-bit ARMv8 A7 chip using an entirely new Cyclone core design and a 28nm process. Apple, now a competitive chip designer, made a shift from Swift CPU core to Cyclone CPU core, which made the A7 chip look more like a desktop processor. The Cyclone CPU architecture had made a leap forward from small core CPUs commonly used in mobile devices to large core CPU found in desktop computers.

Apple rocked the industry by moving to 64-bit roadmap for mobile SoCs

Apple A8 SoC: The semiconductor industry was still coming to terms with the wonders of 64-bit computing that Apple had showcased in the form of A7 chip when Apple took another leap of faith in the SoC religion. The Cupertino-based computing giant announced the second 64-bit chip called A8 at the launch of iPhone 6 and iPhone 6 Plus on September 9, 2014.

A prominent highlight in the launch of A8 chip was Apple’s move away from Samsung’s fab to TSMC, something widely anticipated in the industry amid Apple’s increasingly complicated relationship with Samsung. The A8 SoC was about 25 percent faster than its predecessor in CPU tasks and 50 percent faster on the GPU side of things. It was also 50 percent more power efficient than the A7, and despite almost doubling the transistor count, the die size was nearly 13 percent smaller.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

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Intel and the Intel-of-Things

Intel and the Intel-of-Things
by Tom Simon on 03-22-2015 at 1:00 pm
Categories: EDA, IoT, Mobile

When I joined Calma in 1982, Intel was a small company making microprocessor chips in a crowded marketplace. They had scored big with IBM who was using their 8088 in the very first personal computer. Wind River was a hatchling with David Wilner and Jerry Fiddler working out of a rented warehouse in Berkeley – I know, I hung out with them back then. And, the internet was something Universities used.

Things have come a very long way indeed. Now, of course Wind River is part of Intel, and the internet is, well, everywhere. In fact, it’s likely that you would have a panic attack if went out without your phone and had to endure an hour or two with no internet. Despite all that has changed and developed in the intervening years, there is more to come, much more.

The internet of things is upon us. Lots of companies are generating marketing buzz around the internet of things, and Intel has put out a white paper that presents a preponderance of evidence that it really should be the Intel of Things. The paper pretty exhaustively makes the argument that everything needed to construct the internet of things can be sourced from Intel.

Remember when they were a hardware company? No so anymore. In reading the paper I was struck by just how far afield they have collected offerings. For instance, while John McAfee himself is sliding into the abyss, his namesake company, now part of Intel, figures prominently in Intel’s IoT strategy, offering key security software. McAfee Embedded Control limits what code is whitelisted, ensuring no malicious code is run. The white paper mentions McAfee Endpoint Encryption as the cornerstone of data security. McAfee Integrity Control provides auditing and compliance information. Lastly, McAfee ePolicy Orchestrator provides central security management.

Intel also reviews their processor line up, for use from sensor control and fusion, to up to server class Xeon cores for building the cloud backend. One of their strong arguments is that there is a great deal of code compatibility across Quark, Atom, Core and Xeon families. And even though Wind River started out as an embedded RTOS company, they now provide OS’s for each link in the IoT chain.

Intel defines the links in the chain as “things”, gateways, network infrastructure, and the cloud. Wind River can still provide bare metal RTOS, to Linux, all the way through code stacks to implement heavy duty network layers on network and cloud hardware. In the cloud layer for application development Intel has acquired companies like Mashery and Aepona for API management and monetization. Clearly Intel wants to play in the software space.

It’s unlikely that a company developing an IoT offering will go whole hog and use everything from Intel, but it is impressive how many pieces they have put together. Even so, while they are strong in processors and networking, sensors are another key area for IoT devices. But the bigger question in my mind is how much is the internet of things like the internet itself? Or, in other words, how much of it will be developed vertically by one company, versus a mosaic (no pun intended) of contributions that add up to larger whole?

To answer this I’d like to come back to my FitBit for a thought experiment. It is a device (aka thing), and it talks to the Fitbit mothership, but how much of all the stuff in the middle does FitBit care about? Well, rightfully, it is agnostic as to what kind of phone I have, or even what kind of Bluetooth chip that is inside my phone. Also does my Fitbit care what embedded OS the network switches at Verizon’s backbone use? It’s impressive that Intel has all this capability. But will there even be one Intel customer that will get it all? Probably not. But if so, what could make it such that everything provided by Intel was used, versus the implied balkanization that the internet offers?

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Wow: Synopsys v. Mentor Update!

Wow: Synopsys v. Mentor Update!
by Daniel Nenni on 03-22-2015 at 7:00 am
Categories: EDA, Synopsys

As a reminder, the Synopsys v. Mentor drama started when Synopsys filed a Complaint for Declaratory and Injunctive Relief on the same day (September 27, 2012) as they entered into an agreement to acquire emulation provider EVE (ZeBu emulator systems), which competes with Mentor’s Veloce family of emulators. Apparently, upon hearing about the EVE acquisition, Wally warned Aart about the alleged patent infringements by EVE and Aart’s response was swift legal action. This is the standard Synopsys legal strategy of “the best defense is a good offense”. Aart must be a fan of famed boxer Jack Dempsey. A better strategy would have been to mediate or settle since, with the recent ruling, this could cost Synopsys in excess of $100M dollars when all is said and done.

Take a quick look at thePermanent Injunction ruling of March 17, 2015. The infringement part is over, EVE infringed on Mentor U.S. Patent No. 6,240,376. The question now is damages. One thing that struck me after reading this is that the judge has a much better understanding of our industry than my previous experiences. Here is a link to one of those previous experiences:

Magma Avoids Trial by Settling Contract Suit With Prolific

That one taught me that, within the fabless semiconductor ecosystem anyway, it really was all about who had the better/most expensive lawyers since technology was baffling and using a fire hose of technical jargon was the underlying strategy for getting the most billable hours. Now the judges are much more technology enlightened and much less tolerant of fire hoses and “baseless” legal actions. This one however is the first time I have read a ruling that accurately described the ever important concept of “design wins” in our industry, absolutely.

Now let’s talk about damages. Paul Mclellan made a comment on the most recent Mentor quarterly conference call in regards to emulators that caused a “forward outlook” concern. Emulation is more critical now than it has ever been for SoC design so what is the problem here? From the transcripts Q&A section:

Wally Rhines – CEO, We were able to grow our emulation revenue this past year, but as noted, we had contribution from a large customer, which we don’t expect to have in the coming year. But we do expect that we can probably grow emulation revenue in the year ahead, the year we’re currently engaged in, in fiscal ’16…. Because we are making up for a loss in some of the momentum, we still believe that we will have overall growth but we’ll be swimming uphill in that respect…

If you look back at the ruling it specifically mentions Intel so let’s assume Intel is the large customer Wally mentioned. Intel is the industry’s largest emulation customer and coincidentally a big customer of EVE. The previous award of $36M was based on a 5% royalty fee on past sales. Moving forward the royalty will be tripled to 15% based on the fact that Synopsys knew of the patent infringement and continued sales . And don’t forget about legal and other expenses.

Let’s face it, Wally is a very clever man and he knows how Aart does business. He spoke with Aart prior to the EVE acquisition for a reason, he made the above comment for a reason, and getting Synopsys to file first was pure genius. It all goes to damages and they are going to be big, just my opinion of course.

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SoCs in New Context Look beyond PPA

SoCs in New Context Look beyond PPA
by Pawan Fangaria on 03-21-2015 at 7:00 am
Categories: EDA

If we look back in the last century, performance and area were two main criteria for semiconductor chip design. All design tools and flows were concentrated towards optimizing those two aspects. As a result, density of chips started increasing and power became a critical factor. Now, Power, Performance and Area (PPA) are looked together as the prime criteria for SoCs. Since the beginning of this century the semiconductor industry (including technology, design and software) worked tremendously to optimize PPA for semiconductor chips; the latest technologies being FinFET and FD-SOI.

Today, we have started seeing temperature as a key criterion for consideration in the semiconductor design. Like PPA, temperature acts as a basic criterion at the device and chip levels. We are seeing state-of-the-art tools in the market for thermal analysis of chips and packages. Temperature is a key criterion for hand-held mobile, automotive, and storage devices and therefore for SoCs in that space.

While PPA and temperature (PPAT) definitely need to be looked at as the base criteria, my emphasis in this article is to look at the SoCs in a new context today where there are other major factors which can dominate over these basic criteria; in fact some of the other major factors effectively drive the PPAT for SoCs. There is already lot of work done for PPA and is on the table to be exploited and used in the larger context of SoCs. So, let’s look at the major factors which drive modern SoC design.

Target Segment: The days when one particular processor like IntelPentium used to address most of the computing market needs around the world are no more. Today, we have multiple segments within one market. For example, within computing or processing space, we have desktops, laptops, tablets, smartphones, and so on. Each of these addresses a particular segment in the computing space and can have varying needs. A desktop processor can be less power efficient than a tablet or smartphone processor. Similarly, an SoC for automotive application can be less area efficient than an SoC for smartphone. Again, even for a particular segment it’s not one market across the geography, the markets are further segmented across the geographical regions. A live example is about smartphone markets in USA, China, India, and so on; they are different. Hence, an SoCs should to be planned according to its target segments for what is needed in that segment, and more importantly for how long that design can survive in that market. Otherwise, you may provide the best PPA, but it can still fail in a particular market. Again, power and performance have to balance against each other; today there is no more leeway to gain on both fronts without cost and other implications.

Cost: Today, cost no longer rules the market. The market drives the cost. At the same time, wafer cost at lower nodes is increasing to an extent that the cost per transistor may not reduce substantially with further technology scaling. So, the SoCs need to be architected with appropriate functionality according to the market need and the cost which it can absorb. It’s extremely important to plan the BOM (Bill of Material) upfront according to the cost and profitability. An SoC with similar functionality can have variants with different fabrics and PPAs for different markets according to their cost structures. A recent example is about Qualcommlaunching its mid-range lines of 4G baseband processors, Snapdragon 618, 620, 415 and 425, specifically to compete in China market where MediaTekis aggressively gaining in 4G LTE chipset market with its low priced chipsets. Also, Intel is eyeing emerging markets with its low-end SoFIA processors. The upcoming IoT market will further establish ‘cost’ as a major factor for SoCs, because ‘low-cost and high-volume’ will be the key characteristic of various segments in the IoT market.

A more important observation related to cost, as I see it from business angle, is that the companies (or divisions in large companies) need to be swift in aligning their product line, R&D, procurement, and manufacturing processes according to the market segment they serve; otherwise they can never meet the cost structure of the market. It is okay for Intel to initially indulge in the so called “contra-revenue model” to gain mobile market share, but gradually, rather rapidly, it has to align the mobile product line according to the cost structure of that market.

Functionality: After firming up the top level business strategies for target segment and cost, the actual stage comes where an SoC is architected according to the requirement and driven to implementation. The functionality must come as the top consideration in implementation because that will justify the cost and target segment as explained above. One has to consider, what kind of CPU and with how many cores should be employed, is a GPU required, how much on-chip and expandable memory should be sufficient, memory controllers, interfaces, communication components, and many more. Today, there can be hundreds of functional components on an SoC and there is a lot to choose from for each component. This mandates to decide on the functionality you are going to support for a particular segment at a particular cost.

IP integration: Once the functionality is defined, not all components can be done by one company. There comes IP for various components supplied by vendors across the world. So, here the actual exercise is to choose the best PPA optimized IP for your SoC and best integration methodology for overall PPA optimization of the SoC. This optimization is at a different level where you have to architect the data traffic and communication between different components in most optimized manner to consume lowest power and have lowest latency with minimum congestion in the network. There is Network-on-Chip (NoC) available which can be utilized to manage traffic and minimize power consumption of the overall SoC. Here is an example of how Texas Instrumentsused ArterisFlexNoC in its SimpleLink Wi-Fi Family of SoCs for internet-on-a-chip solution for IoT market in home automation, safety and security, energy harvesting, industrial M2M and wireless audio streaming. This is well architected with NoC fabric to work at extremely low power. The NoC is utilized to shut down the components which are not required for a particular mode of the chip’s operation.

[Courtesy Texas Instruments: TI CC3100 Hardware Overview]

This is a very simplistic, but smart design. Imagine a design where there can be several digital and analog components and high speed interfaces that connect wires getting into and coming out of the analog IPs at different levels of voltages. The floorplanning of those IPs, IOs and busses are critical along with the software that can model the channels in the floorplan. Also, while selecting an IP, looking at its PPA in isolation is not sufficient. There can be situations where more IPs when combined together can produce innovative results. Let’s keep that aside for a more detailed article later.

System Performance: It you count on a CPU performance, it’s simply the product of IPC (instructions executed per clock) and the clock frequency. With the technology scaling, clock frequency has almost reached its limits; although with significant increase in leakage power at lower technology nodes. Also frequency itself has implications on power. The other avenues to increase CPU performance by increasing IPC include techniques such as ILP (instruction level parallelism). Several other techniques such as SIMD (Single Instruction Multiple Data) have been used to reduce the number of instructions for a task.

That was the case for a single CPU. Today, we need to look at the performance in terms of the whole system’s performance. The CPUs can have multiple cores which provide high performance with optimized power. However, to exploit the multi-core architecture, several aspects have to be considered in the SoC design. These aspects may include the number of cores ideal for an SoC requirement, special cores for graphics, speech recognition, communication protocols, cache subsystem architecture, RAM (Random Access Memory), memory access mechanisms, and so on. So, one has to consider actual definition of performance as “time taken to execute a task” and consider the complete system performance while designing an SoC. Also, considerations have to be made for how different types of software would make use of the multiple cores.

Size: The size of a chip should not be confused with the density of transistors a technology node can provide. It’s the architecture and space utilization on the chip that matters. So, it’s the absolute size of the chip which needs to be considered; can it be architected with required functionality within the parameters of the size for a particular market segment. If a robust architecture can satisfy the size with the required PPA at a higher technology node, then that’s the best scenario. One does not need to use lower node process unless essential. In cases of GPUs where there are parallel workloads, higher density of transistors (and hence lower technology nodes) can definitely improve performance almost linearly; so lower technology should be considered there. From a business perspective, size can be extremely important in wearable segment of mobile and IoT market. So, size of the actual SoC is an important criterion to consider before architecting.

I would like to take a pause here as it is getting lengthy. However, there are other important and interesting criteria to consider for SoCs (e.g. h/w, s/w, embedded and so on). I will talk about those later in part-2 of this article.

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Silvaco Swallows Invarian

Silvaco Swallows Invarian
by admin on 03-20-2015 at 7:00 am
Categories: EDA

Yesterday, Silvaco announced that it has acquired Invarian Inc. Details of the transaction were not disclosed.

Who is Invarian? They are a recognized leader in block-level to full-chip sign-off analysis for complex, high-performance ICs. Their unique methodology utilizes a parallel architecture and concurrent power-voltage-thermal analysis to provide engineers with fast, accurate, and consistent results from the gate level through the 3D package environment.

Invarian has several products, all under the InVar umbrella name:

  • InVar Pioneer Power, power analysis platform for custom and standard cell based designs
  • InVar Pioneer IM/ER, full visibility of supply networks from top-level connectors down to each transistor
  • InVar Pioneer Thermal, the industry’s largest capacity and most accurate thermal sign-off analysis
  • InVar Pioneer Macro Modeling, hierarchical modeling to enable fast full-chip analysis while maintaining true to life accuracy from IP and blocks to top-level design
  • InVar Frontier 3D Thermal, static and transient thermal simulator based on the variable splitting method for efficient prediction of temperature distribution for 3D ICs

Having great technology is a good start but on its own it is not enough, foundry support is also important, and given its gorilla status nowhere is as important as TSMC. The InVar product family is TSMC certified for 20nm and 16FF+ v0.9 to enable sign-off analysis accuracy for static & dynamic IR drop analysis and EM verification, and the collaboration is on-going to conclude 16FF+ v1.0 certification.


My old Cadence colleague Suk Lee, now TSMC’s Senior Director of Design Infrastructure Marketing said:TSMC and Invarian have collaborated to ensure that customers have confidence when they perform EM or IR-drop analysis. We look forward to continuing this collaboration with Silvaco with our advanced process nodes.

Today I met with Dave Dutton, Silvaco’s CEO. One piece of trivia I learned is that the Silvaco name was never intended to be the permanent name of the company, it just stands for “silicon valley company” and is not some clever acronym involving simulation, layout and verification. But company names are not always very deep: Apple was supposedly so-named primarily to be alphabetically ahead of Atari.

Another thing he told me is that after several years of absence Silvaco is going to be back at DAC with a 600 square foot booth (#532 for those of you making really early plans). It is no secret that Silvaco’s founder Ivan Pesic, before his unfortunate death, was not really a believer in marketing (except billboards) and as a result Silvaco’s visibility in the industry is a lot less than it should be for a company of their size. Some people are surprised to discover that they even still exist, let alone that there are market segments in which they are the leader. Amit Nanda, the VP marketing, joined us in the meeting: it is his job to change that perception.


There is already some level of interoperability. For example, the above diagram shows co-simulation using Silvaco’s SmartSpice with Invar Electrothermal co-simulation.

The Silvaco press release is here. The Silvaco page on InVar is here.

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Closure: Kilopass v. Sidense

Closure: Kilopass v. Sidense
by Daniel Nenni on 03-19-2015 at 11:00 pm
Categories: IP, Kilopass Technology, Sidense

The long running legal action between the top two NVM IP companies is now finished after close to five years of lawyering. By the way, I write about this stuff in hopes of limiting the future earning power of lawyers that prey on our R&D budgets. This one is significant because Kilopass was not successful in a patent infringement case and now has to pay for the associated legal expenses incurred by Sidense.

Justice is open to everyone in the same way as the Ritz Hotel. ~Judge Sturgess

As I mentioned before, in the U.S., parties in a lawsuit pay for their respective attorney fees which can be staggering. However, U.S. law allows the courts to shift the payment of the winner’s attorney fees to the losing party for “exceptional” reasons. Based on recent legislation “exceptional” now has a much less stringent definition as reflected in recent case law and Kilopass v. Sidense is one of those cases.

You can see the final ruling HERE. This is a must read for any IP company considering patent action against a competitor. The award is for attorneys’ fees in the amount of $5,315,315.01 and other expenses in the amount of $220,630.53. Mediation costs a fraction of that of course but you have to really put your ego in check for that to work. By the way, the court documented the associated legal fees and the hourly expense Sidense paid was between $275-$830 and deemed within reason. So that is what you can expect to pay for fancy San Francisco patent lawyering.

Both Sidense and Kilopass did what I hope is a final press release:

Judge Orders Kilopass to Pay Sidense $ 5.5 Million in Legal Fees and Costs for Baseless Patent Infringement Lawsuit
Ottawa, Canada – (March 16, 2015) – Sidense Corp., a leading developer of nonvolatile memory OTP IP cores, today announced that U.S. District Judge Susan Illston has ordered Kilopass Technology to pay Sidense $5.5 million for its “objectively baseless” patent infringement lawsuit initiated against Sidense in May of 2010. The fee recovery represents attorneys’ fees and associated costs.

Kilopass Focuses on Market and Roadmap Expansion After Sidense Patent Litigation
Kilopass Has Reserved the $5.5M Award, but Moving Beyond to New Business
SAN JOSE, CALIF. –– March 16, 2015 –– Kilopass Technology, Inc., a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP), acknowledges the recent ruling of the U.S. District Court awarding Sidense Corporation $5.5 million for patent litigation legal fees. Kilopass has set aside cash in the full amount of the award.

“We are disappointed in the ruling but, as customers and the market have the substance of the litigation behind them, so do we,” remarked Charlie Cheng, Kilopass’ CEO. “Operationally, we have been busy with 10nm-16nm nodes for OTP roadmap, low-power IoT challenges, and new memory technologies.”

My final thoughts in the form of a cartoon:

Absolutely.

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Full Spectrum Analog FastSPICE Useful for RF Designs on Bulk CMOS

Full Spectrum Analog FastSPICE Useful for RF Designs on Bulk CMOS
by Tom Simon on 03-19-2015 at 1:00 pm
Categories: EDA, Siemens EDA

It has been about a year since the acquisition of Berkeley Design Automation by Mentor Graphics. Berkeley was doing quite well in the somewhat crowded SPICE simulator market. In many respects they broke new ground for high speed and accurate SPICE simulators. Since the acquisition we know that former Berkeley executives are now in significant roles at Mentor. Mike Ellow, former Berkeley Sales VP, is now Senior VP of Mentor’s World Trade Organization; and Ravi Subramanian, former Berkeley CEO, is now Mentor’s General Manager of the Analog Mixed Signal BU.

But more important than how the former Berkeley execs are doing, is how well the products from Berkeley are faring at Mentor.I had the pleasure of reading a white paper from Mentor on their Analog FastSPICE RF suite. The paper is written by two key members of the Berkeley team. David Lee was a co-founder of Berkeley Design Automation, and has a background that spans Bell Northern, Bell Labs and Lucent. The other author is Mick Tegethoff who has worked both in the semi industry and in EDA. He is responsible for marketing in Mentor’s AMSV business unit.

The paper, which can be found here, delves into the challenges faced by high speed analog designers who are increasingly required to work in bulk CMOS and at RF speeds. RF today really no longer implies just radio circuits: SerDes circuits often operate at over 20GHz – well above many RF circuits such as those in the 2.4 or 5 GHz range. The other problem facing analog RF designers is increasing complexity. The circuits have more devices, there are more circuits that must be analyzed concurrently (without making simplifications and approximations), and parasitics play an increasing role in circuit behavior and cannot be ignored.

As high speed analog circuits progress through the design process, their analysis needs progress as well. Estimated parasitics are added followed by device noise analysis and actual parasitics. Finally PVT variation needs to be considered as part of design verification. SPICE simulation is pivotal in each of these steps.

The Mentor white paper points out that Periodic Signal Analysis of near-linear circuits without sharp transitions can be analyzed using Harmonic Balance (HB) techniques. However designers must rely on time domain methods such as Shooting-Newton when the circuits have less linearity or have sharp transitions – which is happening increasingly. Nevertheless, achieving Periodic Steady State (PSS) convergence on the circuits is difficult for many traditional SPICE simulators.

Mentor’s AFS has unique abilities that let it work effectively on non-linear circuits in the frequency domain. First, it uses a Direct Solver, instead of a Krylov based solver for HB. This improves convergence and dramatically improves performance. Secondly, AFS is able to use a full spectrum approach. Instead of limiting the harmonics, it includes noise effects from all the sidebands or harmonics. This graphic from the white paper illustrates how full spectrum simulation in AFS gives better transient results.

There is much more in the white paper. It goes on to talk about Noise Floor improvements in transient sims. Other sections discuss Periodic Device Noise Analysis, Transient Device Noise Analysis, and full parasitic simulation. It closes with more information on circuit characterization, including PVT effects. Lastly it goes over their multi-core parallel operating mode for getting faster results.

Designing at RF frequencies, be it for an optical, RF or a copper medium, is an increasing challenge, especially in bulk CMOS with ever tighter design criteria and specifications. Analog circuit simulation is a mainstay of this process. Mentor appears to have brought on board some key technology as it grows its investment in analog RF design tools and expertise. If you want to read the full white paper, it can be found here.

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SystemC Co-Simulation of NoCs and IP Blocks

SystemC Co-Simulation of NoCs and IP Blocks
by Paul McLellan on 03-19-2015 at 7:00 am
Categories: IP, Sonics

Verification in general suffers from a couple of fundamental problems. Availability of models and performance of different levels of representation.

The first problem, availability of models, is that you would like to start verification as soon as possible but all the representations are not ready early enough. Obviously it is impossible to verify the RTL before writing the RTL, but you may still need to do some simulation of the block to design other parts of the chip.

The second problem, performance, is that it is very difficult to get more than a factor of 10 or 20 out of a representation by discarding detail rather than using a completely different model. You can throw away as much detail as you like in a gate-level representation and you won’t get an RTL simulation. If SPICE simulations ran as fast as emulators then we might not bother with any intermediate representations but obviously they don’t. They can’t even get close to gate-level performance.

As chip design has morphed over the last decade or two from building everything from scratch to integrating IP blocks, the verification problem has got more complex. You would like to verify architectural level performance early in the design cycle. After all, there is little point in going to the effort of assembling the IP blocks if you can tell in advance that the performance will be inadequate.

Another verification challenge is to avoid consuming too much simulation bandwidth on the known-correct parts of the design in order to verify the parts that are still being validated. For example, doing RTL simulation of an entire SoC to validate a single block of RTL is not a good tradeoff of simulation resources.

Many, if not most, advanced SoCs now handle the connectivity of the IP blocks using network-on-chip (NoC) technologies such as those available from Sonics, ARM and others. This means that the IP blocks on the SoC are mostly interconnected through the NoC. One attractive level of simulation is using SystemC. There are actually multiple layers of SystemC although with careful design much of the code can be shared.


Sonics has been creating SystemC IP models since 2005. Initially this was just for performance modeling and functional verification of the NoC itself, but since 2010 they have also provided TLM 2.0 models with OCP/AXI sockets. These models provide their customers with architectural executables for performance/complexity tradeoffs, and also fast models to validate performance on realistic NoC traffic scenarios. This makes it possible to analyze things like bandwidth and latency versus system power, arbitration, buffer sizing and other factors that affect performance, power and area (PPA).

Sonics SystemC models are written to be cycle-accurate. The reason for this is that in a NoC, mico-architectural subtleties (such as missed cycles) can affect performance unduly. While other blocks on an SoC can be modeled approximately, interconnect performance is too central to give up accuracy. The interaction of the NoC with overall system performance is further complicated by features such as clock gating, automatic power-down and wake-up and that have major high-level effects.


Under the hood of Sonics models are equivalence checkers (EC) that ensure that the behavior of the hardware being simulated matches the protocols and catches blocks that “misbehave” and violate some aspect of the protocol (such as sending a message when they should not, or sending a message to an incorrect block). In essence, this compares behavior to the underlying reference model.

Modeling at this level allows co-simulation with models of the IP blocks at different levels, making good use of simulation cycles and allowing investigation to take place at levels from architecture down to RTL verification.


Sonics gave a presentation on co-simulating their NoCs with Cadence’s Incisive at CDNLive earlier this month. The presentations for this year’s conference are not yet on Cadence’s website, but the CDNLive page where they will presumably eventually appear is here.

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TSMC ♥ UMC?

TSMC ♥ UMC?
by Daniel Nenni on 03-18-2015 at 8:00 pm
Categories: Foundries, TSMC

The relationship between TSMC and UMC is one of the more interesting ones in the fabless semiconductor ecosystem in my opinion. Both are headquartered in Hsinchu Taiwan and it is very hard to visit one company without seeing the other as they have facilities right across the street from each other. They also share humble beginnings from inside the same incubator (ITRI) so to me TSMC and UMC are brothers.

Industrial Technology Research Institute is a nonprofit R&D organization (incubator) for applied research and technical services based in Taiwan. ITRI is credited with transforming Taiwan’s labor-centric economy into a technology powerhouse originating more than 260 companies including UMC and TSMC. In fact, UMC spun out of ITRI in 1980 as Taiwan’s premier semiconductor company. TSMC spun out in 1987 as the world’s first pure-play foundry and the rest is as they say history.

Having worked with both UMC and TSMC for much of my career I can tell you that they are two very different companies with unique business models. While TSMC has always been a leading edge company, UMC has perfected the “second source” foundry business model like no other. Chartered Semiconductor tried it and failed, SMIC tried it and is failing, Dongbu, X-Fab, Siltera, the list goes on and on… The jury is still out on GlobalFoundries but with the acquisition of the IBM Semiconductor business they have a legitimate claim to leading edge foundry technology, absolutely.

Unfortunately for UMC the foundry landscape has changed. With the re-entrance of leading edge IDM Foundries (Intel and Samsung) technology requirements are moving at a much faster pace and the Capital Expenditure requirements are well out of UMC’s reach. UMC’s CAPEX for 2015 is less than $2B while TSMC’s 2015 CAPEX is greater than $10B! This CAPEX explosion started at 28nm but with FinFETs (16nm and 10nm) plus new devices coming at 7nm the CAPEX requirements will continue to skyrocket as we desperately try to keep up with Moore’s Law.

What is UMC to do?

If you remember, at 28nm UMC joined the Common Platform Fab Club and licensed the IBM Gate-First implementation. Fortunately UMC changed to the Gate-Last version of 28nm which is used by TSMC and is now reaping the rewards of its continued “T-Like” compatibility. I do not see UMC licensing the Samsung version of 14nm like GF did so what choice do they have but to develop their own T-Like 16nm? With the help of TSMC and UMC shared customers: Qualcomm, Texas Instruments, MediaTek, etc…

The alternative of course is for TSMC to license the FinFET technology to UMC in a similar “copy exact” agreement to what Samsung and GF did. Morris change joked that this made GF Samsung’s “accessory” but as you may have read both Apple and Qualcomm pushed for this agreement so it needs to be taken seriously. There is no way the big fabless companies will be satisfied with just one foundry source moving forward. It is no coincidence that Apple is ping ponging between Samsung and TSMC, right?

So what do you think will happen here? Will TSMC help a brother out?

Also Read: Apple Leaks Chip Sources?