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ARM & Cadence IP Partnership for Faster SoC Design

ARM & Cadence IP Partnership for Faster SoC Design
by Eric Esteve on 03-18-2015 at 9:50 am

IP vendors always try to create differentiation, especially when designing protocol based IP. You can differentiate by building the most performing controller but you will probably miss the expectation of these customers who don’t search for performance but just compliance to a specific standard. Or the vendor may want to design features rich controller supporting every possible capability included in the protocol specification but in this case not addressing customer demand for a compact IP optimized for area and power…

What could be the common requirement, for customer designing SoC addressing various market segments like mobile, consumer, networking, storage, automotive and the Internet of Things (IoT)? Time-To-Market (TTM) is the answer! If you are able to provide pre-integrated IP solutions, not only silicon proven but also validated in a design environment similar to this your customer will follow, available on a single development platform, then you will bring TTM advantage through faster integration of the most important IP.

Designing a SoC means using foundation IP (libraries and memory compilers), integrating CPU and probably GPU core(s) and interface IP (USB, PCI Express, DDRn or LPDDRn, etc.). Cadence offers a wide interface IP port-folio, ARM Ltd is the CPU (GPU) IP core leader supplier (and also #1 IP vendor, by the way). If these two companies build an agreement based on pre-integration of their respective IP, running interoperability of these IP and going up to test chip design, such cooperation may really offer TTM advantage to SoC design team. Extracting from the join Press release, this sentence clearly describe the scope of agreement between ARM and Cadence:

“This multiyear agreement provides reciprocal access to relevant IP portfolios from the Cadence[SUP]®[/SUP] IP Group and ARM. Additionally, the agreement grants both companies rights to manufacture test chips containing Cadence IP and ARM IP and to provide development platforms to customers. The ability to test the IP interoperability in silicon is intended to enable Cadence and ARM to optimize performance and interoperability within systems on chip (SoCs) while accelerating time to market for customers in markets such as mobile, consumer, networking, storage, automotive and the Internet of Things (IoT).”

If you evaluate the TTM impact, it’s clear that this engineering time spent in advance by IP vendors to optimize performance and interoperability during the Test Chip integration phase just become a net time benefit for customer SoC design team. This team should shorten the design phase by an equivalent amount of time during SoC integration. Moreover, the agreement allows ARM (resp. Cadence) to design development platforms built around ARM (resp. Cadence) test chip integrating IP from both sources and to deliver this platform to ARM (resp. Cadence)’s customers.

As mentioned by Pete Hutton, executive vice president and president of product groups, ARM: “This agreement expands upon the successful EDA Technology Access and EDA Subscription Agreements ARM signed with Cadence last year to further enable our customers’ designs to reach peak performance and power efficiency.”

And Martin Lund, senior vice president, IP Group at Cadence points the TTM advantage: “This new agreement allows customers of both companies to get to market faster with pre-integrated IP solutions and continue pushing the envelope on low-power and high-performance SoC design.”

If we look back in the 2000’s the IP market has been completely re-engineered for quality: all the providers not able to meet customer demand for high quality IP have disappeared or been acquired. Then at the end of the 2000, the mantra became “Integrated solution” for interface IP and “one-stop-shop” for most of the IP. If one-stop-shop can help saving legal or purchasing resource, the impact on chip integration is weak.

IP vendors understood at the beginning of the 2010’s the need for providing development platforms, virtual prototyping and hardware prototyping systematically. The goal was to improve TTM by improving software development. Chip integration is the heart of SoC development but little has been done since 2000, or at function level (integrated interface IP and PHY and controller IP interoperability), but not at SoC level. This partnership between ARM and Cadence is one step beyond in the race for faster TTM as it helps improving the SoC integration itself, and this agreement is the first of this kind…

By Eric Esteve from IPNEST

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