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The Curious Case of Samsung’s Shannon Chips

The Curious Case of Samsung’s Shannon Chips
by Majeed Ahmad on 05-03-2015 at 1:00 pm
Categories: Foundries, Mobile, Samsung Foundry

The recent teardowns of Samsung Galaxy S6 smartphone have one thing written all over them: Samsung is doubling down on its logic business. Although most of the technology press coverage went to Exynos 7420, the first mobile SoC manufactured at the 14nm FinFET process, Samsung’s other logic chips inside the S6 handset equally deserve some attention.

Some teardowns reported that the S6 handset has used 16 Samsung chips out of a total of 25 semiconductor components. That makes roughly two-third of the silicon content from Samsung the chipmaker supplied to Samsung the smartphone manufacturer. Below are the notable chip appearances that hint about Samsung’s grand ambitions for the logic business:

Shannon 333: Baseband chip
Shannon 928: RF transceiver chip
Shannon 533: Power management chip
Shannon 710: Envelop tracking chip

Samsung has supplied two-third of silicon content in S6 smartphone

Shannon is the product family name for Samsung’s mobile chipsets. The massive scale of Samsung chips used in its premium smartphone just shows that the Korean electronics giant is now even more ambitious about its components business. Samsung’s semiconductor business comprises of memory and logic chips.

It’s worthwhile to note that Samsung’s gambit for logic chips isn’t new. The Suwon, South Korea–based electronics firm has earlier used the Shannon-based RF transceiver, baseband and power management chips in its Galaxy Note 4 tablet along with in-house Exynos application processors.

A Brief History of Samsung’s Logic Chips

Samsung Semiconductor—the market leader in DRAM and Flash memory products for many years—got its first major breakthrough in the logic business in 2006 when it snatched the application processor socket from PortalPlayer in Apple’s hugely successful media player iPod. Next year, Samsung became the supplier of application processors for Apple’s game-changing iPhone.

Samsung forged SoC skills by producing custom application processors for Apple, and in 2010, the Korean tech giant launched its own application processor Exynos Single 3 in Galaxy S mobile phone. The Exynos family of mobile SoCs has come a long way in terms of horsepower, clock speed and power consumption over the years.


The site for Samsung’s new chip plant in Pyeongtaek

There are media reports that Samsung has started working on its own CPU cores as well as a custom GPU for mobile SoCs. Moreover, Samsung is planning to pump billions of dollars to build a new chip plant in Pyeongtaek, a city south of Seoul. The plant is expected to be complete in 2017. Currently, in South Korea, Samsung has memory-chip production lines in Hwaseong and facilities in Giheung that focus on logic chips.

Samsung’s Shannon Moment

Samsung is already a market leader in chip fabrication and has become a talking point after it surpassed TSMC by producing the first mobile chip at 14nm FinFET manufacturing process. Now take that FinFET flying start and the news about Samsung’s $14.7 billion bet on a new chip facility in the backdrop of the recent statement from Samsung Electronics Vice Chairman Lee Jae-yon.

Business Korea has reported that Lee is urging top Samsung executives to further boost Samsung’s semiconductor design capabilities and has led them to initiate a number of ambitious silicon projects. Why, then, at the eve of this triumphant moment, Lee gave the marching orders for more semiconductor technology prowess. Here, two factors that deserve some attention.

First, Samsung, the world’s second-largest chipmaker after Intel, has been a market leader in both DRAM and Flash memory segments, and there is no imminent challenge on the horizon to its memory silicon market position. Second, with the Exynos application processors improving generation by generation, Samsung is already a key SoC player along with chip behemoths such as Apple, Nvidia and Qualcomm.


Shannon footprint is all over S6 phone teardowns

So where are Samsung’s new semiconductor industry initiatives heading? A simple answer could be Shannon. The Korean semiconductor giant hasn’t even made a formal announcement about its chipset architecture, and there are hardly any technical details available about the Shannon ICs. But the S6 teardowns clearly show that Samsung will mostly likely make a big push in the logic business other than application processors in the near future.

There are no indications if Samsung will target its Shannon ICs to outside customers at this time, but a sneak peek at its record points to a strong possibility that Samsung will eventually aim to supply sockets like baseband, power management and NFC controllers to other electronics OEMs. The Korea chipmaker has set in motion an ambitious roadmap for the logic business, and there could be more surprises in 2015 or 2016.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

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TCAD Enables Moore’s Law to Continue

TCAD Enables Moore’s Law to Continue
by Daniel Payne on 05-03-2015 at 7:00 am
Categories: EDA, FinFET, Synopsys

We live in very interesting times, you can wear an Android watch from Samsung that uses 14 nm FinFET technology, attend the 52nd DAC conference in June to learn about EDA and IP vendors supporting FinFET, and read about research work for new devices down to 5 nm. TCAD is that critical software technology that enables the development of new devices at 10 nm, 7 nm and even 5 nm. To get an update on what Synopsys has to offer in the TCAD space I spoke by phone with Tom Ferry last week, we both worked at a company called CrossCheck back in the 90’s. According to data from EDAC we learn that Synopsys is #1 in TCAD software.

Related – EDA Mergers and Acquisitions Wiki

Synopsys categorizes TCAD software as Silicon Manufacturing and places it into three segments:

  • Device and Process R&D
  • Mask Creation
  • Yield Management

Device and process engineers have used tools like Sentaurus TCAD and Sentaurus Lithography to define and optimize their 10 nm and 7 nm FinFET technologies, while at 5 nm the Nanowire FinFET is still at a prototype stage.

For my MacBook Pro laptop I replaced the hard drive with an SSD from Samsung and it uses a planar NAND structure, while the newest Samsung SSD use a 3D NAND structure. Both the planar NAND and 3D NAND structures are supported in Sentaurus today, while emerging technologies like ReRAM (Resistive RAM) and STT-RAM (Spin Torque Transistor RAM) are in a prototype stage.

Related – 25 Years of SNUG; 50 Years of Moore’s Law

IMEC is a leading research consortium and they’re collaborating with Synopsys to deliver a version of Sentaurus to enable design and optimization of 5 nm technology and smaller nodes.

Using 193 nm light sources to resolve feature sizes for smaller node sizes is a huge challenge that requires OPC (Optical Proximity Correction) and RET (Resolution Enhancement Technology) to print reliable features while not filling up your disks with mask data. Run time is the other bottleneck for running these OPC and RET tools. There are two approaches from Synopsys that meet these litho challenges using the Proteus software:

  • Proteus rigorous compact OPC models
  • Proteus Inverse Lithography Technology (ILT)

A rigorous model is based on physical parameters, which is essential to predict the behavior of new devices, instead of using empirical parameters. ILT is a technology started some 10 years ago, however at first the run times were 10X slower than OPC. The Synopsys approach is to selectively target where ILT gets used to the most critical design areas, providing QOR improvements with a smaller mask cost increase. This ILT technology came from the acquisition of Luminescent back in 2012. The Proteus ILT approach is being qualified for 10 nm mask flows now. Here’s where ILT fits into the mask synthesis flow:

To get the run times lower you use Proteus across a network of CPUs, it could even be thousands. Running a verification tool like Proteus LRC will find a hotspot, then the ILT will fix each hotspot locally so that you don’t have to run OPC and RET again on the whole chip.

Related – FinFET Design Enablement

The time required to write a mask is increasing, however it must be kept under a threshold for equipment reliability reasons.

The Proteus to CATS flow happens in parallel to help shorten this mask writing time. Another speed improvement comes from using the multi-beam mask writer from IMS, now supported by CATS.

There’s even a new mask writer machine from NuFlare called the EBM 8000 that uses variable-shaped beam equipment to reduce write times by 1.5X to 2.0X.

Once a new IC goes into silicon production the biggest question becomes one of yield, and discovering why a specific design has low yield. Synopsys has software called Excalibur running on inspection machines, locating failures in process that are design dependent. Outside of the fab test engineers can run the Yield Explorerand Camelot tools to perform failure analysis on an IC and then pinpoint the failure on a SEM (Scanning Electron Microscope). Inside of a fab they use the Odyssey software as a defect management system.

What makes Synopsys different in yield improvement is that they have connections across all three domains: Design, Fab and Test.

Conclusion

Synopsys has a strong history in the TCAD software business and their Sentaurus tool is used for 10 nm, 7 nm and 5 nm devices enabling Moore’s law to continue. Process window requirements are met with the Proteus ILT and modeling approach. Mask write times can be met with CATS fracturing. Give your Synopsys rep a call to find out more details, or visit at one of the conferences:

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TSMC 10nm Readiness and 3DIC

TSMC 10nm Readiness and 3DIC
by Paul McLellan on 05-03-2015 at 1:00 am
Categories: EDA, FinFET, Foundries, IP, TSMC

At the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!

Around the turn of the millennium Suk actually worked for me. In fact, he took over my job running marketing for IC, which is what Cadence called all of the back end tools for both analog and digital. After that he went to Magma (which of course was acquired by Synopsys). At the start of his career he had also, like me, worked for an ASIC semiconductor company, VLSI Technology in my case and LSI Logic for Suk, so we both have what I like to call “silicon in our veins”. That was followed by his first stint at Cadence before going back to semiconductor at Texas Instruments. He joined TSMC six years ago where he is now senior director of design infrastructure marketing, based in Taiwan.

First there are the new 28nm processes, 28HPC+ and 28ULP. 28HPC+ is for high performance, a speed gain of about 15% for the same leakage, or a reduction of 30-50% in leakage for the same speed. There are also new standard cell libraries for this process with 9 and 7 track libraries (compared to 12T/9T before). The 28ULP (for ultra-low power) process is for IoT applications with a lower operating voltage of 0.7V (versus 0.9V for 28HPC+). This new process joins the other two ULP processes 55ULP and 40ULP. There is also a library benchmarking kit to help design groups find the best combination of libraries to meet their target PPA.

The design flows are largely in place for both processes. The foundation IP is ready for 28HPC+ with other IP becoming available from now through Q1 of next year. A lot of the IP for 28ULP is still in the planning phase.

Next Suk talked about the 16FF+. The design flows and IP portfolio are all in place with almost everything characterized in silicon. At the event a new 16nm process 16FFC was announced. This is intended for cost-sensitive consumer applications. The foundation IP should be available in Q4 of this year, with interface IP coming in Q2 of 2016.

There was a lot of detailed information about 10nm which TSMC were talking about for the first time.

EDA tool support is as follows:

  • Automatic Place & Route: Synopsys, Cadence, Mentor
  • DRC: Synopsys, Cadence, Mentor
  • LVS: Synopsys, Cadence, Mentor
  • RCX: Synopsys, Cadence, Mentor
  • STA: Synopsys, Cadence
  • EM/IR: Synopsys, Cadence, Ansys
  • SPICE: Synopsys, Cadence, Mentor
  • FastSpice: Synopsys, Cadence, Mentor
  • Custom Design: Synopsys, Cadence

The IP library for 10FF is targeted at several different application areas: smartphone, tablet/ultrabook, networking, CPU/GPU/FPGA. The various IP very in their state of readiness from being full characterized from silicon test chips, or waiting for silicon characterization (but able to be used in design starts), to blocks that are still in development. In detail, IP for 10FF is available as follows:

  • Standard cell: silicon report
  • GPIO/ESD: silicon report
  • PLL: pre-silicon design kit
  • SRAM compiler: silicon report
  • ROM compiler: in development
  • Electrical fuse: silicon report
  • OTP: in development
  • DDR4: pre-silicon design kit
  • LPDDR4: pre-silicon design kit
  • PCIe: pre-silicon design kit G3 & G4
  • MIPI: pre-silicon design kit G2 & G3
  • SATA II/III: in development
  • 10G serdes: in development
  • USB 2/3: pre-silicon design kit
  • HDMI/MHL/DP: in development

The 3DIC technologies offer offer heterogeneous die stacking and packaging solutions for high speed, high density and low cost applications. There is thru-silicon-via (TSV) implementation with accurate modeling, an integrated 3D testing methodology, wide-IO interface signal integrity and chip-package-system thermal analysis. The design flow is completely ready, with design kits ready.


TSMC has the broadest IP portfolio in the industry with IP from 0.35um down to 10nm with nearly 9000 different IP titles.

The China Symposium is next week in Shanghai on 5/7 (in Chinese). European symposia are in Amsterdam on 6/16 and Herzliya on 6/29. The TSMC symposium page is here. There will be one in Yokohama but the date is not yet decided. But save the date 9/19 for the OIP Ecosystem Forum in Santa Clara. Details are here.

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Crossing the Chasm: From Technology to Valuable Enterprise

Crossing the Chasm: From Technology to Valuable Enterprise
by Daniel Nenni on 05-02-2015 at 1:00 pm
Categories: Events

One of the advantages of being an independent consultant is that I get to choose who I work with and what type of projects I accept. In fact, that is why I originally started blogging, to get exposure to a wide range of topics and brand myself as a strategic semiconductor business development professional. Now rather than wasting time looking for projects they come looking for me.

Some of the more interesting projects that have come my way are to help emerging companies with their foundry relationships. The larger EDA/IP and fabless companies have teams of people doing this but since I work with multiple companies at a time I get pretty good access as well. And let’s face it, that’s one of the reasons why I blog, speak at conferences, founded SemiWiki, and publish books. It’s all about getting access to the entire fabless semiconductor ecosystem from top to bottom, absolutely.

One of the more interesting projects was with Berkeley Design Automation working for Ravi Subramanian. Ravi and I spent quite a bit of time together in Silicon Valley and Hsinchu. He is one of the most inspirational CEOs I have ever worked with without a doubt. The results of our efforts included hyper revenue growth, TSMC becoming an AFS customer, a TSMC Customer Choice Award, a TSMC OIP Partner of the Year Award, and ultimately the acquisition of BDA by Mentor Graphics. One of my other clients (Tanner EDA) was also just acquired by Mentor Graphics as well so you might see a pattern here…

The reason why I brought this up, other than to brag shamelessly, is that my good friend Ravi Subramanian is being featured in the next “EDAC – Jim Hogan Emerging Companies Series” exploring concepts and best practices for emerging companies. This series was “inspired” by me by the way, since I’m already bragging. This is also a great networking event (100 people are expected). I will be there as will Paul McLellan and it would be a pleasure to meet you. If you have a copy of our book “Fabless: The Transformation of the Semiconductor Industry” we would be happy to sign it. If not I can bring you a copy. Let me know in the comment section.

This installment features a conversation with Ravi Subramanian, former President and CEO of Berkeley Design Automation, on “Crossing the Chasm: From Technology to Valuable Enterprise”.(Berkeley DA was recently acquired by Mentor Graphics Corporation.)

Jim and Ravi will explore his philosophies and experience on building two valuable and successful companies – one fabless semiconductor company and one EDA company.

Ravi Subramanian, General Manager of the Analog Mixed-Signal Business Unit of Mentor Graphics, and former President and CEO, Berkeley Design Automation. Ravi Subramanian is a respected technologist as well as an entrepreneur, with over 20 years of experience in the semiconductor, wireless communications, and electronic design industries. Ravi has been named on the Rutberg & Company’s Wireless Influencers list every year from 2006 to 2014. More information

Jim Hogan, Private Investor, Vista Ventures, LLC. Jim is currently the managing partner of Vista Ventures, LLC. Jim has worked in the semiconductor design and manufacturing industry for more than 40 years gaining experience as a senior executive and board director in electronic design automation, intellectual property, semiconductor equipment, material science and IT companies.

Register Now!
Admission is free but seating is limited

Participants:
Jim Hogan, Managing Partner, Vista Ventures, LLC
Ravi Subramanian, Former President & CEO, Berkeley Design Automation

Date and Time:
Wednesday, May 6, 2015
Reception: 6:00 PM – 7:00 PM
Conversation: 7:00 PM – 8:30 PM

Location:
EDA Consortium / SEMI
3081 Zanker Rd.
San Jose, CA 95134
(Map)

Organized By:
Steve Pollock, EDAC Emerging Companies Committee

Registration Host:
Marketing on Demand

Event Host:

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Why Intel will Never Succeed in IoT Market?

Why Intel will Never Succeed in IoT Market?
by Eric Esteve on 05-02-2015 at 4:18 am
Categories: Foundries, Intel Foundry, IoT

Let me precise that by “IoT” I think about the IoT devices market, made of hundreds of application, wearable gadget to medical, home automation, and so on. One direct consequence of IoT (device) market explosion will be the strong growth of the server market (cloud), to transfer, compute and store information generated by the billions of IoT devices. Intel is certainly the chip manufacturer being the best positioned to enjoy this server market explosion. But this is not the topic today. I clearly refer to the IoT device market, where system cost and power consumption are the first key parameters, along with security, wireless communication efficiency, etc. but let’s focus on cost and power. This post is also an answer to this article from Seeking Alpha: “Intel Is Mispriced And Positioned For IoT Growth”, written by a person probably very good when talking about the stock exchange market, but missing proper understanding of the semiconductor industry, especially when dealing with low power consumption and design for optimum (low cost) SoC integration…

Another useful precision: when I use “never”, I think “within 5 years”. If you look at the recent semiconductor history, it took 5 years to Texas Instruments (between 1999 and 2004) to enjoy revenues from wireless application processors passing from less than $1 billion to more than $5 billion. It also took 5 years to Qualcomm to kick out of this wireless business companies like TI, ST or Broadcom (between 2005 and 2010). In our industry, 5 years is equivalent to the infinite and when dealing with IoT, 5 years means in 2020…

I see three reasons why Intel will not be ready by 2020 to generate high revenue and high profit on IoT devices:

  • Intel’s wafer fab and Si technology are built for high performance process (and processor) rather than for low power process.
  • Intel design culture is directed to build high performance devices (server processors for example) not for designing for power efficiency (like can be Qualcomm).
  • Intel top management has grown in this “always higher performance” culture and managed the whole company on line with this culture.

The first two can’t be changed without first changing the last one. I don’t say that Intel top guys should be fired… but they will have to revolution their way of thinking to admit that power efficiency is much better than pure performance, at least if Intel want to be successful in IoT devices market (and in wireless mobile by the way). Let’s imagine that this revolution occurs and that Intel hire efficient managers with the right culture, like people who have been successful in developing application processors for smartphone application.

I am sure that Intel could find ex-Tiers or former Broadcom or ST employees with the right profile. How long will it take 1) to select and hire this people and 2) to give them the right level of power so they can effectively influence the process peoples? Intel is not really a start-up, rather a kind of mammoth, so 1 year is the very minimum.

Let’s assume that the right set of decision are taken to build new processes (I did not say new advanced process like 10nm, rather process based on 55nm or maybe 40 or 28nm), no more for pure performance but for power efficiency. Developing and proving these processes would probably take another 18 to 24 months (don’t forget that low power design is not in Intel culture, so Intel will have to come to a point it took 10 years for TSMC or TI to come to, process node after process node). Say 2 years.

Then, in parallel Intel will have to build completely new design teams (my opinion), managed by new gurus who know how to design a complete SoC for low power. Clock gating, power islands and probably other techniques will have to be used. At this point of time, a cleaver designer will say: Ooops! We don’t have the right processor core! Let’s buy a RISC (probably not ARM, but who knows…). Back in 2009, when TI was completing OMAP5 validation, I had numerous discussions with one of the TI program manager. I remember very well that he told me that OMAP5 validation was extremely complex, due to the low power techniques. If I remember well, it took more than one year after the prototype release to simply validate the chip. How long could be a complete design phase, starting with a new RISC core? I would say: 18 to 24 months (RTL design + P&R) + 3 months (prototype fabed) + 12 months for prototype validation and S/W integration. 33 to 39 months, say 3 years.

That makes a minimum of 4 years (1 + 3) before Intel can release a low cost, low power (new) RISC based SoC, running on Intel fab (don’t forget that the goal of an IDM like Intel is to fill own wafer fab, right?). Obviously, using ARM based SoC targeting TSMC (or Samsung) would be much more time effective, but does it really makes sense, from a business point of view?

Last point, I think I understand why these stock market analysts are confused. They know that Intel is good at embedded. In this case we talk about embedded x86 integrated into boards, like on this picture:


…when an IoT device will rather look like this system on board (WiPy from TI, but the web is full of similar systems):

Why such a confusion? Is it because an IoT system is by definition based on an embedded processor (here an ARM Cortex M4 core)? But an embedded system board from Intel has nothing to see with an IoT system, it’s just high performance, but high power processor mounted on a board, needing an expensive cooling system (see the picture). Such a board is not: cost effective (the cooling system cost is probably equivalent to the complete IoT solution from TI!) and even more crucial, is not power effective. IoT and more precisely wearable IoT should last at least a week if not a month between charging.

Maybe in 2020 Intel will be in a position to launch such systems, but many barriers will have to be broken in the meantime…

From Eric Esteve from IPNEST

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Fractal at DAC 2015 – What’s new?

Fractal at DAC 2015 – What’s new?
by Pawan Fangaria on 05-01-2015 at 1:00 pm
Categories: EDA, Fractal Technologies

I have been observing Fractal Technologiesexhibiting at DACyear after year, and every year they have demonstrated good value added features in their tools for SoC and IP development. This year at 52[SUP]nd[/SUP] DAC Fractal’s booth number is 1110. Earlier in this year Fractal had added a new ‘Cdiff’ feature in its flagship product Crossfire, for which I had bloggedabout their CTO, Johan Peeters’ views on this feature for accelerated quick check of an IP. Fractal also has quietly added some of the new industry standard formats into Crossfire increasing its versatility for industry wide IP and SoCs. Today, Crossfire is a semiconductor industry standard tool that accepts most of the IC design formats and provides numerous methods and techniques for checking and analyzing the correctness and quality of an IP or SoC design during any stage of its development. It supports all kinds of scripts, and provides interfaces for database query and reporting in several formats as desired.

To know more about Fractal’s secret sauces, new formats and features, and their plans for the upcoming DAC, I talked to Fractal’s co-founder Rene Donkers. Rene provided a great insight into Fractal’s sincerity in accommodating most of the semiconductor IC design industry formats and databases into Crossfire and helping customers accelerate their design turnaround time through correct-by-construction approach and high interoperability provided by Crossfire. Here is the conversation –

Q: Rene, I see Crossfire increasingly being adopted in the industry. It’s natural because a common struggle faced by designers is working through so many formats. Crossfire provides a great relief there by automating things. But no one thought about developing this kind of tool. How did you get this idea?

A: The idea for Crossfire (CF) came into existing from sending AE’s onsite when working at our previous employer for support. The AE’s were just wasting so much time on getting the correct data to start doing what they came for in the first place that I thought there is a QA problem out there and that it is hard to solve.

I realised there is a need for QA tools in the world. We noticed that CAD groups typically had proprietary solutions to solve the consistency problem for their specific design flows. But these scripts were far from comprehensive and always running behind as there was a continuing struggle to keep the scripting up-to-date with new developments.

Q: In last December, you added some of the power formats (UPF and ANSYS APL) support in Crossfire. What’s the motivation behind them? Why they were not supported earlier?

A: The need for new formats is driven by the users. UPF is there because all designs now deal so much with power issues that everyone starts using that. We needed to support it. This is all about priorities. We structure Fractal development around the needs of our current customers, addressing show-stopping issues first. Also when we take on a new format we rather choose to cover it completely rather than create incomplete versions which in the end do not serve our customers and increase our support load.

Q: I see another format, AOCVM (Advanced On Chip Variability Model) supported in Crossfire now. Was there an specific demand for this support? What kind of SoC/IP vendors are using this?

A: AOCVM is needed for nodes like 10nm and beyond because variability becomes a big issue when transistors are being built out of just a few atoms. Our most advanced users need to check this format because they need it more and more.

Q: Why DSPF (Detailed Standard Parasitic Format) was not in the picture yet?

A: DSPF has been there since long. It’s not a new format in the sense that we parse it since long. We just created some new checks on this format, e.g. the sum of the capacitance nodes needs to add up to the number listed for that net.

Q: I see many features added into Crossfire to investigate a design from multiple angles for its correctness and robustness. How are these benefiting customers? Do you have a quantitative figure; say in terms of time saving to tape-out?

A: Users claim that the time they save can go up to a full design cycle since problems are discovered earlier. Using a tool like CF forcing standards makes everybody’s work easier on a day to day basis adding up a lot of minutes day by day… Crossfire allows you to detect issues sooner. It’s well known that sooner you detect an issue, lesser is the time it takes to fix. It’s hard to quantify this benefit, but some of our customers were able to shave weeks off their development cycle.

Q: How is the customer adoption rate for this tool, in US and outside US?

A: We see users going into production within 6 months after introducing the tool. Most of the major IDMs and large fabless design houses are either Fractal customers, evaluating or are considering starting an evaluation.

Q: What are the new things you are planning to showcase in DAC this year?

A: You will see all of the above; new formats, new checks that are implemented in our tools. There are new ways and features added to our IP validation capabilities, which is an area where we see plenty of growth potential in the near future.

This was a very fruitful conversation with Rene. I plan to visit Fractal booth and see these features and formats working in actual demo there. I will write more about the specific feature/format support when I have more information on these. Stay tuned!

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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ASMC 2015 Preview

ASMC 2015 Preview
by Scotten Jones on 05-01-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

From May 3[SUP]rd[/SUP] to May 6[SUP]th[/SUP] the 26[SUP]th[/SUP] annual Advanced Semiconductor Manufacturing Conference (ASMC) will be held in Saratoga Springs, New York.

The ASMC offers a unique view of challenges to the semiconductor industry focusing on things like defect reduction, metrology and fab operations. In my work on modeling of semiconductor costs I find the fab wide operational view of this conference particularly interesting.

I have been going through the advanced program identifying the papers that look to me to be the most interesting:

Monday – May 4[SUP]th[/SUP]
The conference opens with Keynotes on Monday morning. I am particularly interested in seeing Robert Maire present on “The Semiconductor Industry at an Economic Crossroads” There are so many new developments in the industry with Moore’s law slowing and the possible emergence of the Internet of Things that I am interested to hear his perspective.

In session 2 on Factory Optimization I am interested to see the papers on shortening cycle time and simulation use for 300mm fab automation. I have done a lot of work in the area of cycle time and cycle time is an area where I have questions come up a lot about benchmark cycle times and economic impact.

In the afternoon there is a paper in session 3 on Yield Enhancement/Methodology on collapse-free patterning for 20nm NAND flash that looks interesting.

In the evening there is an extensive poster session.

Tuesday May 5[SUP]th[/SUP]
In the morning, session 7 on Factory Optimization features several fab wide optimizations papers that look interesting covering performance indicators, equipment maintenance and green fabrication for energy savings. These type of papers often provide valuable insight into current fab state-of-the-art performance.

In the afternoon session 8 on Advanced Equipment and Materials has an interesting paper on wet etch of TiN and TaN for High-k metal gate fabrication.

Session 10 on Advanced Pattering has a paper on optimizing lithography tools for MEMS manufacturing. MEMS is an area where I do a lot of cost modeling.

Session 11 on Contamination Free Manufacturing has an interesting paper on backside and edge clean of III-V on silicon wafers. III-V on silicon is an area of intense research for sub 10nm logic processes.

Wednesday May 6[SUP]th[/SUP]
In the morning session 12 on Advanced Process Control features a paper on predictive maintenance. Variability is a huge detractor from fab performance and any time you can reduce variability for example by doing preventive maintenance in place of having random breakdowns you gain in efficiency.

Session 14 on 3D/TSV has a paper on enhanced etch process for TSV and deep silicon etch. TSV is an emerging area of great interest and etch is a major gating item in the process.

Session 15 on Advanced Equipment and Materials has a paper on multiple epitaxial films deposition for power semiconductors. Devices such as CoolMOS reduce on-resistance in high voltage power MOSFETs but require multiple Epitaxial layers. This should be an interesting view of how this is done at Infineon, a leader in this technology.

Of course conferences like this are also a great opportunity to network with key customers and partners.

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Can You Really Automate Analog IC Layout?

Can You Really Automate Analog IC Layout?
by Daniel Payne on 04-30-2015 at 7:00 pm
Categories: EDA, Siemens EDA

Digital IC design has been largely automated with high-level languages, RTL coding, logic synthesis, and automated place and route tools. What about analog IC layout automation, is it possible? A few EDA companies think that it is possible and even practical. In recent memory there were two companies really focused on analog layout automation and that I also consulted for:

  • Barcelona Design Automation, out of business in 2005
  • Ciranova, acquired by Synopsys in 2012

Ed Petruswas VP of Engineering at Ciranova, however he moved over to Mentor Graphics in 2011 and his group just presented a paper at the 9th International Design and Test Symposium titled: Multi-Device Layout Templates for Nanometer Analog Design. This paper talks about a proposed EDA tool that automates the very difficult task of analog IC layout.

Related – Advances in Nanometer Analog and Mixed Signal Design!

Proper performance of many analog circuits requires that the transistors be matched in their physical layout. The goals of an automated tool would be:

  • Generate complex analog layouts using Open Access (OA)
  • Support commonly used analog circuits
  • Use placement techniques like common centroid and stress avoidance
  • Produce highly matched layouts
  • Routing driven by user-constraints
  • Free of DRC violations
  • Support guard rings and dummy devices

Here’s the proposed tool flow for automating analog IC layout:

The Layout Templates Tool is where this methodology differs from manual placement and routing. The components of the Layout Templates Tool are shown below:

Using this approach you can generate an optimized layout for analog circuit topologies like: differential pairs, current mirrors and cascode current mirrors. A circuit designer uses schematic capture to select these devices and then defines the needed placement, routing, guard ring and dummy constraints through a GUI. The core engine accepts this info and automates the layout using device generators with technology from a design kit. There’s a layout pattern generator that has a set of pre-defined interdigitated patterns for each analog building block. Three placement methods are supported in the automatic pattern generator:

  • Perfect Common Centroid (PCC)
  • Common Centroid and Shallow Trench Isolation (CC&STI)
  • Separate Placement (SP)

The internal placer engine uses a two-stage approach, device placement for a row followed by placement of rows. Internal routing also uses two stages, routing inside the row then routing between rows. Passive devices like capacitors can also be automated by using array placement.

Related – Full Spectrum Analog FastSPICE Useful for RF Designs on Bulk CMOS

Here’s an example in 28 nm technology of a differential pair as a schematic and automated layout with interdigitation of PCC, without guard ring, and the number of finger/device = 32.

A more complex integrator circuit example has the following components:

  • Differential pair
  • Current mirror
  • Current mirror bank
  • Capacitor array
  • MOS transistor
  • Resistor
  • Capacitor

Summary

Mentor Graphics has developed a capability to automate analog IC layout, so that the team of circuit designer and layout designer are more efficient, and spend less time doing manual chores, less time running DRC checks, and less time iterating to meet specifications. I look forward to a formal product announcement in the future. The complete 6 page conference paper is available here.

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Extending Moore in Silicon

Extending Moore in Silicon
by Daniel Nenni on 04-30-2015 at 7:00 am
Categories: Foundries

A year ago many eulogized the death of Moore’s Law at 28nm due to higher prices per transistor at more advanced nodes, but now that we have celebrated the 50th anniversary let’s look ahead to technology scaling and electronic systems miniaturization for the next decade. Despite our industry’s bipolar tendencies and daunting technical challenges, I remain soberly optimistic about the future of semiconductors. Here is one reason why:

“The technology shift from planar to 3D MOSFETs has created new opportunities for disruptive device and process innovations that can extend Moore’s Law.” –Jeff Wolf, CEO of FinScale Inc.

Has technology scaling brought us into a physical domain where new approaches are needed? Many think so, and it seems counter-intuitive (to me) that we could capture all of the potential gains offered by the shift to 3D MOSFETs using the industry’s now institutionalized tick-tock approach to device and process development. A break from past paradigms should be explored when transitioning from two to three dimensions in any context – as we’ve already experienced in graphics, CAE and video games.

I recently met with founders of FinScale, a device and process innovation start-up, who introduced me to their 3D quantum FinFET. As CTO Victor Koldyaev described how FinScale’s qFinFET harnesses positive quantum effects and mitigates negative QE, I had to stop him and ask, “Do you really talk to customers like this?” It was refreshing to hear scientific support for how we can continue to scale forward with Moore’s Law benefits, and made me realize we haven’t been getting as much technical explanation from manufacturers about their process and yield improvement learning as in the past.

We should expect changes in the way we describe semiconductor technology in the quasi-ballistic regime. I don’t yet hear many talking about the fundamentals of sub-20 nm 3D MOSFET operation, which are increasingly dominated by the atomic properties of materials and quantum effects. Beyond our vital discussions about litho, punch-through and electrostatic control, I’m looking forward to hearing more discussions about quantum inversion layers, ballistic transport, scattering centers and carrier relaxation times.

FinScale touts qFinFET’s many-node Moore’s Law scaling roadmap in silicon down to the 5 nm node, on either bulk or SOI, with dimensions specified for critical device features at each node. The FEOL process sequence is defined, including many FinScale innovations that work together to improve performance, density and power efficiency, and lower the manufacturing cost of fin-based devices. FinScale claims that qFinFET can be readily fabricated using existing advanced node process modules, equipment and materials, and provide fin-based device solutions for logic, embedded and stand-alone memories, analog, RF and image sensors.

While this all sounds good and is well-supported by scientific and advanced manufacturing technology research, FinScale’s inventions need to be validated in practice by a high-volume foundry or IDM early adopter, which is FinScale’s goal.

I think a compelling case can be made for start-ups as enablers of the industry’s path forward – to incubate potential breakthroughs with focused intensity on accelerated timelines. The figure below shows the recent results for the all-in-house approach to R&D. For the past five years the time gaps between node-to-node transitions at leading manufacturers are increasing. It doesn’t appear that business-as-usual is getting the industry to where it needs to be according to Moore. These gaps are opportunities that FinScale aims to fill.

http://www.semi.org/en/node/50391, accessed 13 April 2015

I’m encouraged to see renewed investment interest in semiconductor start-ups after declining deal flow in recent years. Our industry needs to keep seeding and cultivating promising start-ups and disruptive technologies so that they’re ready when needed to solve difficult challenges and capitalize on tomorrow’s world-changing opportunities.

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Single Chip MCU + DSP Architecture for Automotive: SAMV71

Single Chip MCU + DSP Architecture for Automotive: SAMV71
by Eric Esteve on 04-29-2015 at 7:00 pm
Categories: Foundries

It’s all about Cost of Ownership (CoO) and system level integration. If you target automotive related application, like audio or video processing or control of systems (Motor control, Inverter…) you need to integrate strong performance capable MCU with a DSP. In fact if you expect your system to support Audio Video Bridging (AVB) MAC on top of the targeted application and to get the automotive qualification, ARM Cortex-M7 processor based Atmel SAMV70/71 should be your selection: offering the fastest clock speed of his kind (300 MHz), integrating a DSP Floating Point Unit (FPU), supporting AVB and qualified for automotive.

Let’s have a closer look at the SAMV71 internal architecture:

When developing a system around a Micro Controller Unit (MCU) you expect this single chip to support as many peripherals as needed in your application to minimize the global cost of ownership. That’s why you can see the long list of system peripherals (top left of the block diagram).
Atmel SAMV71 is dedicated to support automotive infotainment application, so the Dual CAN and Ethernet MAC support (bottom right). If we dig into these functions, we can list these supported features:

  • 10/100 Mbps, IEEE1588 support
  • MII (144-pin), RMII (64-, 100, 144-pin)
  • 12 KB SRAM plus DMA
  • AVB support with Qav & Qas HW support for Audio traffic support
  • 802.3az Energy efficiency support
  • Dual CAN-FD
  • Up to 64 SRAM-based Mailboxes
  • Wake up from Sleep or Wake up Modes on RX/TX

The automotive-qualified SAM V70 and V71 series also offer high-speed USB with integrated PHY and Media LB, which, when combined with the Cortex-M7 DSP extensions, make the series ideal for infotainment connectivity and audio applications. Let’s take a look at this DSP benchmark:

If you are not limited by budget consideration and can afford integrating one standard DSP along with a MCU, you will probably select the SHARC 21489 DSP (from Analog devices) offering the best-in-class benchmark results for FIR, Biquad and real FFT. But such performance has a cost, not only a $ cost but also in term of power consumption and board footprint, let’s call it “cost of ownership”. Automotive applications are running in production by million units per year, and $ cost is absolutely crucial in this market segment and you will quickly decide to go to an integrated solution.

To support audio or video infotainment application, you expect the DSP integrated in the Cortex M7 to be “good enough” and you can see from this benchmark results that it’s the case for Biquad for example, as ARM CM7 is equal or better than any other DSP (TI C28, Blackfin 50x or 70x) except the SHARC 21489… but much cheaper! Good enough means that the SAMV70 will support automotive audio (Biquad in this case) and keep enough DSP power for Ethernet MAC (10/100 Mbps, IEEE1588) support.

You can see on the above picture the logical SAMV71 architectures for Ethernet AVB support and how using the DSP capabilities for Telematics Control Unit (TCU) or Audio Amplifier.

Integrating a DSP means that you need to develop the related DSP code. Because the DSP is tightly integrated into the ARM CM7 core, you may use the MCU development tools (and not specific DSP tools) for developing your code. Since February the ATSAMV71-XULT (Full featured Xplained board) is available from Atmel. As this board has been built around the features rich SAMV71, you can develop your automotive application on exactly the same MCU architecture than the part going into production:

More information about this evaluation/development board is available on Atmel web here.

From Eric Esteve from IPNEST