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FinFET Design Enablement

FinFET Design Enablement
by Daniel Payne on 03-10-2015 at 1:00 pm
Categories: EDA, FinFET, Synopsys

We read about FinFET technology in the semiconductor press daily now, thanks to Intel introducing their TriGate transistors starting in 2011 and creating a race with foundries and IDMs to switch from planar CMOS nodes. To get some perspective about the progress of FinFET IP and EDA tools I spoke with two experts from Synopsys, Swami Venkat and Saleem Haider. Synopsys is an EDA software company that enables FinFET chips to be designed, verified and implemented. We spoke by phone on Friday, March 6th.For the past three years 2012-2014, the general FinFET progression has been mostly test chips and limited production, outside of Intel. At DAC in June 2014 we saw the first 14 nm FinFET production silicon from Samsung. Intel now has a 2nd generation FinFET technology at 14 nm used in their Core M Processor.All new semiconductor process technologies start out with 3D TCAD tools that predict the physical and electrical properties, start to build up models used by SPICE circuit simulators, and create flows for parasitic extraction. Even IP development can start at this early stage, and for FinFET that process started back in 2005 with SPICE models.From 2012 to 2013 the commercial EDA tools were updated to work with FinFET requirements, and in the past two years the IP companies, foundries and IDMs have been validating their FinFET designs through test chips, correlating silicon to their models and announcing IP libraries. All of this groundwork now makes 2015 the year that FinFET designs are in production ramp up, like the Samsung Galaxy S6 phone announced this week. Early collaboration between foundry, IP and EDA companies was critical to the success of FinFET use.Related – What’s New with Static Timing AnalysisSynopsys EDA tools are FinFET ready and silicon is working:

  • FinFET device modeling and circuit simulation: HSPICE, CustomSim, FineSim
  • FinFET IC layout editing with abutment rule, double patterning, MEOL (Middle End of Line) layers: Laker Layout
  • FinFET parasitic extraction: StarRC
  • FinFET layout rule compliance for DRC (Design Rule Checking) and DPT (Double Patterning Technology): IC Validator
  • Place and route with quantized rules, grid rules, optimizations: IC Compiler I, IC Compiler II
  • Static Timing Analysis with waveform-propagation delay calculation: PrimeTime

Related – How Well is HSPICE Tracking Current Design Trends?Use of the Synopsys EDA tools are so popular that some 90% of volume production FinFET chips use at least one of their tools. These customers include:

  • HiSilicon Technologies (ARM Cortex-A72, Cortex-A57, Cortex-A53 for wireless)
  • Marvell
  • Netronome
  • NVIDIA
  • Foundries

    • Intel Custom Foundry (Achronix)
    • GLOBALFOUNDRIES
    • SAMSUNG
    • TSMC
    • Samsung

One EDA tool for Place & Route optimized for FinFET is IC Compiler II, announced about one year ago. Compared to the first generation IC Compiler tool you can expect a speed-up of 10X, and better QoR (Quality of Results), while using less RAM resources. With that speed improvement engineers can now consider doing more explorations to optimize for for area or frequency, while pulling in the schedule a bit.The IC Compiler II tool is now used at 27 different customers, with 67 engagements and 17 tape-outs so far. Adoption looks brisk for a relatively new tool, so that’s a good sign, plus there are several customers that have testimonials: ARM, Imagination, LSI, MediaTek, Panasonic, Renesas, ST Microelectronics, Samsung and Toshiba.Related – How Imagination tested the PowerVR Series6XTTrendsThe 20 nm planar node required DPT, which was more complex on implementation and the power, performance and area weren’t compelling enough. Many customers opted to skip the 20 nm node, and instead go to 16 nm and 14 nm FinFET instead.Chip speed as measured in GHz is increasing again with FinFET technology. Leakage on planar devices was limiting the GHz race. The pressure is on for dynamic power optimization, pushing P&R tools and improving QoR.FinFET at 16 nm and lower nodes the routing is now limiting the overall density, so having technology like Zroute helps meet routing requirements.The size of physical partitions must increase, so 100 blocks in a chip is happening today. Partitions with up to 5-10 million cells can now be handled.SummaryEDA companies, IP providers and foundries have created virtual teams that have closely collaborated to enable the FinFET revolution that we are now witnessing in production quantities for 2015. These are very exciting times for consumers like me, because I get to enjoy products that were unthinkable only a few years ago.

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2015, the Year of the Sheep…And the 16nm FPGA

2015, the Year of the Sheep…And the 16nm FPGA
by Paul McLellan on 03-10-2015 at 7:00 am
Categories: FinFET, FPGA, Xilinx

If you live in California anyway, with its large Asian population, you can’t have helped noticing that it was the Lunar New Year a couple of weeks ago, the start of the year of the sheep. A couple of days after the New Year, Xilinx announced their new families of what they now call FPGAs, 3D ICs and MPSoCs. But which the rest of us will probably still be calling FPGAs until the year of the sheep comes around again in 12 years. These form the UltraScale+ portfolio.

These new products are (or rather will be) built in TSMC’s 16FF+ process. Just like in the TSMC process names, where 16FF and 16FF+ are not at all the same process, that “+” sign after UltraScale is important. The previous UltraScale family was built in TSMC’s 20nm planar process. The 16FF+ process is FinFET (that is what the “FF” stands for) with all the well known performance and power advantages. Since TSMC’s 16nm processes share the BEOL (metal) with their 20nm process, the area savings from the previous generation are likely to be minimal.

This is really a pre-announcement since parts will not be available until Q4. As was said on the last earnings call, the parts should tapeout in Q2, a quarter later than originally planned. Of course the primary competition is Altera who are famously building their first FinFET arrays on Intel’s foundry process. But in their earnings call they said that they might switch back to TSMC for 10nm, which I can only assume means that things are not going all that well. Anyway, Xilinx is continuing to claim to be a generation ahead. They are not actually the first FinFET FPGAs, I think that Tabula actually had some parts in Intel’s 22nm FinFET process and Achronix does too, but they are not volume suppliers (and in Tabula’s case, not suppliers at all since the company is shutting down).

In addition to moving their portfolio to 16nm, Xilinx also announced two new technologies:

UltraRAM which gives you up to 432Mb of memory. This is designed to be a better solution than either distributed RAM (in the FPGA fabric) or on-die block RAM, and with much better performance and power than you can get with external RAM. Of course if you need gigabits of RAM you will need to pay the cost of going external.
SmartConnect intelligent interconnect optimizes interconnect and matches the interconnect architecture to the performance constraints of your design. It reduces interconnect by about 50% and so leads to an overall reduction of about 20% in power and area for the overall design.

Xilinx announced 3 new families:

At the highest end is Virtex which is their 3rd generation of 3D IC, now with added 3D transistors too. These are the parts that use multiple smaller die on a silicon interposer to build huge arrays that would barely yield at all if manufactured as a single die (assuming they don’t exceed the maximum reticle size).

Next is Zynq, what they call the all-programmable SoC. They have a lot of processors, around 10, on each array: a quad-core ARM Cortex-A53, a Mali GPU, a Cortex-R5 dual-core real-time processor, a power management unit with its own processor, a security processor for key and vault management, hardware H.265 implementation, PCIe, 100G ethernet and more.

Kintex is the low end, smaller arrays intended for mid-range applications. They incorporate the UltraRAM and SmartConnect technologies

The TSMC process delivers a big increase in performance/watt. Xilinx claim 2-5X. Of course you can take that as extra performance for the same power, or lower power for the same performance, or some combination. But note the small print, they compare themselves to their 28nm arrays (since that is what most people are actually using today) and not to the 20nm generation.

Learn more at the Xilinx website here.

Also Read: Altera 14nm and 10nm Update!

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Why did Mentor Acquire Tanner EDA?

Why did Mentor Acquire Tanner EDA?
by Daniel Nenni on 03-09-2015 at 11:30 pm
Categories: EDA, Tanner EDA

You have to love when a professional journalist leaks a story and cites a “source close to the acquisition.” News flash: Anyone “close” to the acquisition is under NDA which is a legally binding agreement, not very professional if you ask me. Bloggers however can write whatever they want but since I was actually “close” to the acquisition I had to wait until it was officially announced.

Like the Mentor acquisition of BDA(I was close to that one too), Tanner provides a critical part of Mentor’s evolving analog and mixed signal (AMS) design strategy. As we know, AMS makes the mobile, automotive, and IoT world go round which is why Mentor is getting aggressive on acquisitions in this space. Also notice that Tanner and BDA tools are already integrated.

Tanner EDA has been with SemiWiki since the beginning and it has been a pleasure to work with them. Take a look at their landing page HERE.There is a nice company history, videos, blogs, and wikis. I also helped Tanner EDA with foundry work and their exit strategy. I can’t mention numbers of course but let me just say that it was indeed a happy ending for John Tanner and a new beginning for Tanner EDA.

“Tanner EDA has built an outstanding reputation as the price performance leader for the design, layout and verification of AMS ICs, MEMS and IoT devices,” said Greg Lebsack, President of Tanner EDA. “We are excited to join Mentor Graphics where we can leverage their extensive technology leadership and global footprint. We view this transaction as very positive for Tanner EDA’s customers, employees and the industry as a whole.”

Over the last 27 years Tanner EDA has shipped close to 35,000 licenses of its software to more than 5,000 customers in 67 countries. The Tanner analog and digital tools are THE most cost effective, have THE shortest learning curve, and THE best customer support. That is the John Tanner recipe for success. The challenge they had however is similar to the one I face as a consultant and with SemiWiki subscribers. Once our customers are successful they get acquired and we are displaced by existing corporate agreements. So it really is a treadmill of finding new customers. Mentor of course already has volume purchase agreements with the top semiconductor companies who are driving the semiconductor industry consolidation so Tanner EDA is an accretive acquisition.

Most importantly, Tanner tools are the key to penetrating the Cadence Virtuoso monopoly. The best way to do that is to work closely with emerging companies, universities, and developing countries with semiconductor design as a national charter. Simply stated, rather than attack a stronghold, build your own fortress from the ground up and innovate your way to increased market share. Yes of course this has been tried many times but that was before IoT. The Tanner tools and support model are the perfect solution for IoT and now Mentor has them. Congratulations to all! This acquisition truly is for the greater good of AMS design, absolutely.

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MIPI Ecosystem talk at Seattle this week

MIPI Ecosystem talk at Seattle this week
by Eric Esteve on 03-09-2015 at 7:02 pm
Categories: IP

Sunday 8, March 2015. D-day minus one before the MIPI Alliance Face to Face meeting, starting in Seattle on Monday 9[SUP]th[/SUP] for five days. MIPI members are joining from all around the world to attend this one week meeting. If you take a look at www.mipi.org you will see the names of the 263 members from MIPI. A strong ecosystem has grown around MIPI technology since the Alliance creation in 2003. If you rank these 263 members by categories, you find SoC and Peripheral chip makers, OEM-ODM, IP and VIP vendors or Test equipment suppliers. That’s already a vibrant ecosystem! Add Test Services, Design Services, Education and “Others” and you have the complete MIPI Ecosystem.

And I will present during the opening plenary session in Seattle the results obtained after six weeks fascinating work. Doing such research is all about methodology; in this case it was two phases work. During the first phase I had to compile about 30 criterions by company to build a complete data base. The second phase was honestly much more fascinating than the first one. I have processed this large amount of information to find the characteristics specific of this MIPI ecosystem. As soon as the data base is available, just running Excel can answer many questions and this aspect of the research is fascinating! I can tell you that I run Excel in many ways, crossing the criterions and even doing some differential analysis, extracting the real trends from the ambient noise (like in analog electronic).

New MIPI Members by Year of Membership
To reserve the fresh information to the MIPI members who have travelled to Seattle like I did yesterday, I can’t show more than these two pictures. Just for your information, this “MIPI Ecosystem 2015 Survey” includes 35 pictures and most of these are more complex than the above one, going deeper into the ecosystem (trying) answering many relevant questions like:

  • Who are the newcomers, what market segment do they target: mobile, PC, IoT, wearable or/and Automotive?
  • Which MIPI specification (s) tends to be used in IoT and wearables ?

And many more questions about IP vendors, OEM, VIP vendors, SoC chip makers… and so on. Moreover IPnest did the same research in 2012, so I could measure the parameters defining the ecosystem evolution. Exploring the time dimension allows bringing a new bunch of answers, certainly useful for the marketing people working at these 263 companies, the MIPI members. If you are working for one of these, you should be able to read this survey (for free) as it should be distributed to every member… just wait for a couple of weeks!

Sorry, I just have to leave my hotel room to find the right conference room, to fine tune the two presentations I will make on Monday and Tuesday. Once again, this research was fascinating, and I have no doubt: MIPI technology penetration has been strong (in mobile first) and the pervasion in other market segments has started in some of these or is just a question of time for the others…

MIPI Alliance has organized an Open and Demo Day (non-MIPI members are welcomed) this Thursday 12, March in Seattle, at Renaissance Hotel… see you there!

From Eric Esteve from IPNEST

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Apple Watch Announcement

Apple Watch Announcement
by Daniel Payne on 03-09-2015 at 1:00 pm
Categories: General, Mobile

Rock music, invitation only tickets, hollywood lighting, journalists from around the world, live streaming on the web, yes, another typical Apple-orchestrated product launch on Monday, March 9th at the Yerba Buena Center in California.

Up first was a video about Apple’s store opening in West Lake China with superb cinematography. Tim Cook strolled on stage to thunderous applause and talked about opening more stores in China and around the world, with some 120 million customer visits last quarter.

Apple TV
Apple TV has lots of streaming content choices, and now you can get HBO too. Richard Plepler, CEO of HBO read from a prompter instead of addressing the audience. Special one day pricing of $69.00 for AppleTV, instead of $99.00.

iPhone
iPhone sales have now reached 700 million units since inception. Apple Pay has now up to 2,500 banks supporting it, with some 700,000 locations to use it.

CarPlay
CarPlay will soon be working in all major brands of cars, with some 40 car models shipping in 2015 with support.

HomeKit
HomeKit developers have produced 90 apps so far, making the home a bit smarter place.

HealthKit
HealthKit has piqued the interest of medical researchers, especially for getting volunteers into medical testing studies. ResearchKit is a way for medical researchers to continuously gather medical information using iPhone and HealthKit, thanks to a dozen major medical institutions. You sign up for these research studies using your iPhone and special apps. Initial uses for ResearchKit are: Parkinson’s, cardiovascular, asthma, breast cancer. Privacy is central to the adoption of such apps, and Apple never sees your medical data. ResearchKit will be Open Source, so there’s hope potentially Android users as well.

Mac
This product line has outgrown the industry for the past 10 years, with MacBook growing at 21% last year while the laptop segment declined. Phil Schiller introduced the new MacBook with a 12″ display, weighing just 2 pounds and 13.1 mm thin, even thinner than the MacBook Air, and with no fans, starting at $1,299.00. SoC use enabled a 67% smaller circuit board, using the Intel Core M CPU, sorry no break from Intel quite yet. The display is glossy like a mirror, so there’s room for improvement with a matte display in a future release.

The trackpad is more pressure sensitive, and there are multiple batteries with contoured cells providing all-day use. A single connector is the USB-C.

MacBook Air
This gets faster processors, and 2X faster Flash.

MacBook Pro
The tiny 13″ laptop gets newer processors, and longer battery life. I was personally disappointed because I wanted a 17″ MacBook Pro to be brought back after being orphaned in 2011, however it appears that Apple is not interested in providing larger, more powerful laptops.

Apple Watch
Crammed with features, like: Luxury, accurate time piece, variety of faces, customizable, controlled by swiping, traditional crown, single button operation, receive messages, make phone calls, read emails, watch-to-watch doodling, purchase with Apple Pay, view photos, ask Siri, receive notifications and do fitness tracking with motivation.

There’s a WatchKit SDK and developers have been coding new apps, like: Facebook, Twitter, sports, trips, calendar, WeChat, Apple Pay for retail purchases, Instagram, Uber, boarding pass, hotel reservations, unlock hotel room door, Shazam, text messaging, garage door remote.

The Apple Watch really only works with an iPhone, so don’t expect to plug and play with Android any time soon. Battery life is designed to be 18 hours. Three price points are:

  • Apple Watch Sport in silver or space grey with Aluminum alloy, $349 to $399 (two sizes)
  • Apple Watch in stainless steel, $549 to $1,099 (two sizes)
  • Apple Watch Edition in 18kt Gold, $10,000 (two colors)

Bands for the Apple Watch come in a huge variety, and you can pre-order watches on April 10th, shipping on April 24th.

Summary
Apple has the best consumer marketing in the world and with the new Apple Watch they have added yet another new product line that will tantalize the Apple faithful and make competitors green with envy. Full disclosure, I do own AAPL stock, but use an Android phone and will not be buying the Apple Watch.

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Voltage Limbo Dancing: How Low Can You Go?

Voltage Limbo Dancing: How Low Can You Go?
by Paul McLellan on 03-09-2015 at 7:00 am
Categories: CLK Design Automation, EDA

All chips these days have to worry about power. Indeed it is typically the top of the priority list of concerns, above performance and even area. Transistors are effectively fast and free, but you can’t have too many of them (at least turned on at once). The most obvious way to reduce power is to lower the supply voltage. This occurs squared in the dynamic power equation and is non-linear in static (leakage) power. This is not just a problem for the most leading edge processes, 14/16/10nm. A lot of designs, especially for IoT, are done in non-leading-edge processes. Indeed, TSMC has recently gone back and produced even lower power versions (ULP) of several of their mature processes that can run at lower voltages than the original processes when they were introduced. The way to get the power to an absolute minimum is to run with the supply voltage as low as possible, but this means that the margins for timing are critical. Being optimistic will lead to outright failure or low yield; being pessimistic leaves a lot of performance and power-reduction on the table.

As is usually the case in EDA, the substitute for pessimism is accuracy. But even using lots of process corners isn’t enough since there is too much variation and it is often impossible to close timing with this approach: fixing the FF corner causes violations at the SS corner and vice versa. Systematic margining will not get you there. It is necessary to explicitly analyze variance since putting the voltage up is not a viable option.

So here are four pictures to scare you!

At very low voltage, process variance can be as much as half the delay, much more than at higher voltages. Inaccuracy in calculating variance is not a second-order effect that can be ignored:

At low voltage, the variation is non-Gaussian (not a normal distribution) and in particular the tails are longer and just guard-banding with a certain number of standard deviations will miss those tails:

Constraints are also affected by process variance and voltage too, and can also be non-Gaussian at very low voltages:

Static timing analysis misses some effects, in particular Miller capacitance, which is a dominant effect below 20nm and especially at low voltage. On high fanout nets such as clocks, STA will miss Miller Capacitance and so miss violations:
So that is scary. What can you do about it?

CLKDA’s portfolio of FX tools is designed to address these issues and let you get the voltage as low as possible by giving you the accuracy you need to be confident of working/yielding silicon.

FX is within 2% of MC SPICE for delay but is 400,000X faster, so can analyze thousands of paths in minutes and full clock-trees in hours. It supports all major foundries and libraries. It is in production down to 14/16nm and is being used in leading SoC designs today.

There are multiple components:

  • Variance FX: the industry standard for timing derates (supports AOCV, POCV and LVF)

    • derates drive process yield into physical flow (STA, P&R, optimization)
    • all cells, arcs, loads and skews
    • 1000 cells per hour using 100 cores
  • Macro FX: extends variance FX to complex logic cells

    • big delay buffers, retention flops, very large flop trays, memories
  • Voltage FX: voltage and variance sensitivity for delay and constraints for cell libraries

    • analyze library across voltage operating points
    • identify at-risk cells in library
    • extend to process and temperature
  • Clock FX: full-chip clock tree analysis, SPICE accurate insertion delay and skew

    • automatically finds clock trees
    • corner, global corner/statistical or full statistical
    • measure delay, crosstalk, voltage effects
    • fast: 100M instance 20nm design in under 2 hours
  • Path FX: run tens of thousands of paths in just minutes, identifies timing surprises no other STA tool can find

    • SPICE-accurate path analysis
    • timing waivers, multi-voltage paths, PVT path sweeps, black box timing models,

The FX platform can be used across the entire design process from library design, through floorplanning, physical design, clock tree generation, optimization and signoff.

There are lots more details about the FX platform on the CLKDA website here.

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Is Cadence the Best EDA Company to Work for?

Is Cadence the Best EDA Company to Work for?
by Daniel Nenni on 03-08-2015 at 7:00 am
Categories: Cadence, EDA

Apparently that is the case. Honestly my choice would have been Mentor but I can easily make an argument for Cadence based on my discussions with the foundries and their top customers but more on that later.

Fortune Magazine last week added Cadence to the 2015 list of “100 Best Companies to Work For” citing a cultural transformation driving the company’s recent success. They are referring to the hiring of Lip-Bu Tan as CEO of course. At first some said he wouldn’t stay as CEO but that was more than six years ago, right?

“Being named to FORTUNE’S list of 100 Best Companies to Work For is a tremendous honor,” said Tan. “It speaks to the achievements of our employees, and to the strength of our culture. The enthusiasm of employees for innovation and solving customer problems is central to who we are and has been a critical component in our success.”

I started my semiconductor career right out of college moving to Silicon Valley in the early 1980s when EDA was just getting started. It was dominated by DMV (Daisy, Mentor, Valid) when two smaller start-ups merged (ECAD and SDA) in 1988 to create Cadence with Joe Costello as CEO. Joe was quite a character and I credit him with making EDA an exciting place to work. Unfortunately after Joe left in 1997 Cadence seemed to lose its way. In January 2009 Lip-Bu Tan joined Cadence as President and CEO after serving on the Cadence Board of Directors for five years. To me that was a turning point which brought Cadence back to what they are today, an industry leader. Cadence stock agrees as it has quintupled since Lip-Bu took over as President and CEO.

In regards to the fabless semiconductor ecosystem, I would say I have my finger on the pulse as much or more than most. I routinely meet with the foundries and their top customers and listen to the latest EDA tales of woe. Over the last three years however I have noticed a positive turn to the Cadence stories. One large fabless customer who is a notorious complainer told me recently that they have the best relationship with Cadence today than they have ever had which is going on 20+ years now. Same with the foundries, you can clearly see this through the level of engagement via Hsinchu visits, PDKs, conferences, webinars, and other collaborative activities.

Speaking of that, Wednesday seems to be foundry day at CDN Live this week. Unfortunately I will not be able to attend as I’m in Hsinchu but SemiWiki bloggers Paul McLellan and Tom Simon will be there for some live coverage. If I was able to attend however this would be my must see list:

  • Cadence In-Design and Signoff Tools Certified for ST’s 28nm and 14nm FD-SOI Technologies
  • Tempus (TM) Timing Signoff Solution for Certification in 16FF/10FF TSMC
  • Flows Tackling Coloring, Cell Pin Access, Variability for 2nd Gen Patterning and 2nd Gen FinFET at TSMC 10nm Using Cadence EDI System
  • 10nm Parasitic Challenges and How It Is Addressed by Industry’s Most Accurate FinFET Extraction Tool; Quantus Extraction

Anything FD-SOI and 10nm of course because those are the trending keywords on SemiWiki…

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Semiconductor in China: Is 3rd Time a Charm?

Semiconductor in China: Is 3rd Time a Charm?
by Paul McLellan on 03-07-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

China has recently announced extremely ambitious plans for becoming more self-sufficient in semiconductors. Today China is about 1/3 of the worldwide IC market but about 90% of that is imported. Think of something like the iPhone assembled in Shenzen with chips from TSMC, Samsung, Hynix, Toshiba/Sandisk , Micron and more (Taiwan, Korea, Japan and US).

China is already a growing market for IC equipment. This year it will be $5B, 12% of the world market with another $6B for materials, 13% of the world market.

China has actually been involved with semiconductor for a long time, staring with work done in 1964 not long after the original invention of the IC. They have had several attempts to build domestic manufacturing starting in the 1970s importing production lines from Japan. In that era, when a fab was cheap, there were actually many lines established in China, but mostly for R&D and not commercial. In the late 1980s they created the China Electronics Corporation by the then Ministry of Electronics Industry. They had a joint project with Lucent based on a Lucent process, training and design, although it was not truly successful. Then a joint-venture with NEC in 1997 with a 200mm fab. In that era, SEMI predicted 20 fabs in China but that never materialized. In 2000 SMIC was created and was more successful. There is more capacity in China now, 8% of the world total, but about 2/3 of it is overseas companies operating fabs there (Intel, Samsung, Hynix).

In June 2014 China announced a national project to develop a truly domestic IC industry covering IC design, IC manufacturing, advanced packaging and even semiconductor equipment and materials. There are plans to invest $21B with a more market-based structure, and as much as $100B including local funds from Beijing, Shanghai, Wuhan and Hefei.

To start with now the focus is on 32/28nm and medium to high-end assembly and test. They also plan to develop 200mm 45nm and 65nm equipment. From now through 2020 they plan 20% annual growth which, if achieved, will grow the market to $143B which is 3.5X 2013 levels. The roadmap for 14/16nm is in that timeframe.

They have some very specific goals:

  • IC manufacturing: mass production for 32/38 nm process shall be realized by 2015 and 16/14 nm process shall be realized by 2020.
  • IC design: certain key technologies (e.g. mobile smart terminal, network communication) shall approach international first-tier level by 2015, and other strategic technologies shall achieve international leading edge by 2020.
  • IC packaging and test: revenue from mid-end to high-end technologies shall be more than 30% of total revenue by 2015, and key technologies shall achieve international leading edge by 2020.
  • Material: 12-inch silicon wafers produced in China shall be ready for use in device production by 2015, and enter global supply chain by 2020.
  • Equipment: 65-45nm key equipment manufactured in China shall be used into production line by 2015, and enter global supply chain by 2020.

During SEMICON China, SEMI China will host the Tech Investment Forum-China 2015 on March 18th. The Tech Investment Forum has already become an important platform between investment and pan-semiconductor industry in China. This year, Mr. Wenwu Ding, the CEO of China National IC Investment Fund will give a keynote speech.

SEMICON China is March 17-19th at the SNIEC in Shanghai. Kenotes on March 17th in the Kerry Hotel Pudong are by Lisa Su, President and CEO of AMD; Tzu-Yin Chiu, CEO of SMIC; Xinchao Wang, CEO of JCET; Simon Yang, CEO of XMC; Michael Hurlston, EVP worldwide sales for Broadcom; and Lei Shi, President National Fujitsu Microelectronics. Full details are here.

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Is Semiconductor Technology a Strategic Industry?

Is Semiconductor Technology a Strategic Industry?
by admin on 03-06-2015 at 7:00 pm
Categories: Foundries

Dependence on electronics is acute in all fields today. This includes both civilian and military use. Whether the technology used is state of the art or classic in nature, importance is pointed to the necessity of solid state electronic hardware in everyday life. In such an environment the need to ensure the availability of semiconductors is critical for any user, be it commercial or defense sectors or the government. Thus system producers need to ensure a robust supply source for all their needs that is dependable under all circumstances. Therefore, governments get involved in this activity as part of governance responsibilities.

A compounding factor is the various forms of technology control. Export regulations by government on certain sensitive and/or dual use technologies puts a question mark on the availability of certain kinds of materials/products for dependent markets and economies. This leads to a growing cry for development of indigenous or local supply sources.

Although the semiconductor industry is spread across the world over, the technology to manufacture it in commercially significant levels is limited to very few countries (USA, Korea, Japan, etc.). The underlying need for dependable infrastructure – both in cost and availability – has forced most aspirants to look the other way when it comes to thinking of implementation of this demand, in certain geographies. China invested heavily in the semiconductor manufacturing sector during 1990s and early 2000s. Thus it has been able to establish itself as a formidable force that other countries take note of. The extent of government support that enabled this transformation is significant. Even the USA is known to give considerable monetary support to the semiconductor industry – openly and in concealed forms – towards developing and maintaining this technology leadership.

Also Read:CDN is Live in Silicon Valley!

An additional factor is the sheer monetary cost to the exchequer. The world semiconductor trade is about 300 billion dollars. India is a significant consumer with its growing market for mobile communication and other electronics consumables. India imported over $25B of electronics during 2010-11; this included over $6.5B for semiconductors. Significantly, this import accounts for almost 100% of the semiconductors consumed by Indians; which means, the local production of semiconductor hardware is almost zero. The significant investment and activity seen in the electronics/IT world in India – by leading and startup companies alike – are primarily in design, software and services sectors.

India’s own annual electronics import bill is expected to cross its humongous oil import bill (over 100 billion dollars annually) in the next few years. Given all these factors there is indeed a dire need to ensure local manufacture. The Indian Government has given an in-principle approval for 2 fabs to be set up with technical know-how sourced from global majors. It is here that the “Make in India” campaign by the (now, not so) new Indian Government is pushing for the manufacture of semiconductor chips in India. Given the flux and the large number of coordinating activities that abound in these kinds of endeavors, it is but natural for things to take time, especially in a country like India.

Indeed, the semiconductor industry has turned out to be one that can be called strategic in nature!

Dr. PRADEEP JANA, Ph.D.

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Intel and Samsung in Barcelona

Intel and Samsung in Barcelona
by Paul McLellan on 03-06-2015 at 7:00 am
Categories: Foundries, Intel Foundry, Mobile, Samsung Foundry

This week it was Mobile World Congress in Barcelona. Everyone who is anyone in mobile is there. Unfortunately I’m not since Barcelona is one of my favorite cities to visit. Two companies that set high expectations before the show were Samsung and Intel.

Samsung announced the new Galaxy S6 and S6 Edge smartphones on Sunday. Since there had already been so many leaks there were not a lot of surprises. Yes, it has a metal back, a (very) high resolution screen, fingerprint sensor, 32/64/128GB internal storage, 16Mpx camera, support for Samsung Pay using NFC or MFT, wireless charging. And like the iPhone, no expansion microSD slot, no removable battery, not waterproof. In fact, it is like the iPhone in so many ways, clearly designed to compete with it head-on at the high-end and also outspec Xiomi’s phones who are the big competition in China. It will be available April 10th.

From a chip point of view, the application processor is the Octacore Exynos. That is a big.LITTLE ARM processor with 4 Cortex-A57 and 4 Cortex-A53 cores, running at 2.1GHz and 1.5GHz respectively. Previous high end Galaxy phones, at least in most markets, used Qualcomm Snapdragon processors. It presumably also has the Exynos LTE modem although I’m not sure whether it is all integrated on one chip with the AP or not.

Anyway, the phone has been getting great reviews, although some people are complaining about some of the steps they consider backward (no removable battery for example). It is microscopically thinner than the iPhone 6 and has higher resolution display, giving them some bragging rights at least.

The other widely anticipated announcement was Intel. Brian Krzanich gave one of the keynotes and also Intel had a press conference on Monday. Before the show something big was anticipated since, well, Brian is Intel’s CEO and so just by being there is indicating something about Intel’s commitment to mobile. With the PC market growing at best slowly, and mobile continuing to be the way of the future, Intel needs to be in this market.

Apple, as I’m sure you know, builds its own application processors (currently A8 with A9 expected soon). As mentioned above, Samsung builds their own application processors (Exynos). Qualcomm and Mediatek have almost all of the market for merchant application processors for other mobile handset manufacturers. The high end, where you would expect Intel to be competing based on its history and its historic high silicon margins, is thus proprietary leaving Intel to fight it out on the very competitive lower end.

So what did Intel announce? They renamed SoFIA to x3 for low cost smartphones and tablets. They say they have 20 customers committed to deliver designs. Remember, this is the follow-on design from the one that they have been shipping negative revenue with, basically paying customers as much as $40 to use the part. For higher-end tablets they renamed Cherry Trail to x5 and x7. They introduced a new LTE modem, the XMM 7360 with download speeds up to 450Mbps. The timetables of some of these chips seem to be a little accelerated from previous announcements, but the details remain a bit sketchy. They announced that customers include Acer, ASUS, Dell, HP, Lenovo and Toshiba, who have already committed to deliver devices on this platform.

The Intel press release is cleverly worded so if you don’t look closely it seems the level of integration is greater than it is:Combining 64-bit multi-core Intel Atom processors together with 3G or 4G LTE connectivity, the integrated communications SoC combines the applications processor, image sensor processor, graphics, audio, connectivity and power management components in a single system chipset.

This is what they said during their investor meeting back in November:

They seemed to have pulled the schedules in somewhat. I am no longer sure which of these chips are built by TSMC and which in Intel’s own fabs. The SoFIA MID on the above table is explicitly “Intel fab” so I think the rest are probably chipsets combining an 64-bit Atom-based processor built in Intel fabs with an LTE modem built in TSMC 28nm until late next year when they will finally have a combined AP+modem on an Intel process (the SoFIA MID was explicitly called out as Intel Manufacturing in the November table). Anyway, at MWC Intel now say that Cherry Trail aka x3/x5 will be out in 1H (presumably something like June) whereas it was second half before.

But it all comes over as too little too late. If Intel doesn’t have any flagship design wins I don’t see how they can compete against Qualcomm and Mediatek. Intel is a “manufacturing powerhouse” but that usually means they have great technology for the high-end microprocessor business. Whether that is the technology of choice for the low-end mobile business I’m dubious about.

You can see a video of Intel’s press conference at MWC 2015 (about 30 minutes) here.

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