webinar IPXACT banner
Semiconductor Expert Forum

Posted on

When Talking About IoT, Don’t Forget Memory

When Talking About IoT, Don’t Forget Memory
by Tom Simon on 11-13-2015 at 7:00 am
Categories: Foundries, IP, TSMC

Memory is a big enough topic that it has its own conference, Memcon, which recently took place in October. While I was there covering the event for SemiWiki.com I went to the TSMC talk on memory technologies for the IoT market. Tom Quan, Director of the Open Innovation Platform (OIP) at TSMC was giving the talk. IoT definitely has special needs for memory because of the need for low power, data persistence and security.

Tom Quan started the talk with an informative view of the IoT market. I have heard a lot of IoT overviews, but I listed with a keen ear to learn how TSMC views this market. Since 1991 there have been three big growth drivers for the semiconductor industry. IoT promises to be the fourth.

The first was personal computing which saw 7X growth from 1991 to 2000. Next came mobile handsets demonstrating 9X growth from 1997 to 2007. Last we have smart mobile computing, which lumps together mobile computing, internet, mobile communications, and sensing. This segment grew by 12X from 2007 to 2014. Clearly the IoT is the next big thing and will likely continue this accelerating this trend. The conclusion is that IoT will be the next big growth driver for the semiconductor industry. The sum of PC’s smartphones, tablets and IoT is expected to approach 20 billion units by 2018, compared to roughly 8 billion total today. The last year there is hard data was 2013 with ~5 billion units.


IoT is really an extension of mobile computing. Tom’s talk broke it down into the four umbrella categories of smart wearables, smart cars, smart home and smart city. It will consist of smart devices on smart things. Think of health sensors, gesture and proximity, chemical sensors, positional sensors and more. So where do today’s technologies stand as far as meeting the requirements of the IoT?

Probably every metric for design will be stressed by IoT. Unit volumes will go from the single-digit billions of the PC era to hundreds of billions in the IoT era ahead. Operating times for devices will need to go from hours to years. This in turn demands that the hundreds of watts that PC’s used transform into nano watts for edge sensors and the like. Additionally, new technologies, materials and architectures will need to be developed.

To make these transitions everything will need to be moved forward technologically. The slide below shows how this might work for the wearables segment


A huge part of this will involve embedded memory. Right now SRAM is used primarily for volatile memory. There are a number of solutions for non-volatile memory (NVM), including several future technologies that are very promising. The two major axes for NVM are density (size) and endurance (re-writability). Small sizes that do not need high endurance are things like configuration bits, analog trim info, and calibration data. The work well with one time programmable (OTP) approaches.

Even some boot code can be stored in OTP when it is configured to simulate re-writable memory. However, the number of re-writes will be limited as the non-reusable bit cells are utilized.

Flash and eeprom are good for applications that require larger sizes and more re-write endurance. But they come with the penalty of requiring additional layers or special processes.

Tom suggested that magneto-resistive RAM (MRAM) is one technology that shows some promise. It harkens back to the old core memories, but is scaled to nanometer size. Of the two original approaches for MRAM only the spin-transfer torque (STT) technology has been proven to scale well. There are two competing approaches for this: In-Plane and Perpendicular. MRAM using STT is very fast and uses low power. So it looks very promising as a NVM replacement that can also be used for SRAM replacement.

Another area of promise for future NVM solutions is resistive RAM or RRAM which uses the memristor effect in solid state dielectrics. There are several flavors of this technology being researched. But RRAM is not as far along commercially as MRAM is. However, this is an active area of research and the frequently use high-k dielectric HfO2 material has been discovered to work as RRAM.

Advances in NVM will have a huge impact on IoT. Power savings from having readily available persistent storage will open up new application areas. Think of not having to save system RAM when entering sleep. To further save power TSMC continues to add ultra low power processes to its existing process nodes. IoT will be driven in large part by technologies that allow edge node devices to be power sipping.

For more info on TSMC’s Open Innovation Platform look here.

Posted on

A Novel Microprocessor Fighting Dark Silicon, Energy Efficiency, Code density and Silicon area

A Novel Microprocessor Fighting Dark Silicon, Energy Efficiency, Code density and Silicon area
by Roger Sundman on 11-12-2015 at 4:00 pm
Categories: EDA

Processor cores used in computers and smartphones have become impaired by their own complexity and can’t fully utilize future CMOS generations for increasing their efficiency. Due to the continued increase of density and speed of transistors, these big cores produce too much heat per mm[SUP]2[/SUP] if trying to follow Moore’s law for both transistor count and frequency.

Every transistor switch event produces energy, i.e. heat. Both size and delay time for transistors are reduced for every generation, and if these are utilized, i.e. density or clock frequency is increased, then the heat density increases. This has become a problem with the latest generations. If both maximum density and maximum frequency would be utilized over the entire chip, then the heat would destroy the chip. For a processor core is of course desirable to be able to utilize the maximum performance the technology allows, but this can be done only on a few percent of the chip area, and the percentage is reduced for every generation. The remainder has to be “dark silicon”, meaning that is has to have much lower activity.

A radically new processor architecture, reducing overhead high frequency switching, is needed in order to fully utilize the potential of future CMOS technology. Optimizing for energy efficiency, throughput, cost, code density, adaptability and scalability is a big challenge for the computer architect.

Imsys’ processor has a different, yet well proven, fundamental design that doesn’t have the above mentioned limitation and is therefore suitable for the new situation in semiconductor technology. The core itself consists mainly of memory and it has rich functionality, which enables it to save energy by efficient use of its small flexible arithmetic logic.

Almost the entire chip area, 97%, is memory. Energy efficiency has, for the first time and for the foreseeable future, become the most important characteristic of processors, big and small, also for other reasons than the problem described above.

A proof-of-concept chip, prototyping a tile of a many-core system, has been produced and verified. 97% of its transistors are used in memory blocks. It includes Imsys’ patented dual core solution, where the pair of cores occupies 40% less space and consumes 25% less power than two single cores while doubling performance. The chip is manufactured by UMC using the 65 nm LL process and draws 18 mA at 1.2V and 350 MHz with both cores active. The cores share memories and a 5-port grid network router, NoC. Each core has local memory capacity sufficient for its immediate need, bringing down the load on the grid network on the chip. Memory management is handled by microcode and memory is interwoven with the processor and there is no cache or memory controller needed.

Simply placing 128 copies of this verified tile next to each other results in 256 cores, 42 MByte ROM and 25 MByte RAM on 320 mm[SUP]2[/SUP] silicon, consuming 2.8 W with all cores running at 350 MHz. This can simply be scaled down – with 14 nm technology, an area of 238 mm[SUP]2[/SUP] could have 4096 cores, 672 MByte ROM and 400 MByte RAM and consume 31 W at 1.6 GHz.

The second core only need half the power used by the first core. Each core has almost constant power consumption when active, and the heat it generates spreads across the adjacent memory areas. This allows a higher total power dissipation and simplifies cooling system and power budgeting.

Microcode, as opposed to logic gates, is compact and energy efficient. Imsys uses extensive microprogramming to accomplish a rich set of instructions, thereby reducing the number of cycles needed without energy inefficient speculative activity and duplicated hardware logic. Each core has two instruction sets, including native Java bytecode execution.

Microcode is also used for computationally intensive standard routines, such as crypto algorithms, which would otherwise be assembly coded library routines or even special hardware blocks. Optimizing CPU intensive tasks by microcode can reduce execution time and energy consumption of hot spots by more than an order of magnitude compared to C code.

The rich instruction set optimized for the compiler reduces the memory needed for software and, just like the microcoded special algorithms, it reduces the number of clock cycles needed for execution. The reduced requirements for memory bandwidth and the flexible microprogram control allow the compact arithmetic unit to do useful work all the time.

This platform has a certified JVM and uses an RTOS kernel certified to ISO 26262 safety standard for automotive applications. The development tools will be enhanced with the support enabled by the LLVM infrastructure. A new instruction set optimized for an LLVM backend has been developed and is being implemented in the coming hardware generation.

More information HERE.

Don’t forget to follow SemiWiki on LinkedIn HERE…Thank you for your support!

Posted on

Merger Mania: The Future of the Semiconductor Industry

Merger Mania: The Future of the Semiconductor Industry
by Pawan Fangaria on 11-12-2015 at 12:00 pm
Categories: EDA, Events, Siemens EDA

In a semiconductor industry which appears maturing, we are also seeing the technologies unravelling newer transistor structures, memories, processors, and newer ways of designing ICs and electronic systems. The present decade appears to be at the cusp of a new transformation in the semiconductor industry. Amid a slew of mergers and acquisitions this year, multiple questions arise on how these will affect or shape the future of semiconductor industry.

Dr. Walden C. Rhines, Chairman and CEO of Mentor Graphics Corporationpresented a keynote in their 11[SUP]th[/SUP] User2User India Conference. In his keynote titled “Merger Mania” Dr. Rhines emphasized about the major change in the structure of the semiconductor industry that will affect everything from the product definition to its design and manufacturing. I found a great opportunity talking with Dr. Rhines and getting his perspective on some of the key issues I thought will be coming in the way as we transition into the new phase of the semiconductor industry along with these mergers. Here is the conversation –

Q: Dr. Rhines, a large number of mergers this year reminds me about 2008 when the global financial crisis took place. Although the main cause of that crisis was housing subprime mortgages, there was also a significant consolidation in the semiconductor and other arena just before 2008. How do you interpret the current consolidation? Are we expected to see some sort of financial crisis again in coming years?

A: I hope there will not be a crisis like 2008; at that time housing loans by a large number of people could not be paid back. Today, the situation is not like that. There is liquidity in the market, credit is available at cheap interest rates, and there is free market economy. This is favouring debt and hence acquisitions and mergers are practical because they provide better economy of scale. At the same time the government tries to bring equilibrium in the economy whenever there is distortion in the market. So when interest rates start increasing the merger activities will slow down.

Q: In the current consolidation we are seeing multiple elements. The cost and capital conservation are anyway there to an extent, but there is innovation and expansion as well in particular areas such as IoT and its related segments. Do you see this consolidation bringing a bigger business opportunity rather than just contraction in the number of companies?

A: I see the opportunities in several ways. The corporate overhead will reduce and more money will be available for R&D and innovation. This is a periodic cycle; when acquisition happens, there is reduction in spending, but new businesses expand in due course of time. On the average 14% of the semiconductor revenue goes into R&D. So there may be more expansion in coming years, of course the law of economics cannot be violated.

Q: How do you see the fabless and IP model of business being impacted amid this consolidation?

A: The percentage of IC revenue from foundry wafers continues to increase; it’s touching to about 40%. The silicon foundries have enabled competitive costs for fabless companies, thus enabling economy of scale for IC production. So there may be a few IDMs acquiring fabless companies, but overall the fabless business will continue to grow. Among IP, the standard IP like USB or PCIe are commoditized. However the other value-added IP business will continue to grow.

Q: In near future we can foresee major changes coming in terms of transistor technologies, memories, processing power, IC manufacturing etc. and all of that at nominal cost to end-user. How is the semiconductor industry preparing to cope with providing high-value at lower cost?

A: The cost of transistor has decreased since last 50 years through reduction in feature size. Now wafer cost reduction is reaching its limits, but the transistor cost can still go down by increasing volume and other new technologies to reduce cost. There can be multiple dies in the same package. There is a learning curve associated with every new technology, so in due course we will see new technologies evolving and there will be further growth in the semiconductor industry.

Q: The technology is the driver for EDA tools and EDA tools are enablers for designs. The technology also brings new paradigms in designs. How do you see the EDA tools evolving amid new demands from the technology and design arena?

A: The EDA is an exciting field. Today it caters to multiple prominent process nodes – 28nm, 20nm, 14nm, 10nm, and now 7nm is close to stabilizing. The modern EDA tools are factoring multiple aspects in the design phase of ICs, e.g. manufacturing, cost, yield, and so on. The correlation of test failure with layout is evolving as a significant business. The cost reduction has to be achieved through multiple means. The systematic defects have to be automatically identified through the use of data mining and analysis.

About 5 years ago, Emulation was applied to only graphics chips, but today it’s used to verify any big digital chip. The Emulation driven verification business has doubled in last 3 years. The verification incurs largest expense in a design. The verification cost has to be reduced by multiple means. In the coming future, there will be many changes in EDA tools to enable more efficient design and verification in multiple ways.

Q: China is investing huge money to develop semiconductor industry in that region; M&A is also a part of that initiated by Chinese institutions. How do you see the worldwide semiconductor industry from regional perspective?

A: Yes, in China, the government along with private equity (PE) corporations have announced a five year plan to invest in big way in semiconductors (foundry as well as fabless) which will involve development in China as well as acquisitions in foreign countries. The government will invest ~$20 billion and PEs will invest ~$100 billion. We have already seen the acquisitions of Spreadtrum, STATS ChipPAC, ISSI, OmniVision, and Montage Technology. Micron’s acquisition is proposed for $23 billion. So, there will be a significant development in the semiconductor industry from China, stimulated by PE investment there.

Q: After more or less 35 prime years of semiconductors, we are seeing our second generations just entering this fascinating industry which infuses semiconductors in most of the other industries. What is your message to our younger generation engineers who may see a much transformed semiconductor industry than we saw?

A: The best is yet to come. So far we have seen many styles of chips in the form of ICs, now SoCs. Going forward system design will be in the mainstream. Design and verification is still in infancy. Although large designs are being developed, the verification is still being done in the same way as we were doing 30-40 years ago. We have to think in terms of system design from the beginning; define, implement and verify at that level.

Q: This is Mentor’s 11[SUP]th[/SUP] U2U conference, similar events are happening in other EDA companies. Considering these initial years of this century as pivotal for next generation semiconductor industry, what is the most important observation in the design community you think should be continued or changed?

A: The semiconductor industry is a learning industry; it needs a lot of collaboration and interaction. Today there are many ways of sharing information across the world through internet, webinars, tele-conferences, and so on. However, the design engineers still require direct physical interaction. So, focused User2User and other technical conferences are the best forums for sharing and learning. There is no end to these conferences, they will continue. The attendance in U2U conferences keeps increasing; we hold U2U conferences in all user dominated regions across the world.

It was a very inspiring discussion with Dr. Rhines. We eagerly look forward to the best yet to come in the semiconductor industry!

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

Posted on

IP-SoC Rebound in 2015 !

IP-SoC Rebound in 2015 !
by Eric Esteve on 11-12-2015 at 7:00 am
Categories: IP

Going to IP-SoC every year since 2006, I have enjoyed the conference as it’s the only one 100% IP focused and a very good opportunity to network within this rather small ecosystem of IP vendors… but I must admit that, since 2012, the attendance tend to be lower than before. Because of the well-known “chicken & egg” theorem, low attendance was linked with less presentation. Let’s stop IP-SoC bashing here, because the above is not true anymore (just take a look at the impressive presentation list below). It’s really amazing to see the foundry corner, including SMIC as well as TSMC (the clear #1) and STMicroelectronics and GlobalFoundries both communicating about FD-SOI.

You may wonder why 3 foundries out of the top 5 (TSMC, GlobalFoundries and SMIC) are actively participating to IP-SoC as it was not the case in the early 2010’s? I would say that, right after the 2008-2010 economic crisis, the semi (and IP) industry was captivated by China where economy was growing by 10% or so every year and semi start-up were created at the same rate than in the Silicon Valley in the 1990’s. In the same time we have perceived something like “Europe-bashing”, the real business was in Asia, Europe had no future, and so on…

Now, if you consider that TSMC collaborates with IMEC (Leuven, Belgium) to “joins forces with IMEC to strengthen their global R&D”, that GlobalFoundries has licensed FD-SOI technology to STMicroelectronics and the related foundation IP to LETI, you realize that Europe is still a great place for innovation. Nevertheless, if innovation is mandatory to sustain semiconductor market dynamic, you need to sell chips or wafers to create healthy business.

What are the buzzwords when talking about the semiconductor future? Big data (servers), IoT and Automotive are the businesses expected to bring $ value and profit tomorrow. I left Mobile market apart, on purpose, as the market is going to commoditize, still providing high value but lower profits. Big data is clearly dominated by the US and Intel. Which semiconductor market segment is expected to provide the higher CAGR up to 2020? It’s the Automotive market segment. Who are the big players in this segment? Many of them are located in Europe (Japan, USA too).

Even if I don’t think that IoT killer application will come from Europe but rather from the US (or China?), you will find a bunch of semi companies selling microcontrollers, like NXP, STMicroelectronics or Infineon able to address IoT needs.

You will find a well busy track dedicated to IoT, including a panel. The other tracks deal with IP strategy, standard and innovation in IP, FPGA, or Embedded… By the way, I will be happy to present a paper “MIPI beyond Mobile…”, reworked from the presentation made during the DAC 2015 and nominated from “Best Paper Award”. See you in IP-SoC in Grenoble, on December the 2[SUP]nd[/SUP] and 3[SUP]rd[/SUP] !

From Eric Esteve from IPNEST

IP-SoC 2015 presentations:

Foundry Corner and Innovation in Technology
[TABLE]
|-
| –
| “Smic’s IP Platform and Design Services” by Hongying Wu, Sr Director of IP Alliance Program, SMIC
|-
| –
| “Automotive Electronics” by Marco Vrouwe, TSMC
|-
| –
| “FDSOI is taking on speed as platform and a European focus project” by Gerd Teepe, GlobalFoundries
|-
| –
| “FDSOI IP Shop: The key enabler of success” by Patrick Blouet, Collaborative program manager, STMicroelectronics
|-

• IP SoC Strategies and Vision
[TABLE]
|-
| –
| “Strategies for SoC / IP Design for Emerging Applications:An Indian perspective” by Samir Patel, Sankalp Semiconductor
|-
| –
| “Assessing and managing the IP Sourcing Risk” by Philippe Quinio, STMicroelectronics
|-
| –
| “Semiconductor Industry Consolidation Wave: What is left for IP Companies” by Sanjeev Kumar Sharma, Terminus Circuits
|-

• Standards and Innovation in IP Design
[TABLE]
|-
| –
| “MIPI Beyond Mobile: Preferred IP for IoT, Wearable, Automotive” by Eric Esteve, IP Nest
|-
| –
| “Why Embedded NVM is an Important Part of Every SoC” by Xerxes Wania, Sidense
|-

• What’s special on FPGA
[TABLE]
|-
| –
| “What an FPGA Vendor Knows about IP Reuse” by Ron Wilson, Altera
|-
| –
| “Qualifying and tuning external IP though FPGA prototyping” by Huy-Nam Nguyen, Atos
|-

• Technical Highlights in Power Optimization
[TABLE]
|-
| –
| “Power Planning and Timing Signoff Solutions” by Jean-Luc Pelloie, ARM
|-
| –
| “Autonomous Power Subsystem IP” by Drew Wingard, Sonics
|-

• Embedded Systems
[TABLE]
|-
| –
| “Embedded Software is Everywhere” by Colin Walls, Mentor Graphics
|-

• IoT
[TABLE]
|-
| –
| “IP That Will Drive Energy-Efficient IoT Designs” by Philippe Borges, Field Applications Engineer, Synopsys
|-
| –
| “Making IoT Security a Reality” by Bart Stevens, Director of Product Management, Mobile and Networking Hardware Security Solutions, Inside Secure
|-
| –
| “Innovative Energy Savings Using GZIP IP Within IoT Devices” by Nikos Zervas, CAST
|-
| –
| “The impact of IoT on IP Program” organized by Hal Barbour (CAST) with the participation of Nikos Zervas (CAST), Bart Stevens (Inside Secure), Philippe Borges (Synopsys), Philippe Quinio (STMicroelectronics), Matjaz Breskver (Beyond Semiconductor)

More presentation or registration here
|-

More articles from Eric…

Posted on

HiSilicon’s Experience with Synopsys ICC2

HiSilicon’s Experience with Synopsys ICC2
by Daniel Nenni on 11-11-2015 at 4:00 pm
Categories: EDA, Synopsys

At TSMC’s OIP Symposium last month, Zhe (Jared) Lui of HiSilicon presented their experiences with Synopsys’ ICC2 physical design suite.

Jared started by giving an overview of Huawei and HiSilicon. HiSilicon is the semiconductor arm of Huawei. I assume everyone knows who Huawei is. To a first approximation they are the Cisco of China, although they are also in consumer facing businesses. In particular, they are currently (Q2) #3 in worldwide smartphone market share (ahead of Xioami and Lenovo/Motorola). They are the largest telecommunication manufacturer in the world, having passed Sweden’s Ericsson a couple of years ago.

I was surprised to find that HiSilicon started in 1991. They are the #1 fabless company in China, with over 5500 employees. They are headquartered in Shenzhen (just across a river from Hong Kong if you are unsure where that is) but have over 20 R&D centers in 10 countries and regions. If you have driven down Central expressway where it goes over San Tomas expressway you have seen their Silicon Valley campus.

Their current production smartphone chips are in TSMC 28nm HPC. For example, the Kirin 935 application processor for the Huawei P8 MAX was created by HiSilicon. It contains an 8 core big-LITTLE ARM Cortex A53e/A53, runs at either 2.2GHz or 1.5GHz, has an ARM Mali 628 GPU. It has a dual SIM LTE Cat 6 modem (300Mb/s downlink, 50Mb/s uplink).

In networking they are already at 16nm. In fact their 32-core ARM Cortex-A57 networking chip was the world’s first 16nm production tapeout at TSMC using Synopsys physical design (in March of this year). Each ARM CPU is 1.6M instances with 78 macros (and there are 32 of them) so this is a big chip.

Jared then talked about the main implementation challenges at advanced nodes:

  • colored flow for advanced patterning
  • vertical placement constraints to to enable pin accessibility on ever shrinking standard cell layouts
  • highly heterogeneous metal stacks (low levels metals have high resistance)
  • increasing electromigration issues due to high switching activity and high power draw
  • on-chip variation and the need for increased accuracy, parametric OCV
  • timing accuracy in the multi-patterned world, and low voltage delay effects

Synopsys introduced IC Compiler II (ICC2) in March of 2014 with a promise of 10X increased throughput and productivity compared to what is just called IC Compiler (but I’ll call it ICC1 to be clearer). The promise of the same or better results faster interested HiSilicon, thus initiating a close working partnership to see if ICC2 could deliver on that promise. HiSilicon and Synopsys initiated a partnership in 3 phases.

Phase 1, full P&R on complex, high performance CPU blocks. On a design with about 600K cells in TSMC 16FF+ with 2.5GHz clock, multi-mode multi-corner timing IC2 then ICC2 reduced run time from 1.5 days to 0.3 days meaning multiple iterations per day. This is a speedup of 4.6X.

Phase 2, full P&R on high capacity blocks from GPU designs. On a design with 3.4M cells in TSMC 16FF+, 700MHz, MCMM, the speedup was 3X from over 4 days to less than 1.5 days.

Phase 3, P&R of latest node silicon validation vehicle. 1.5M cells, a TSMC process (unnamed, but I’m guessing 10nm), 2GHz+, MCMM, power-aware flow. Result was a run time of about 30 hours delivering signoff quality timing and DRC.

Some of the key features of ICC2 that contributed to HiSilicon’s success:

  • advanced timing analysis: accurate timing at advanced nodes and low voltage
  • automatic clock layer optimization: use low resistance metal layers for long nets
  • post-route clock closure
  • power reduction with DesignWare and DC Ultra for datapaths
  • advanced power recovery in PrimeTime: downsizing cells on positive slack paths, Vt cell swaps for power recovery

The end of the story is that ICC2 delivered 3-5 times runtime benefit while using less than half the memory, and delivering better QoR out-of-the-box. The reduction of design iterations further shortened development time. HiSilicon have decided to deploy ICC2 in production for new node design work, and are also expanding their collaboration with Synopsys and TSMC going forward.

If you attended OIP, even if you didn’t attend this session, the slides are in the handout book. Or you can get more information on ICC2 HERE.

Posted on

It’s All about Packaging — In this Material World, Who Is Your Partner?

It’s All about Packaging — In this Material World, Who Is Your Partner?
by Deborah GeigerSEMI on 11-11-2015 at 3:20 pm
Categories: ESD Alliance, Events, Semiconductor Services

GSPMO%20Image

By Dr. Dan Tracy, senior director, Industry Research and Statistics, SEMI

With the recent release of Apple’s 6s and the form factors of internet-enabled mobile devices and the emergence of the IoT (Internet of Things), advanced packaging is clearly the enabling technology providing solutions for mobile applications and for semiconductor devices fabricated at 16 nm and below process nodes. These packages are forecast to grow at a compound annual growth rate (CAGR) of over 15% through 2019. In addition, the packaging technologies have evolved and continue to evolve so to meet the growing integration requirements needed in newer generations of mobile electronics. Materials are a key enabler to increasing the functionality of thinner and smaller package designs and for increasing the functionality of system-in-package solutions.


Figure 1: Packaging Technology Evolution – Great Complexity in Smaller, Thinner Form Factors, courtesy of TechSearch International, Inc.

The observations related to mobile products include:

  • New package form factors to satisfy high-performance, high-bandwidth, and low power consumption requirements in a thinner and smaller package.
  • Packaging solutions to deliver systems-in-package capabilities while satisfying low-cost requirements.
  • Shorter lifetimes and differing reliability requirements. For example, high-end smartphones and tablets, the key high reliability requirement is to pass the drop test; and packaging material solutions are essential to delivering such reliability.
  • Shorter production ramp times to meet time-to-market demands of end product. This is becoming critical and causes redundancy in capacity to be required, capacity that is underutilized for part of the year

Packaging must provide a low-cost solution and have an infrastructure in place to meet steep ramps in electronic production. The move towards bumping and flip chip has only accelerated with the growth in mobile electronics, though leadframe and wirebond technologies remain as important low-cost alternatives for many devices. Wafer bumping has been a major packaging market driver for over a decade, and with the growth in mobile the move towards wafer bumping and flip chip has only accelerated with finer pitch copper pillar bump technology ramping up. Mobile also drives wafer-level packaging (WLP) and Fan-Out (FO) WLP. New wafer level dielectric materials and substrate designs are required for these emerging package form factors.

Going forward, the wearable and IoT markets will have varying packaging requirements depending on the application, the end use environment, and reliability needs. Thin and small are a must though like other applications cost versus performance will determine what package type is adopted for a given wearable product, so once more leadframe and wirebonded packages could be the preferred solution. And in many wearable applications, materials solutions must provide a lightweight and flexible package.

Such packaging solutions will remain the driver for materials consumption and new materials development, and the outlook for these packages remain strong. Materials will make possible even smaller and thinner packages with more integration and functionality. Low cost substrates, matrix leadframe designs, new underfill, and die attach materials are just some solutions to reduce material usage and to improve manufacturing throughput and efficiencies.

SEMI and TechSearch International are once again partnering to prepare a comprehensive market analysis of how the current packaging technology trend will impact the packaging manufacturing materials demand and market. The new edition of “Global Semiconductor Packaging Materials Outlook” (GSPMO) report is a detailed market research study in the industry that quantifies and highlights opportunities in the packaging material market. This new SEMI report is an essential business tool for anyone interested in the plastic packaging materials arena. It will benefit readers to better understand the latest industry and economic trends, the packaging material market size and trend, and the respective market drivers in relation to a forecast out to 2019. For example, FO-WLP is a disruptive technology that impacts the packaging materials segment and the GSPMO addresses this impact.

The new report will be published later in the fourth quarter of 2015. For more information, download the 2013/2014 sample report and/or to preorder, please contact SEMI customer service at 1.877.746.7788 (toll free in the U.S.) or 1.408.943.6901 (International Callers). For further questions, please contact SEMI Global Customer Service 1.408.943-6901 or email mktstats@semi.org.

Posted on

28nm FD-SOI: A Unique Sweet Spot Poised to Grow

28nm FD-SOI: A Unique Sweet Spot Poised to Grow
by Pawan Fangaria on 11-11-2015 at 12:00 pm
Categories: FD-SOI, Foundries, STMicroelectronics

I have been silently watching STMicroelectronics pursuing FD-SOI technology since quite a few years. FinFET was anyway getting more attention in the semiconductor industry because of several factors involved. But from a technology as well as economic perspective there are many plus points with FD-SOI. I remember my debate, two years ago, with an IP provider for choosing between FD-SOI and FinFET for some of his IP blocks. Although we were more positive towards FD-SOI the debate was inconclusive at that time, but today the 28nm FD-SOI technology node stands to win as the best value added proposition for the emerging markets such as IoT, automotive, consumer, mobile, and so on. To expand the FD-SOI technology ST has also signed strategic licensing of their 28nm FD-SOI technology with other foundries including Samsung and GLOBALFOUNDRIES. Samsung entered into licensing agreement with ST for manufacturing collaboration on 28nm FD-SOI in mid 2014.

The industry leaders including ST are looking at scaling down the FD-SOI technology to 20nm and even 14nm to gain FinFET like performance at lower power and cost. GLOBALFOUNDRIES has already announced the availability of their own FD-SOI technology at 22nm (the 22FDX platform). In the near future we can see more development on this technology front. How’s the technology poised to provide high-performance and low-power at a low cost? I investigated in detail in a whitepaper at ST’s website.


This is an image from STMicroelectronics showing the flexibility of 28nm FD-SOI technology to modulate the effective channel length of transistors with the same abstract. The leakage current is reduced by an order of magnitude through poly-biasing. There is no junction leakage in this technology.

A single 28nm FD-SOI technology node provides a wide range of operating voltages between 0.6V and 1.1V for trade-off between power and performance. Specialized multi-threshold-voltage (V[SUB]T[/SUB]) libraries such as RVT (Regular V[SUB]T[/SUB]) and LVT (Low V[SUB]T[/SUB] ) are available.

Major EDA / IP vendors have included support of FD-SOI technology in their design flow and availability of IP on FD-SOI. Last year Cadence announced availability of IP solutions on 28nm FD-SOI process. This year Synopsys announced support of FD-SOI technology in their Lynx Design System. Mentor supports FD-SOI process in their tools and design flow as well. There are many others looking up at FD-SOI technology.


A powerful mechanism in FD-SOI technology is body-biasing (enabled in ST’s 28nm FD-SOI technology) with extremely thin buried oxide (BOX) for controlling the channel to further boost the performance or lower the power. The biasing can be modulated dynamically over a wide range during the transistor operation.

The body-biasing provides additional benefits in process compensation. In the above graph, the worst case (WC) performance trend is built using slowest (SS) and leakiest (FF) process corners. With body-biasing the SS and FF process spreads are masked together, thereby recovering performance by 17% without any dynamic power penalty.

The FD-SOI is a planar technology, simple to process at significantly lesser cost, without channel doping, and without much process variation as seen in FinFET technology. There are fewer mask layers and fewer immersion litho layers compared to FinFET technology.

ST’s standard-cell libraries based on FD-SOI technology are optimized for mainstream, low-power and high-performance applications and come in different flavours. There are mask programmable ECO cells which can be used to implement changes by changing metal layers only without the need for full mask-set reorder, thus reducing implementation time and cost. One can choose between 12-track high-performance and 8-track high-density architectures to optimize the PPA (Power, Performance and Area).


There is a wide variety of flip-flops that enable designers to choose the appropriate ones for right trade-off in their designs. Also, there are innovative multi-bit flip-flops to reduce clock-tree load and thus overall dynamic power. The leakage power is also reduced due to sharing of clock inverters between these multi-bit flip-flops. There are multi-stage synchronizers to mitigate the effects of metastability in multiple clock domains circuits.

There is a whitepaperat ST website written by N Shivaram Venkatesh and Bedanta Choudhury. Read this whitepaper to know more details about ST’s offering of standard cell libraries with FD-SOI technology for modern SoC applications. The document also provides benchmarks of 28nm FD-SOI 8T technology against other similar HKMG external references.

The SoCs are dominated by standard cells as they occupy more than half of the area, consuming almost 3/4[SUP]th[/SUP] of total power, and falling in 3/4[SUP]th[/SUP] of the critical paths on the chip. So, it’s essential that standard cells are optimized for PPA in order to optimize the SoC.The FD-SOI technology is in a sweet spot from where it can provide differentiated PPAs for different market segments.For example, ultra-low-power and ultra-low-leakage libraries can be used in IoT and wearable devices; low-power, low-costlibraries can be used in RF analog transmission, a key requirement for smartphones and network applications.

Also read this articleon the CEA-Leti’s announcement of “Silicon Impulse”, a platform to support and broaden the use of FD-SOI technology.

GLOBALFOUNDRIES announcement for support of FD-SOI at 22nm is HERE
Samsung announcement of licensing ST’s 28nm FD-SOI process is HERE

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

Posted on

GlobalFoundries Visit – Part 2 – Waking the Sleeping Giant

GlobalFoundries Visit – Part 2 – Waking the Sleeping Giant
by Scotten Jones on 11-11-2015 at 8:00 am
Categories: Foundries, GlobalFoundries

In part one of this blog I described a visit to GlobalFoundries (GF) Fab 8 site in Malta New York by Daniel Nenni and myself. In this part 2 of the blog, I will describe the second day of our trip when we visited Fab 9 in Burlington Vermont. Before we got to Burlington I thought it would likely be a letdown after seeing the state-of-the-art Fab 8, but Burlington turned out to be just as interesting as Malta.

Before describing the Burlington site visit I should set the stage by describing GF’s business unit structure. GF is organizes into three business units:
[LIST=1]

  • CMOS Platforms – GF side of the business comes from the AMD and Chartered acquisitions and GF although the IBM acquisition adds technology.
  • Application Specific Integrated Circuits (ASIC) – comes from the IBM acquisition.
  • RF – comes primarily from the IBM acquisition although GF has some presence here as well from the Singapore site (former Chartered).

    Burlington Site
    Burlington is another large site and our visit began by working our way through two security gates and finding the lobby (actually the site is in Essex Junction near Burlington).

    The first briefing of the day was by Janette Bombardier, the site Vice President and location manager. The Burlington site has been in operation since 1957 and is the largest private employer in Vermont. The site uses 3.2 million gallons of water per day including 2 million gallons per day of ultra-pure water. The water comes from lake Champlain and waste water treatment is done on-site. They have reduced their water usage by 30% over the last decade. The site is fed by 150 Kilovolt power lines and they have their own smart grid delivering peak power of 65 megawatts, they have reduced peak power by 7 megawatts. There are 60,000 sensors and meters monitoring the site. The Essex Junction site and the Williston site are a combined 750 acres. Janette was very proud of the sites environmental record and highlighted the many awards they have won in this area (see Janette’s presentation at the end of this section for a list of the awards). In my experience older fab sites have not always had the best environmental record and it was refreshing to see an older site with an environmental focus.

    The Burlington site hosts several different functions:

    • Burlington is the first trusted foundry for the United States Government. Buildings 970 and 973 are now run as one 200mm wafer fab with 40,000 wafers per month capacity after a $55 million dollar capacity expansion announced the day after our visit. The fab includes over 1,400 tools and supports 30 different unique flows.
    • Burlington has a mask shop on-site with 70 tools, approximately 180 employees, and working with their partner – Toppan they produce 15,000 to 18,000 masks per year.
    • Test and final product distribution for the former IBM microelectronics division is also done at Burlington.
    • There are quality labs and information technology on site.
    • A large office complex hosts General Dynamics, the Vermont State Department of Children and Families and some IBM functions as well as GF activities.
    • A 300KW solar array test bed – the Vermont Photovoltaic Regional Test Center in partnership with Sandia and the DOE. The test bed gives the partnership a cold weather/cloudy location test capability.

    In terms of the site history:

    • 1957 to 1990 – wire relays – captive logic and memory supplier to IBM, first 200mm wafer fab in the world. Five generations of wafer sizes (presumably 3”, 100mm, 125mm, 150mm and 200mm).
    • 1990 to 2000 – sole source for IBM processes, entered OEM business for fab fill, churn of equipment and facility, DRAM manufacturing followed by logic. IBM exited the DRAM business in the late 90s.
    • 2000 to 2003 – final new server ramp, significant downsizing, future viability dependent on developing and executing a new business model.
    • 2003- 2006 – OEM business in ASICs, >50% factory load, first trusted foundry.
    • 2007 to 2010 – ASIC OEM business declined, started new RF business (7RFSOI and SiGe5PSAe) focused on cell phone Front End Module.
    • 2011 to 2014 successful RF business.

    The Burlington site products go into HDTV, Video, DVD, laptops, Automotive, Printers, etc. They Build design for others, some as a foundry and some as ASICs with much earlier involvement.

    They have ASIC design tools that are really good if you need tight timing and complex designs. They are more focused on communications and consumer now, more cost sensitive.

    The Burlington Fab 9 briefing deck is HERE.

    ASIC Group
    Our second briefing of the day was given by Jim Rogers director of ASICs. Also present were Duncan Needler from Strategic Marketing and Mark Kimely and Paul Zilkowski.

    I have to admit that I though ASICs were kind of a dying business and no longer very interesting but I was about to learn differently. In fact I now think this part of the IBM Microelectronics acquisition could be hugely important to GF!

    IBM has been the number one ASIC supplier into networking for over ten years. They don’t disclose their revenue but noted they are a multiple of eSilicon (a $250 million US dollar business, Faraday (UMC tie in) or GUC (TSMC tie in) in size (Gartner reportedly estimates that the former IBM ASIC business is over $1 billion US dollars).

    Networking customers are power and cooling limited. They have fixed power budgets for each application and want to get more performance within the power budget. Designs are becoming more parallel, some frequency scaling as well but parallelism is growing and even with node shrinks die sizes are growing. They are focused on MIPs/watt.

    Their first ASIC offering was at 500nm. They have high performance IP, unique memory options, they are an ARM licensee now (they have been for a while but didn’t announce it). With the GF acquisition they have more scale to work with, Malta is a lot bigger than East Fiskill (Fab 10, the former IBM 300mm site). They have been doing very large ASICs for external customers plus IBM processors (they also did networking for IBM when IBM was still in networking). They have pre verified IP and test and insertion so the entire system works. They typically sell packaged – tested parts with a margin, they are sort of intermediate between a foundry and a standard product. They will sometime sell tested wafers. Wafer sort is done internally but they use Outsourced Assembly And Test (OSAT) for packaging and class test. They can take a hand off at several levels, turnkey or net lists, and then they do the physical design.

    The ASIC group is currently doing ASICs in 90nm and 65nm bulk and 45nm and 32nm Partially depleted SOI technologies (PDSOI). They have a 30G backplane and 56G is available to design now as well as PCI-express gen 4 (Dan noted that other suppliers are really struggling trying to get 56G working). They also offer Ternary Content Addressable Memory (TCAM) where memory is accessed by data and not by address; this is very useful for networking tables (TCAM uses a special bit cell). They also have smaller SRAM array capability than other IP vendors or TSMC, “best dense SRAM macro in the industry”. They have more that 50 ASICs with TCAM in production (6 generations). They can make the largest TCAMs work (Dan noted that in his experience it is hard to make TCAM work). They supply all of the major network companies and have been the #1 ASIC supplier for wired communications for 11 years. They think having IP, fab, and technology development under one roof is an advantage. They have global design centers, have done some of the industry’s most complex ASICs and have an outstanding record of success.

    As interesting as all of that is, they then went on to describe their new FX-14 ASIC offering utilizing the 14LLP process manufactured at Fab 8 in Malta. As an outside observer one concern I had for GF was how they would differentiate themselves from Samsung and become more than a second source when they are licensing the 14nm process from Samsung. While we were in Burlington we heard the AMD has committed to 14LPP giving GF a volume first source customer to drive yield learning. Now GF will also have a pipeline of ASIC designs on 14LPP from the ASIC group. This announcement combines world class 56G SERDES and multi ARM core generation support, high capacity state-of-the-art 14nm manufacturing at Fab 8 on a cost effective 14LLP process with over a decade of ASIC industry leadership!

    The 14LPP FinFET architecture provides more performance per watt for connect, compute and store application and fewer watts per GHz for mobility and wireless applications. 14LLP was qualified in Q3 of 2015 and will be in volume production in 2016. 14LPP offers a 55% area reduction, up to a 50% power reduction and 85% less leakage than the 32nm ASIC technology. 14LPP will be supported with industry standard tools (IBM was proprietary tool based), there will be multiple Vt libraries for power/performance tradeoffs and an expanded IP portfolio. FX-14 will offer 64 bit ARM cores including A53 and A72 as well as 32 bit cores, 56Gbps and multiple 30Gbps SERDES designs, leading edge TCAM and the industry’s highest density and performance SRAM.

    To my view the combination of the expertise of the IBM ASIC team with the GF manufacturing scale and improved access to IP and design tools offers a very powerful combination. Jim Roger’s apparently feels the same way because he smiled from ear to ear through his entire presentation.

    The FX-14 briefing deck is available HERE.

    RF Group
    Bami Bastani, the senior VP for RF gave us a briefing on the RF business. Also present was Stephen Lace RF Chief Technical Executive, product managers Peter and Christine and Duncan Needler from Strategic Marketing.

    The front end of cell phones has to support a variety of different frequency bands and standards for 3G and 4G data and voice. The Front End Modules (FEM) may include multiple antennas with antenna tuning for each antenna, antenna switching, multiple filters and multiple power amplifiers. IBM’s combination of Partially Depleted SOI technology (PDSOI) and Silicon Germanium (SiGe) technology have made them a huge player in this space. RF SOI utilizing PDSOI has emerged as the technology for RF switches as well as some antenna tuning and a small amount of power amplifier applications. SiGe is used to address power amplifiers and also automotive radar. IBM’s RF SOI technology has shipped over 17 billion parts and the SiGe technology has shipped over 3 billon products although power amplifiers are still dominated by Gallium Arsenide (GaAs). SiGe power amplifiers are also used in WiFi modules for cell phones. They 65nm RFCMOS typically used for WiFi don’t have a good enough power amplifier and they are often bypassed for a SiGe power amplifier. RF SOI devices reduce parasitics, provide higher Q – lower loss, increased isolation and linearity and better economics than III-V solutions such as GaAs. RF SOI can be produced on 200mm and even 300mm wafers whereas GaAs is still on 150mm wafers.

    The acquisition of IBM microelectronics by GF provides a global network for RF as well as increased investment. While we were in Burlington we heard about a $55 million dollar investment in additional capacity in the Burlington fab. GF’s Singapore site also has 200mm and 300mm capacity for RF. GF has bene doing some 300mm RF in Singapore for capacity reasons but they don’t see it as more economical than 200mm due to substrate cost and depreciations. Moving forward to 5G and millimeter wave applications 45nm RF SOI likely on 300mmm will offer the next generation solutions. They will still support 180nm/130nm on 200mm for 3G and 4G and then do 45nm for 5G.

    The current market for RF SOI is estimated to be approximately 60,000 wafers per month primarily driven by switch and tuner applications.

    By producing RF on SOI substrates logic can be integrated onto the same product. The RF business is a classic foundry business with customers doing their own designs and buying wafers from GF. GF does provide some simple standard cells. GF RF business is the leader in the market shipping primarily from Burlington with some capacity coming from Altis in Europe (former IBM site) and Singapore ramping up.

    The RF business offers another growth path for GF.

    The RF presentation is available HERE.

    Mask shop
    We ended our visit to Burlington with a tour of the mask shop. The mask shop supports masks sets all the way down to 7nm and has EUV mask capability. Currently the mask shop supports Burlington (Fab 9) and East Fishkill (Fab 10) but they are now working on masks for Fab 8 and may support provide support to other GF sites as well.

    Conclusion
    Often acquisitions are touted as providing “synergies” that are hard to envision and even harder to realize. After visiting Fab 8 in Malta and Fab 9 in Burlington the potential synergies are very clear.

    • The acquisition of an experienced IBM development team offers GF the potential to develop their own 10nm and 7nm technologies as opposed to licensing technologies from others as they had to do at 14nm.
    • The former IBM ASIC business is a leading supplier of ASICs for networking. The combination with GF provides more advanced process technology, manufacturing scale and a parent company in the same business. There is a potential here to make the ASIC business stronger while providing GF with a customer stream for the 14LLP technology.
    • The former IBM RF has been capacity and resource constrained. They now have access to greater resources and capacity to drive into 5G and continue to support 3G and 4G.

    The bottom line to me is the acquiring the IBM microelectronics business fill gaps in GF and in the IBM businesses and offers the opportunity for real and lasting synergy. Of course as we discussed in part one execution will be key. Watching how this plays out over the next couple of years will be fascinating and will ultimately determine whether GF can become a truly viable leading edge pure play foundry.

    You can read part one HERE.

    • Posted on

    64-bit for the masses with Cortex-A35

    64-bit for the masses with Cortex-A35
    by Don Dingee on 11-10-2015 at 12:00 pm
    Categories: Arm, IP

    It has been four years since the announcement of the ARMv8 instruction set, three years since the launch of the ARM Cortex-A57 and Cortex-A53 cores, and two years since the Apple A7 with its “Cyclone” core blew away any misunderstanding of 64-bit as being just for servers.

    There is, however, still this idea that 64-bit is only for flagship mobile devices. Continue reading “64-bit for the masses with Cortex-A35”

    Posted on

    Verification with Tcl for what? – part 2

    Verification with Tcl for what? – part 2
    by Anatoly Myshkin on 11-10-2015 at 7:00 am
    Categories: EDA

    In Orion Bytes we use Tcl both for the internal research, product and different verification services. We use also SystemVerilog UVM and Python based Cocotb for different approaches. I think it’s no need to deep into the SystemVerilog and UVM principles here – today’s main verification fashion is well described through the web and books.
    Continue reading “Verification with Tcl for what? – part 2”