One of the most frequently discussed concerns regarding FDSOI adoption is the higher starting wafer cost compared to bulk technology. This discussion was also brought up after my earlier post, Continue reading “FDSOI Cost Analysis – Part I”
Profile of an IoT Processor for Industrial, Consumer Markets
The intersection of data with intelligent machines is creating new possibilities in industrial automation, and this new frontier is now being increasingly known as the Industrial Internet of Things (IIoT). However, if there is a single major stumbling block that is hindering the IoT take-off at the larger industrial scale, it’s security.
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SEMI Releases Industry’s First “Global 200mm Fab Outlook to 2018” and Announces Webinar
SEMI, the global industry association advancing the interests of the worldwide electronics supply chain, today (October 19) published a new report, “Global 200mm Fab Outlook to 2018.” According to the report, worldwide 200mm semiconductor wafer fab capacity is forecast at 5.2 million wafer starts per month (wspm) in 2015 and expanding to 5.4 million wspm in 2018. In addition to the release of the report, SEMI is offering two complimentary webinars (November 2 at 5:00pm Pacific; November 3 at 8:00am Pacific) with highlights of the newly released 200mm report.
Based on the rapidly increasing number of internet-enabled mobile devices and the emergence of the IoT (Internet of Things), demand for sensors, MEMS, analog, power and related semiconductor devices is growing. While these devices are critical to enable the new era of computing, the applications do not require leading-edge manufacturing capability, and this demand is “breathing new life” into 200mm fabs.
Highlights of the results of the SEMI 200mm report include:
- 36 facilities are expected to add 300,000 to 400,000 200mm wspm from 2015 through 2018.
- Capacity investment is expected to total over US $3 billion during the 2015 to 2018 period.
- Eight new facilities/lines are expected to begin operation from 2015 through 2018.
- China and Southeast Asia are forecast to lead the expansion in 200mm fab capacity.
Source: Global 200mm Fab Outlook, SEMI; October 2015
Complimentary webinars will be held on November 2at 5:00pm Pacific and November 3 at 8:00am Pacific. In the webinar ( www.semi.org/en/iot200mmwebinar), lead analyst Christian G. Dieseldorff will share highlights of the new Global 200mm Fab Outlook.
For more information, download the Global 200mm Fab Outlook sample report, contact SEMI customer service at 1.877.746.7788 (toll free in the U.S.) or 1.408.943.6901 (International Callers), or email mktstats@semi.org. For information on all SEMI Market research reports, visit www.semi.org/en/MarketInfo.
About That Landauer Limit…
You may have heard of the Landauer principle or the Landauer limit. This defines a lower bound on switching power dissipation in any form of digital circuit. Rolf Landauer first presented this principle in 1961, while working at IBM. It’s not limited by how the circuit is built – you can use FinFETS or spintronics or even dilithium crystals. The bound is determined by the laws of thermodynamics and is believed to set a fundamental lower limit to switching power.
A condensed version of the principle goes roughly like this. You can’t do useful work (computation) without dissipating heat. For a digital system, this originates from a decrease in the entropy of the system as computation proceeds. When data passes through a 2-input NAND gate, information is lost (because you started with 2 bits but get out only 1 bit). You have effectively erased 1 bit, so information entropy (Shannon) decreases by ln(2). Landauer assumed a correspondence between physical and information entropies leading to a physical entropy loss of k[SUB]B[/SUB]ln(2), where k[SUB]B[/SUB] is Boltzmann’s constant. This decrease must be offset by an increase in entropy in the surrounding environment, at least some of which will manifest as dissipated heat. The second law of thermodynamics says this must be at least TdS (T is temperature and dS is the change in entropy). And that’s Landauer’s principle: each loss of information of one bit, resulting from convergence in logic or other erasure of bits (through a reset for example), results in at least k[SUB]B[/SUB]Tln(2) of heat dissipated.
At room temperature this is about 3×10[SUP]-21[/SUP] joules/bit, which sounds negligible. But consider a 1 billion gate circuit running at 100MHz. Maybe 10% of the circuit is active at any time so, assuming bit loss is the same order as this number, you have 10[SUP]8[/SUP]x10[SUP]8[/SUP]x3x10[SUP]-21[/SUP] or 30uW. Still not bad. Now run 10 iterations of Moore’s law (assuming it continues). That’s a 10[SUP]3[/SUP] increase in gate-count and a 10[SUP]3[/SUP]increase in speed. Now you’ve got 30W. Not so ignorable, especially if this is an absolute minimum and a real design would be worse. Going to more advanced technologies doesn’t help; the quantum computing folks feel they are already in range of the Landauer limit.
However, the physics debate is not yet over. There have been vigorous efforts to demonstrate that the theory is flawed, not in basic thermodynamic principles and the expectation that there will be some lower limit, but instead in the the methods of proof and the specific limit that Landauer sets. These argue that Landauer and defenses of Landauer are based on consideration only of special cases and ignore effects that should be included. Whether right or not, it looks like there are soft spots in the theory which maybe should be renamed “Landauer’s Conjecture”, rather than “Landauer’s Principle”.
Yet again, there have been recent experiments which confirm that heat dissipated in a specialized bit erasure aligns precisely with Landauer’s prediction. So while the theory may need to be shored up, the limit may still be a practical reality.
And yet again, Landauer himself argued that reversible logic could break this bound since entropy need not increase in reversible computations. In a reversible gate, you can recover the state of the inputs given the state of the outputs, which requires that each gate has as many outputs as inputs, so logic would be quite a bit bulkier. However, it has been pointed out that among other disadvantages, the increased interconnect required with this design style would result in increased interconnect power dissipation which would overwhelm any switching savings.
And for the final yet again, comments by Cavin and others (comments section here and conclusions here) point out that in addition to the basic information entropy limits used by Landauer, there are dissipative mechanisms in the control of any kind of switch which themselves will have some unavoidable minimum and should therefore be included in a minimum energy calculation. And of course these could only increase the minimum threshold.
Wrapping up, the theory behind the Landauer limit is not entirely solid, but experiment backs up the number and objections mostly seems to be along the lines of the theory being based on ideal switches with zero energy cost in switching. Real dissipation can only be worse and Landauer is very probably an absolute if unattainable lower bound to power. So get ready for the big showdown (in 15 years or so): Moore’s law versus the second law of thermodynamics.
How LETI IP will speed-up GlobalFoundries 22FDX™ ASIC Development
GlobalFoundries has positioned FDSOI proposal -22FDX- to provide better performance and power dissipation than competitive FDSOI offers on 28nm node. The FDSOI licensing agreement between LETI and GlobalFoundries is only a couple of months old (July 2015), but the real work has started in Dresden as several engineers from LETI are working to secure FDSOI porting in GlobalFoundries wafer Fab. But the partnership goes further as Leti will also provide GlobalFoundries’ customers circuit-design IP, including for its back-bias feature for FD-SOI, which enables exceptional performance at very low voltages with low leakage. I like the picture below, extracted from a presentation made by Rutger Wijburg, senior vice president and general manager of fab management at Globalfoundries Inc., during the Semicon Europa exhibition held in Dresden. Such a picture is far more efficient than a long talk as it says everything: the PC wave of the 2000’s was based on expensive Silicon targeting maximum performance for about 300 million systems per year. The next big wave is concerning 1,500 million systems per year, relying on devices offering 75% cheapest costs per gate designed for performance efficiency, or maximum battery life time. Finally, the expected IoT wave will be built on completely different devices characterized by minimum possible size and a cost per sq mm divided by 5 compared with smartphone application processors… Such an evolution is more like a revolution.
To support such a revolution, GlobalFoundries strongly relies on FDSOI technology. The gate length in 22FDX is 14nm (but the CMOS transistor is still planar, cheaper to manufacture than 14nm FF transistor), allowing better performance and power efficiency than 28nm and finally lower power consumption, when the interconnects levels, having the same metal pitch than with 28nm, are at par in term of manufacturing cost. Technology is key, but not enough as you need to create an Ecosystem. Building a solid (ARM Ltd. calls it “vibrant”) Ecosystem is the key for success in the fabless industry, more than in any other industry. Before launching a SoC into production, the foundry will have to organize and support various industry partners, including EDA, IP, ASIC design services, Test, Packaging and probably more. Globalsolutions was created by GlobalFoundries to spur innovation in the semiconductor industry and assure chip designers receive world-class service from design conception to production. LETI is joining Globalsolutions as a technology (licensing) provider, as an IP provider and as an ASIC provider, specifically to support GLOBALFOUNDRIES’ 22FDX™ technology platform. “This strategic partnership with GLOBALFOUNDRIES positions Leti to help a broad range of designers utilize FD-SOI technology’s significant strengths in ultra-low-power and high performance in their IoT and mobile devices with 22nm technology,” said Marie Semeria, Leti CEO.
GlobalFoundries was not the first to license FDSOI technology from LETI. We can consider that they have filled the gap by offering the technology on a node offering better performance than 28nm. Licensing FD-SOI one year later than Samsung is also a great opportunity to benefit from existing EDA and IP ecosystem, already built to support 28nm FD-SOI. On the IP side, these have been developed several years ago and have been Silicon proven. IP vendors will have to port it to 22FDX, which is only a part of the development effort. EDA vendors have already supported numerous chip tape out in 28 FD-SOI, the tools are ready. Even more important, as one of the game changers is the Body Bias capability allowing increasing performance or reduce leakage current, this key feature is now well supported by design tools (it was probably not the case at FD-SOI technology introduction, leading to more complex design flow). From an interview made on the 10/15 with Gary Patton, ex-IBMer and now head of R&D and CTO at GlobalFoundries, we understand that FD-SOI is GlobalFoundries strategy to target smartphone AP and RF ASIC. Even if 22FDX is more suited for mid to low end AP, this market is huge, as well as RF ASIC. Did you know that IBM has put in production 16.5 billion RF-SOI IC since 2002? To further develop these markets, GlobalFoundries will have to rely on a strong Ecosystem and they are building it now. From Eric Esteve from IPNEST You can find Gary Patton interview
Samsung’s Luck with Gear S2
The wave of new and improved smartwatches started this year. Apple launched its first smartwatch in April. Several other players including Motorola, LG, ASUS, and Huawei have launched their new smartwatches this year. Sony launched its latest ‘SmartWatch 3’ in October last year. Rising consumer electronics brands like Xiaomi and traditional electronic brand Casio are also planning to launch their versions of smartwatches. And now prominent names from Swiss watch bazaar including Tag Heuer and Swatch would be launching their smartwatches with the so called “Swiss quotient” very soon.
Apple, with an “unofficially estimated” sale of Apple Watch between 3 to 5 million units so far, certainly brought a momentum in the smartwatch market and now commands a leadership position just next to Fitbit in the overall wearable segment. Apple’s arch rival Samsung unveiled its latest smartwatch, Gear S2 last month in IFA 2015. I assume Samsung by now has released more smartwatches than any other smartwatch company in the wearable segment. In 1999 Samsung had launched the first commercial smartwatch, which was actually a watch phone, SPH-WP10. This was followed by several models until now. Although there were improvements, the initial models of smartwatches were so bulky that they gave the impression of a phone hanging with your wrist. Lately with continued improvement in its smartwatch models Samsung had earned the leadership in smartwatch business with its Gearseries. Samsung had sold ~1.2 million units of Gear watches in 2014. However that leadership was short lived after the arrival of Apple Watch. Although Apple Watch sales figure is impressive, it definitely needs further improvements. Samsung in its Gear S2 has filled some of those gaps along with keeping the point-of-parity with the Apple Watch. Also it’s much different from Samsung’s own Gear watch. How the Gear S2 fares in the market remains to be seen, but an initial impression from its features says it has an edge over the Apple Watch.
With a round face and metal band it gives a traditional look. It’s a stand-alone watch performing phone functions without needing a smartphone to pair with it. It has an on-screen QWERTY keyboard for writing and sending text messages. There is 3G connectivity. You can make phone calls and send e-mails. The 1.2” circular screen has a display resolution of 360 x 360 and a pixel density of 302 pixels per inch. The other key features that come along with the Gear S2 are smart car keys, smart home control, mobile payment, and so on.
Like Apple Watch the Gear S2 also has several apps including weather information, heart-rate monitoring, sports tracking, stopwatch, time-zone and so on. The app icons are rounded and elegant; those go well with the round face. The apps can run natively on the watch without needing your smartphone, thus eliminating any lag due to communication with your phone. This is a downside in Apple Watch because apps there need to communicate with your iPhone.
The circular face is very easy to navigate. You can rotate the face to control the touch screen. The screen can be swapped to notifications or apps by simply and smoothly turning the bezel towards left or right instead of swiping on that small screen. The Gear S2 comes preloaded with 26 third-party watch faces, which include the ones made by CNN, Bloomberg, and so on.
The Gear S2 has Samsung’s Tizen OS customized for the watch. The device is made compatible to go with any other Android device with KitKat 4.4 or higher version of OS. It has a dual-core Exynos processor that runs at 1 GHz clock. It comes with 4GB memory and 512MB RAM. The device is equipped with a barometer, an accelerometer, a gyroscope, and sensors for ambient light, heart rate monitoring, and so on. A single charge on battery can go for 2-3 days.
The Gear S2 series has three models – Gear S2 Classic with traditional look, Gear S2 3G for techies, and the basic Gear S2. The models have been tested in various conditions; wet climate, dusty environment, submerged 1 meter deep in water for 30 minutes, and so on.
LG’s Urbane Luxe, Motorola’s 2[SUP]nd[/SUP] generation Moto 360, and Huawei Watch are other similar models, also unveiled during IFA 2015. Sometime later I will talk about them as well. While competition has risen beyond Apple Watch for Samsung, I must say the Gear S2 has good potential to bring back Samsung’s fortune in the smartwatch business. The smartwatch holds a major portion in the wearable market segment. According to IDC the wearable segment is expected to grow beyond 150 million units by the end of 2019, and out of that more than 80% will be wrist-wear.
ARM Server Chips: What Qualcomm Wants?
Qualcomm has made the long-awaited foray into the ARM-based server chipsets and the trade media is presenting its 24-core SoC prototype as a challenger to Intel’s hegemony in the cloud server market. Is it so?
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Extendible Processor Architectures for IoT Applications
The Internet of Things has become a ubiquitous term, to refer to a broad (and somewhat ill-defined) set of electronic products and potential applications – e.g., wearables, household appliances and controllers, medical applications, retail applications (signage, RFID), industrial automation, machine-to-machine communication, automotive control and communication, agricultural monitoring, etc.
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IoT chipsets and enterprise emulation tools
When most people talk about the IoT, it is usually all about wearables-this and low-power-that – because everyone is chasing the next huge consumer post-mobile device market. Mobile devices have provided the model. The smartphone is the on-ramp to the IoT for most consumers, with Bluetooth, Wi-Fi, and LTE, and maybe a dozen or so sensors in a personal cluster at a time.
That model represents just the edge. IoT applications, especially ones designed for the industrial IoT, have two more tiers. In the middle is the multi-protocol gateway, capable of handling streams of incoming data from tens, hundreds, or even thousands of sensors under a wide variety of protocols. These gateways usually smash everything into an IP-compatible blend, in real-time, for further analysis.
Behind both the smartphone and the multi-protocol gateway is some kind of infrastructure, the third IoT tier. Much of the “cloud” application infrastructure is designed for human interaction through a web services protocol, often using a RESTful programming model. A short delay, no more than a second or two, is an acceptable response for most applications.
IoT infrastructure is usually real-time, where a second to respond might as well be never, and unpredictable latency in an IoT network can be an incredibly bad thing. To handle real-time operations, many IoT architectures are moving to a hybrid cloud model, with a converged modular server running multiple cores to handle incoming data and analytics.
We have smaller chips somewhat improving for the edge, but the problem of optimizing bigger chips for the IoT gateway and infrastructure tiers looms very large.
Mentor Graphics dives in to the deeper end of the IoT pool with a brand new white paper discussing how large-scale Veloce emulation systems can help in design and verification of IoT chipsets. They come at the problem from an evolved mobile SoC or network processor (NPU) point of view, which is a valid point of reference. Their discussion of protocols centers on IP-level interconnect, not IoT frameworks such as AllJoyn, MQTT, Thread, and others – I’d like to see them extend their concept to that next level, perhaps with an IoT ecosystem partner.
Nonetheless, Mentor touches on some important issues in IoT chipset design and verification. I’d like to mention two more of their five main points – power consumption, and software.
As Apple is discovering with their A9 chip from its dual sources, system-level power management is becoming a very big deal. Mentor claims Veloce can run the billions of cycles needed to expose power issues, starting early in the design and continuing to full-up verification. Veloce also integrates with third-party tools such as ANSYS for even more advanced power analysis. Power management at remote gateways, or even on a per-core basis in a converged modular server or Spark node in the infrastructure, may prove particularly tricky.
Software for the IoT is another issue entirely. Most co-verification efforts focus on Linux or Android as the platform. IoT operating systems and software may be completely different, running compact RTOS platforms at the edge, OSGi on gateways, and an advanced language such as Lua or Rust on the infrastructure to support data management and analytics. Without getting to the real operating system or language in use for an IoT chip, issues may go entirely unnoticed. Veloce is virtualized, allowing applications to be run over Veloce OS which abstracts emulator and debug details from the application. Again, I’d like to see more IoT software specifics from Mentor in the Veloce environment, but their idea of virtualization is headed in the right direction.
The white paper concludes with a discussion of how Veloce is an emulation data center, rather than just a piece of engineering lab equipment. An Enterprise Server allows job management and scheduling over LSF, relieving a major weakness of earlier hardware emulator implementations. This allows multiple projects to be configured on a single Veloce emulator of sufficient capacity.
To download and discuss the Mentor paper, head here:
SoC Verification for the Internet of Things
I think it is great we are starting to explore these ideas. While the building blocks of the IoT are very similar to those used in mobile chipsets, there are going to be implementation nuances that need addressing in optimized IoT designs. Simulators will not get us where we need to go in terms of understanding behavior of multi-protocol gateway and infrastructure chipsets that must be highly reliable under any real-time traffic scenario. Hardware emulation makes a stronger case for IoT chipset verification, if we can see some actual software and protocols applied.
Is the IP market expected to decline by 2020?
To answer this question, I will share the results about Interface IP, more precisely the Top 5. The Top 5 protocols, USB, PCIe, Ethernet, DDRn and MIPI, are part of the interface IP market and each of them has been characterized by very strong growth rate. If you compute actual numbers for 2010 to 2014, it results to a Cumulated Annual Growth Rate (CAGR) of 14%.
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