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Price of Admission $0.00 at Inaugural Silicon Valley Conference

Price of Admission $0.00 at Inaugural Silicon Valley Conference
by Beth Martin on 10-20-2015 at 7:00 am

 Back in 2002, the Southwest DFT Conference was born and experts on design for test (DFT) and test got together to share ideas and talk to people in this industry that were trying to solve test challenges of the day.

On November 11[SUP]th[/SUP], the first annual Silicon Valley DFT and Test Conference is coming to Milpitas, California. This is the “sister” of the Southwest conference held in Austin, Texas. The saying goes, “there is no such thing as a free lunch”, but in this case, not only will you get a free meal, the whole conference will cost you nothing.

On the first day, you will hear from industry experts on hot topics like the impact of the Internet of Things (IoT) on test, the latest information on the IJTAG standard, and how automotive semiconductor designers are employing new testing techniques. At closing, a happy hour panel of experts will answer your burning test questions. If you are new to DFT and test, you are in luck, as on the following day, there will be a free tutorial covering all the basics, plus another free lunch.

In order to get a sneak peek at what will be a popular topic at the conference, I spoke to Steve Pateras, Product Marketing Director, Tessent Solutions, at Mentor Graphics. Steve said, “The explosion of technology in cars is impacting the semiconductor industry. An increasing number of devices are being developed for the automotive market and must therefore meet new quality and reliability requirements.” Steve will be presenting practical test solutions that help meet these requirements:

  • Zero defects per million (DPM) devices
  • In-field, self-test and diagnosis
  • Failure and yield excursion analysis

In order to approach zero DPM, Cell-Aware automatic test pattern generation (ATPG) is used to detect defects internal to standard cells. Electrical defects are mapped to cell-level transistor models and then SPICE simulation maps fault effects into a logical fault model. ATPG then targets the Cell-Aware faults.

In-field, self-test is addressed using logic built-in self-test (LBIST). A hybrid ATPG compression/LBIST approach allows sharing DFT resources for both manufacturing test and self-contained, on-chip tests for when the chip is in the actual car system.

Failure analysis employs both Layout-Aware and Cell-Aware diagnosis. Layout-Aware diagnosis provides valuable classification and localization of defect types. Cell-Aware diagnosis improves resolution to defect locations inside cells. This fast and accurate diagnosis is critical for analyzing the root cause behind field returns. Statistical analysis of large volumes of failing devices is used to quickly identify the root cause of yield excursions which are often early signs of reliability problems.

Steve concludes, “These new test techniques are already being adopted by many companies developing devices for the automotive market.”

If you are looking to learn about practical test solutions in a collegial setting, register today for the November 11[SUP]th[/SUP] conference at:http://www.svdft.com