webinar IPXACT banner
Semiconductor Expert Forum

Posted on

The Internet of Challenges Bumps Along

The Internet of Challenges Bumps Along
by Bernard Murphy on 11-18-2015 at 12:00 pm
Categories: Arm, IoT, IP

More from ARM TechCon. Great show as always, high-energy and a reminder that systems and solutions are where it’s at. There was a very big focus on Internet of Things in all its many guises, from devices to detect whether a garbage container is full, to a child’s necklace to store immunization and other health data, to new ways to push entertainment directly to whatever screen we happen to have in hand. But for those who think the IoT is an easy path to fame and fortune, there were reminders that this domain still has plenty of challenges ahead.

Let’s start with venture investment. That sexy new wearable you think will blow the VCs away? Forget it. According to Eric Klein, a partner and VC at Lemnos Labs, the Consumer IoT market is “very saturated”. That aligns with a couple of frequently overlooked points in consumer economics. First, we only have so much disposable income. Even if a carrier is nominally prepared to underwrite the cost of a device, they are digging deep into your wallet for that plan. If they find a way to bundle an additional device into the plan, they’ll dig even deeper. Second, we all hit gadget fatigue at some point, even the uber-geeks. Life (for most of us) offers too many other distractions. Eric’s take-away – focus your creative energy on enterprise and commercial applications. Businesses don’t care about sexy; they pay to reduce costs and increase revenues.

Next up, security. An expert panel (Paul Kocher – Cryptography Research, Eduardo Montañez – Freescale and Zack Colby – ARM) discussed where they really think we’re at. ARM has done a lot of good work to build a turnkey security solution at the device level – TrustZone® with CryptoCell as the basis for a trusted platform, secure communication over mbed TLS, secure code compartments through mbed OS uVisor and secure lifecycle management through mbed ID, Config and Update. And GlobalPlatform will certify complete Trusted Execution Environments. All of which are good steps to get to to a unified approach to security in the IoT.

But another observation was that this only works if the people at the end of the value chain turn it on. There is evidence that at least some of those folks find that step too difficult, or too costly, or just not very important – until of course there’s a breach, at which point it will be your fault. So we have to deal not only with bad actors but also careless actors – in buying, installing and maintaining. Changing these behaviors won’t be as easy as standardizing software and hardware.

Last and very far from least, a few observations from Colt McAnlis’ keynote. He’s a developer advocate at Google and a very entertaining speaker. His main point is simply stated and sobering – that if we’re not careful, all the entrepreneurs who are busy developing zillions of new solutions are going to screw up the IoT. One example is obvious (after he presented it). You walk through a shopping mall; each business has B2C (biz-to-consumer) “things” to ping your phone as you walk by, alerting you to their great sale on jeans. Two problems here: the annoyance of constant pings and your battery draining thanks to that WiFi/BT communication. Then you click on the message/app which takes you to a website with a rich graphic (or even video) experience, requiring an LTE session, which drains your battery even more. Now amplify that to add automated parking stations, automated hotel doors, automated checkouts… Pretty soon you’ll need a backpack battery to keep your phone charged. And then someone (Colt’s daughter in the keynote) will develop an app to block all that stuff and B2C IoT (two acronyms in a row, a personal best) will die a quick death. That’s what will happen if we don’t coordinate to avoid annoying consumers.

Colt had more good stuff on not defaulting to using internet “classic” technologies and data on the IoT. An example he gave was JSON. Great method on the standard internet to pass around structured packages of data. All text, human readable, easily debugged, what’s not to like? The answer is a massively bloated format burning unnecessary power to communicate and pack/unpack on a cell phone. There are more compact formats like FlatBuffers which are much more efficient. Another “classic” use-model example is widespread use of pictures. We’re graphics junkies now but they’re very expensive to download. That’s not a problem if you can pick and choose but see above. In our website development kits, we need a new target “format”, along with laptop, tablet and phone. We need an “only marginally annoying IoT format” which will skip downloading ads, cute Flash videos (and while we’re at it, will download just the one page you need, in minimal text, not the home page, or a page where you have to scroll forever to get to what you need).

Colt made us hold up our phones at the end and swear we were not going to screw up IoT. If we want it to thrive, we’d better listen.

More articles by Bernard…

Posted on

Intelligent Devices for Internet Of Things (IDIOT’s), Software Defined Networks and BotNets

Intelligent Devices for Internet Of Things (IDIOT’s), Software Defined Networks and BotNets
by Arun Majumdar on 11-18-2015 at 7:00 am
Categories: IoT

One conversation topic I hear these days is: the Internet of Things is coming and all the devices will be intelligent. It will be achieved by embedding some kind of AI technology or machine learning or reasoning or whatever into the devices themselves.
Continue reading “Intelligent Devices for Internet Of Things (IDIOT’s), Software Defined Networks and BotNets”

Posted on

Breaking the Limits of SoC Prototyping

Breaking the Limits of SoC Prototyping
by Pawan Fangaria on 11-17-2015 at 12:00 pm
Categories: EDA, FPGA, S2C EDA

Earlier this month during my conversation with Dr. Walden C. Rhines, he emphasised the need for our next generation designers to think at system level and design everything keeping the system’s view in mind. The verification will go through major transformation at the system level. I can see the FPGA prototyping systems already in place for large SoCs. The designers sitting at multiple sites can access a FPGA prototyping system remotely and prototype IP, subsystem or SoC utilizing one or more FPGAs without any issue.

It takes a lot more work than just increasing the capacity of FPGA for large SoCs; both combinational logic and sequential blocks need innovative methods to accommodate different types of logic structures, clock structures, modes of operations, test structures, I/O optimization, flexible interconnects, and so on while maintaining high performance. The configurability and flexibility of hardware extension determines the scalability of a FPGA system, but even more important is the software support to provide ease of design, verification, debug, and rework. The potential of a technology can only be realized after making it easy to design and operate.

Recently, S2Chad announced its single module UltraScale VU440 Prodigy Logic Module for FPGA-based prototyping. Today, it was a pleasure to see another press release from S2C extending its XilinxVirtex[SUP]®[/SUP] UltraScaleFPGA prototyping board family with Dual VU440 Prodigy[SUP]TM[/SUP] Logic Module. Now a larger design can be partitioned and fitted onto two VU 440 FPGAs without any need of cabling, thus improving the SoC reliability and performance.


S2C has a clear lead in terms of scalability and ease of prototyping large SoCs on FPGAs. The Dual VU440 LM is very compact (280mm x 250mm) on a single board and can handle up to 88 million gates. It can be used as a standalone board or inside the Cloud Cube offered by S2C. The Cloud Cube is an enterprise class prototyping system that can accommodate up to 16 such logic modules, thus scaling the SoC design to more than billion gates.


The two FPGAs are connected through 518 direct interconnects and 12 GTH transceivers. There are 1200 general purpose I/Os and 64 GTH transceivers on 12 high-speed connectors that are compatible with S2C’s Prodigy Daughter Cards. The system has 177.2Mb internal memory and DDR4 SO-DIMM and DDR3 SO-DIMM sockets that can support up to 16GB of high-speed memory. The clock management scheme can be set for standalone as well as cloud-cube mode. The Prodigy connector I/O voltages can be adjusted through runtime software in GUI with 4 status LEDs on-board to indicate I/O voltage. The system supports 30000+ design interconnections between two FPGAs with LVDS running at 1.2GHz.

The system is supported by state-of-the-art Prodigy Player Pro[SUP]TM[/SUP] Runtime software that can import the design, partition it and run P&R software. The runtime software sets up clock, reset, I/O voltages, self-test, and hardware monitoring. The monitoring of hardware including cable setups between connectors and daughter cards can be done from remote location. S2C also provides other software for design implementation, Multi-Debug system for multi-FPGA deep-trace debug, and ProtoBridge AXI software for interconnect.

The Prodigy ProtoBridge[SUP]TM[/SUP] AXI software links the system-level simulation environment to the FPGA-based prototyping platform, thus allowing managed traffic flow. The abstraction of interconnect also renders the IP blocks reusable.

The Dual VU440 LM is S2C’s 6[SUP]th[/SUP] generation SoC prototyping system that is quite sophisticated compared to previous generation FPGA systems and allows easy IP based prototyping for large SoCs. Multiple FPGA configuration options are possible through Ethernet port, USB port, JTAG, and micro SD card. Also there is on-board battery charging circuit that makes FPGA bin file encryption easy.

Read the press release HERE. The datasheet for Dual VU440 Prodigy[SUP]TM[/SUP] Logic Module is HERE.

Also read:
S2C ships UltraScale empowering SoFPGA
Taking a Leap Forward to Prototype Billion Gate Designs

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

Posted on

The EDAC Wally Rhines Roast (video)

The EDAC Wally Rhines Roast (video)
by Daniel Nenni on 11-17-2015 at 7:00 am
Categories: EDA, Siemens EDA

Last week was the EDAC Phil Kaufman award dinner. It was much more like a roast, probably because Wally has a great sense of humor and as Aart de Geus said, “Wally is a cool cat to have a beer with…” Aart is right of course, hanging with Wally is one of my favorite work things to do.

The place was lousy with media people so I will try and add some additional color here. But first check out the tribute video below featuring former Intel CEO Craig Barrett, TSMC CEO Morris Chang, NXP CEO Rick Clemmer, Sir Peter Bonfield, TI CEO Rich Templeton, Synopsys CEO Aart de Geus, Cadence CEO Lip-bu Tan, and even a clip from the Phil Donahue Show:

The video is fast moving (like Wally’s hairline) so it is definitely worth the ten minutes.

This whole thing started at the last Design Automation Conference in San Francisco. The Kauffman Award honors an individual who has had demonstrable impact on EDA. EDAC had a DAC booth with pictures of all the Kaufman Award winners and Wally’s picture was not there. I had just done a Fireside chat will Wally and asked him why?


He said he believed it was because he was viewed as a semiconductor guy versus an EDA guy. Considering Wally has been a member of the EDAC Board of Directors since 1994 and served as EDAC’s chairman from 1996 to 2012 I did not agree. I also noticed that there were no female award winners so maybe that will be addressed as well.

One of the more interesting topics of the evening was Wally’s contribution to blue light-emitting diodes which was later “perfected” and awarded The Nobel Prize in Physics in 2014. You can read more about that here:

EDA and the Nobel Prize in Physics!
by Daniel Nenni Published on 10-15-2014 05:00 AM
What does EDA and the Nobel Prize for Physics have in common? Our very own Dr. Walden Rhines (CEO of Mentor Graphics)…

It was quite an elegant affair with several hundred people, some of which are recognized EDA heroes. There were actually two videos shown but I doubt the second one will be posted. It was a spoof on Wally that fell flat. Craig Barett’s keynote was very good. Craig was a professor at Stanford and was on Wally’s PhD advisory panel so he had some interesting stories.

The most interesting comment Craig made was about Wally’s father, Dr. Fredrick Rhines, who authored “Phase Diagrams in Metallurgy Their Development and Application” circa 1956 and coined the term “microstructology” to describe the study of microstructures of metals and alloys. The apple did not fall far from the tree it seems. According to Wally’s Wiki page: During his career Dr. Rhines Senior was the Alcoa professor of light metals at the Carnegie Institute of Technology from 1946-1959 and founder of the department of materials science and engineering at the University of Florida, from which he retired in 1978; today the department is housed in Frederick N. Rhines Hall.

The other interesting information of the evening came from the guy sitting next to me, a long time EDA lawyer, who had some incredibly funny stories that he made me promise not to print. But let me tell you, between the two of us we know where most of the EDA bodies are buried, absolutely!

The video of the event will be posted HERE at some point in time.

Don’t forget to follow SemiWiki on LinkedIn HERE…Thank you for your support!

Posted on

Maybe Clockless Chip Design’s Time has Come

Maybe Clockless Chip Design’s Time has Come
by Tom Simon on 11-16-2015 at 4:00 pm
Categories: Cadence, EDA, Sonics

There have always been novel technologies vying to compete with conventional design practices. It is hit or miss on the success of these ideas. In the 90’s I recall speaking to someone who was convinced that they could effectively build computers based on multilevel logic. This, as we know did not pan out. But there have been many more ideas that have been partially or fully successful.

Years ago Intrinsity was formed by the former Motorola PPC design team to commercialize their dynamic logic based design approach. They could achieve impressive performance/mW numbers, but it was only suitable for full custom designs and was a challenge to work in their design specification language. They did some work with Microsoft on one of the early X-boxes. They had a tough time selling their solution to a more general market. However, they scored a major win when the design team was acquired by Apple. These are probably the same folks that are building your A9 chips.

One area of consistent effort is clocking schemes. One such effort that seems to have stalled out is resonant clocks. The start up Cyclos produced some chips with AMD, but making it commercially viable proved difficult for them. They boasted 4GHz clock speeds, but this is a clock speed achievable using conventional clock trees, so the benefit may not have justified the added effort.

Azuro is well known for shaking up the CTS market. Before they came along, the big guys probably had one or two part-time developers working on improving CTS. With their dramatic improvements in area and power, they signed some big deals with major chip companies and were eventually acquired by Cadence.

What a lot of people do not know is that their CEO Paul Cunningham originally wanted to develop a commercial solution for clockless design. However, after significant effort they abandoned that and focused on improving the existing CTS methodology. Clockless design still remains the holy grail of power-performance improvement. Of course it would also be a win in PVT in general as it would handle variation much better.

Wave Semiconductorhas developed an approach for implementing digital designs using a clockless approach called Wave Threshold Logic (WTL). To make it work they needed to change some fundamental ways circuits are designed, but claim to be able to make equivalent functionality, running much faster with a minimal area penalty.

They needed to use 2 wires per signal, to convey 0, 1, NOT_DATA, and an unused/illegal state. An increase in signal lines is not an excessive penalty for eliminating an entire clock tree and all its signal wires, buffer and and registers. But they also boast a power consumption win from the elimination of glitching transitions. The only transitions in their logic are true data transitions. When logic changes it is because of necessary switching. They also had to invent a new type of gate – one that switches based on the sum of the number of its input that are at logic 1.

Using this new gate and backward branching lines to coordinate logic readiness, they can implement the equivalent of any Boolean logic gate and pipelines of arbitrary depth. Arguably this approach still suffers from the problem Intrinsity had, which is the lack of a direct translation from RTL to their gates. However, Wave Semiconductor can easily reach data speeds of 8 to 12 GHZ. I am sure the lack of a gate level compiler had held back their business progression. Now It seems they have found a path that will provide them a bigger TAM.

Given how much bandwidth they have available, they appear to have decided to move up the abstraction chain and build a fabric of 8 bit processors and a way of converting high level design specifications into configurations of the fabric. Their website even talks about dynamic reconfiguration during chip operation. While this sounds similar to what an FPGA might offer, FPGA’s still have the limitations of a clocked architecture and cannot compete with ASIC’s and SOC’s on performance/area/power.

Wave’s fabric running at ~10GHz could implement a programmable approach that is fast enough to be the finished chip. In their current offering they have licensed NOC technology from SONICS, and are including a CPU and other IP blocks to round out the functionality. By going with a commercial product that could go to volume they have solved one of the big problems other novel clocking scheme designs have struggled with. If they can make the supporting software and the design specification process straightforward enough, they could be successful in an area where many others have struggled.

I think there might be an interesting back story on how their ‘brilliant’ idea was molded into something that can be marketed effectively to compete with the traditional solutions. After all, there have been a lot of clever ideas that did not quite pan out because there was not a good enough fit with the design needs of the market. One need not look any further than companies like Cyclos, Tabula or Intrinsity for good examples.

Posted on

More than just mobile phones for Mali

More than just mobile phones for Mali
by Don Dingee on 11-16-2015 at 12:00 pm
Categories: Arm, Events, IP

ARM TechCon 2015 was another tour de force for ARM and its ecosystem. Besides some of the developments in mobile, IoT, and security (more coming soon in the Epilogue of “Mobile Unleashed”), there were two topics that I found very educational and will cover in blogs this week. One was how the Mali family is powering more than just mobile phones. Continue reading “More than just mobile phones for Mali”

Posted on

A (R)evolution in Hardware-based Simulation Acceleration

A (R)evolution in Hardware-based Simulation Acceleration
by Tom Dillinger on 11-16-2015 at 9:45 am
Categories: Cadence, EDA, Prototyping

The most exciting products in our industry are those that are both evolutionary and revolutionary. Cadence has just announced an update to their hardware simulation acceleration platform – Palladium Z1 – which continues the evolution of the unique capabilities of processor-based acceleration, plus a revolutionary approach to managing this resource across an increasingly diverse set of users and verification environments.

I recently spoke with Frank Schirrmeister, Senior Group Director, Product Management, for the Cadence System and Verification Group, who shared his excitement about the capabilities of this new platform.

Simulation Hardware Acceleration as a General-Purpose Resource

Simulation acceleration platforms fall into two categories – processor-based and FPGA-based architectures.

Cadence offers both types of systems – Palladium and Protium – and has been developing flows to enable verification teams to move workloads between the two as seamlessly as possible, to leverage the best of both offerings. (For a discussion of Palladium and Protium migration, please refer to this earlier Semiwiki article: “What’s the Difference Between Emulation and Prototyping?”)

Typically, these platforms are reserved for large, system-level verification workloads, where the throughput of software simulation tools are inadequate for the task. Model compilation and job execution are usually managed by a smaller verification team, who are experts in the nuances of:

  • partitioning the model across platform domains (e.g., FPGA’s or acceleration hardware clusters)
  • managing multiple, concurrent project workloads running on the platform
  • integrating attached in-circuit hardware emulation interface modules
  • debugging methods specific to these platforms

The increasing complexity of SoC’s and the IP integrated into these chip designs requires that simulation acceleration no longer be primarily focused on system verification, often used in a narrow interval of time in the overall project development schedule. Rather, IP and SoC verification plans also need to incorporate the benefits of accelerated simulation, in various potential scenarios – more on “usage models” shortly.

Recognizing this need, Cadence approached the development of the Palladium Z1 platform to be more of a general-purpose resource, readily available and familiar to a broader cross-section of the verification team, across the full gamut of IP, Core, SoC, and system environments, as illustrated in the figure below.

First, some of the evolutionary improvements in the Palladium Z1 offering…

Palladium evolution
Leveraging technology scaling has enabled Palladium Z1 to improve specifications significantly over the previous Palladium XP-II platform:

  • up to 4X maximum model capacity
  • up to 2X performance in model build and resource allocation
  • up to 1.5X runtime execution throughput
  • 2X power density improvement (watts per million gates)

Extending multiple boxes to accommodate larger models has been enhanced to utilize optical fiber and Infiniband interfaces for the inter-system connectivity. (Existing Palladium-XP users will no doubt acknowledge that multi-system model domain management and cabling has been a pain.)

Cadence has continued to emphasize model portability between platforms, including the Cadence Incisive Enterprise Simulation software toolset. Utilizing a model compilation front-end that is aware of semantic differences between software simulation and acceleration (e.g., multi-state vs. two-state evaluation), verification environments and intermediate runtime results can be moved from IES to Palladium Z1 and back again, using a methodology that Cadence refers to as a “hotswap”.

Debug databases are readily off-loaded from the Palladium Z1, for off-line post-processing.

And, the ability to integrate in-circuit emulation with Palladium is supported. The Emulation Development Kits (EDK) are adapted to reflect the change in overall Palladium product strategy, to be discussed next.

Palladium “revolution”
As mentioned above, the need for accelerated simulation is reaching lower levels of IP, core, and SoC verification. To enable (and scale) for this growing requirement, Palladium Z1 has been re-designed to be a “data center” resource.

The unique product form factor of previous Palladium models has been replaced by a rack, with footprint, power, cooling, and cabling all consistent with data center “standards”.

Verification job queuing and dispatch on Palladium Z1 integrates readily with existing compute infrastructure (such as the LSF resource management tool).

The allocation of Palladium Z1 capacity to a verification task no longer requires an expert in the Palladium architecture to assign domains to each project. The job allocation to specific Palladium domain(s) is managed by the Cadence software. Indeed, the Z1 resources are dynamically allocated. Re-targeting of job resources is supported — i.e., re-location and re-shaping, without re-compilation — to enable a subsequent large dispatched job to have the (contiguous) resources necessary to execute with optimal performance. Frank indicated that the new platform supports up to 2304 concurrent jobs, with a 4M gate granularity.


As illustrated above, the EDK hardware emulation attach support has also been adapted to the data center strategy, with modules physically accessible to the Palladium Z1 in a rack located within 30 meters. These attached resources are available to verification users across the corporate data center network.

The strategy of expanding simulation acceleration to a much larger set of users and verification tasks also requires addressing the multitude of “usage models” that a verification team encompasses. The figure below highlights the specific areas of focus that Cadence has maintained for the Palladium Z1.


Throughout successive generations of microelectronics technology, the complexity of building block designs has grown, as has their functional verification requirements.

Yet, the transition from software simulation to an accelerated emulation or FPGA prototyping platform has typically required specific expertise, which has hindered the utilization of these platforms across the range of verification tasks. The data center focus of the new Palladium Z1 platform addresses this issue, and significantly reduces the “expertise gap”.

Verification project plans can now incorporate greater diversity in target tools and platforms for each level of design decomposition, to optimize throughput and testbench focus. The impact of adopting accelerated throughput across a wider set of models – especially, IP and subsystem designs – could indeed “revolutionize” how large design projects are verified.

More information on Palladium Z1 is available HERE.

-chipguy

Posted on

Strengthening That Serving ARM

Strengthening That Serving ARM
by Bernard Murphy on 11-15-2015 at 4:00 pm
Categories: Arm, IP

Everyone is aware of ARM’s dominance in mobile devices and their likely dominance in IoT, but what about servers? ARM has been making a play for this area but conventional wisdom is that fortress Intel will protect its server market at all costs. You’ll hear that servers are not so much about compute power, they’re more about I/O and no-one knows I/O with all its backward compatibility requirements better than Intel. Is that really the case and is ARM charging a hill it cannot take? Or are changing market needs shifting to favor new entrants?

There was a very revealing presentation at ARM Techcon this year from the Linaro group which goes to the heart (or at least an important heart) of this topic. Linaro is an open-source collaboration to drive compatibility for Linux kernel and other software for ARM-based platforms; they developed the Linaro Enterprise Group (LEG) in 2012 to focus on compatibility for server platforms. That in turn enables server SoC development from AMD (Seattle platform), Cavium (ThunderX platform), Applied Micro (X-Gene platform) and HiSilicon among others, aside from internal server development in Amazon (for AWS), Facebook and Google.

LEG is steadily moving ARM up the ranks in server support. The first step was enablement – the stuff you have to do to even play in the server/cloud space. This is UEFI (the modern replacement for BIOS), ACPICA for configuration and power management, KVM for kernel virtualization infrastructure, XEN for hypervisor and OpenJDK for Java support. LEG have been busy developing patches, having these approved and getting them upstreamed to releases.

They then expanded focus to workload optimization and this is where it gets really interesting. There are a lot of capabilities you need to ensure you run well on a Linux platform: LAMP, OpenStack, Docker, Ceph and more but one area really points to a strategic focus – establishing ARM as a best-in-class citizen and officially supported platform in big data, specifically around Hadoop. Hadoop itself is a complex ecosystem, including Spark, Pig, Hive, Calcite, HBASE and many other pieces. (For anyone who thinks software is easy compared to hardware, your head should be spinning by now.)

A central component of Hadoop is H[SUB]2[/SUB]O which provides an interactive interface to an underlying database view of the data. A lot of the statistical analysis and model-building starts here. LEG ran benchmarking to look at scaling on a cluster of 6 Seattle (AMD) 8-core nodes, using a 14 GB dataset (airport landing and departure times). They found that both file-parsing and model-building scales linearly with memory and that, surprise surprise, the speed of the external network is limiting for performance. For 1Gb Ethernet, performance flattens out after 2 nodes, but for 10Gb Ethernet it remains linear with the number of nodes (at least up through 8 nodes).

This has an obvious consequence for on-chip server node integrations: integrations are valuable only in so far as you can achieve ~10Gb Ethernet communication between nodes. And that’s for up to 8 nodes; it will flatten at some point beyond that, which will drive you to to even higher speeds. It is unlikely you can do any of this with traditional fabrics. The people who are building large node-count SoCs (the Calxeda team now in Amazon Web Services for example) almost certainly see their own proprietary fabrics as their primary technology advantage.

Given all this, does ARM have a shot? Big Data support is a new and potentially large market driving server growth (and therefore worth chasing), the playing field is leveled through need for innovation in fast, coherent on-chip fabrics (where traditional IO interface expertise doesn’t help) and the biggest customers don’t seem to have the patience to wait for a commercial solution and are building their own server chips and servers (which they pretty much have to do using ARM cores).

In short, as long as the ARM ecosystem can keep pace with big data needs, yes – they have a very real shot.

More articles by Bernard…

Posted on

ARM Announces Cortex-A35, mbed OS 3.0 at ARM TechCon 2015

ARM Announces Cortex-A35, mbed OS 3.0 at ARM TechCon 2015
by Majeed Ahmad on 11-15-2015 at 12:00 pm
Categories: Arm, IP

Mike Muller, Chief Technology Officer of ARM, has announced the availability of Cortex-A35 processor core for low- to mid-range smartphones at the opening keynote of ARM TechCon on November 10, 2015 in Santa Clara, California. According to Muller, there are going to be 2.8 billion smartphones shipped this year, and more than one billion of them are heading to developing economies mostly using the entry-level smartphones.

It’s the latest member of ARM’s ultra-high-efficiency 64-bit processors family based on the ARMv8-A architecture. Cortex-A35 chips are targeted at mobile and embedded applications, and production silicon from ARM partners is expected to be available in late 2016. MediaTek is one of the first chipmakers adopting the Cortex-A35 processor that consumes nearly 33 percent less power per core and takes 25 percent less silicon area compared to the Cortex-A53 processor core.

Next, Muller announced the availability of mbed OS 3.0 and mbed Device Connector for the Internet of Things (IoT) service provisioning and authentication. He also explained how ARM is bringing TrustZone security hardware infrastructure to low-cost microcontrollers. ARM’s TrustZone technology, which has been part of the Cortex-A processors, will now be part of the Cortex-M processors targeted at embedded and IoT applications.


Mike Muller: ‘ARM server chips have arrived’

Muller also talked about ARM-based server chips. He said that ARM has been talking about server chips for two to three years, and the firm has been making inroads in the server market during this time. “We are at the cusp of transformation while shipping server chips for a number of manufacturers.”

Muller told the audience that arm.com is now running on ARM-based server chips. When asked what ARM brings to table for server chips, Muller’s answer was cost and diversity. He said that it’s not going to be a single server chip; instead, there will be a variety of chips, for instance, for high-performance computing (HPC), C-RAN, networking and storage, etc.

ARM is celebrating the 25th anniversary of its founding at the ARM TechCon 2015.

Posted on

The Reason ARM Will Win IoT!

The Reason ARM Will Win IoT!
by Daniel Nenni on 11-15-2015 at 7:00 am
Categories: Arm, IP

After spending the week in Silicon Valley at ARM TechCon and related meetings, there was one common thread amongst the presentations and conversations and that was security. No matter what the topic was, mobile, consumer or industrial IoT, wearables, automotive, etc… security always came up. The question I had was how will companies approach security organizationally?

Take ARM for example, do they have one security group or security specialists in each product group? Do they approach security horizontally, vertically, or diagonally in regards to the different market segments? The answer of course is “all of the above” because security will be one of the most critical aspects of system level design and that starts with silicon, absolutely.

“We have the opportunity to get this right. Let’s take that opportunity to get the IoT right. As the IoT evolves, and as it gets more complex, it will be difficult to address security after the fact.” ARM CEO Simon Segars, ARM TechCon 2015 Keynote.

A funny side note, right in the middle of Simon’s keynote, alarms went off and we were all evacuated from the building. As it turns out, not so smart sensors detected an over toasted bagel during an IoT conference. Just a little bit of irony there… The sensors were probably connected to a PC but I digress…

The most impressive slide I saw at ARM TechCon, and I saw plenty, is the ARM partner slide above. Let me tell you something about collaboration, it is a language in itself. The fabless semiconductor ecosystem was born and raised collaborating so it is our native tongue, one that we have spoken for more than 25 years. TSMC is a great collaboration example of course and the result is the largest and most successful foundry ecosystem the world will ever see. TSMC and partners start at process development and continue through to the finished chips that hide inside the electronic devices we rely on every day.

ARM, on the other hand, has a different challenge. ARM and partners also start at process development but they continue through to the system level (both silicon and software) that enable the electronic devices we use every day. There are hundreds of silicon, design support, software, training, and consortia partners in the ARM ecosystem. This is literally 25 years of collaboration experience synthesized down to one slide and no one in this industry speaks collaboration better than ARM.

When I attend other conferences and hear companies that are new to the fabless semiconductor ecosystem talk about collaboration it really is hard to keep a straight face. It’s like me trying to speak my kid’s social language. I do not now nor will I ever really know what it is like to be a millennial but sometimes I pretend to, just to amuse my adult children. Try this one, tell your kids that you and their Mother are going to “Netflix and chill tonight” and see what happens.

Back to security, they say it takes a village to raise a child? Well, it will take an ENTIRE ecosystem of EXPERIENCED collaborators to make a SECURE mobile, consumer or industrial IoT, wearable, automotive, etc… device, ABSOLUTELY!

Don’t forget to follow SemiWiki on LinkedIn HERE…Thank you for your support!