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Top 10 Reasons to invest in Interactive Design Rule Checking tools

Top 10 Reasons to invest in Interactive Design Rule Checking tools
by Tom Dillinger on 10-01-2015 at 12:00 pm
Categories: EDA, Siemens EDA

One of the most energetic presentations at the recent TSMC OIP 2015 symposium was given by Tom Williams from Qualcomm, who shared his insights (and enthusiasm!) for Mentor’s Calibre RealTime interactive Design Rule Checking (iDRC) product.

Paraphrasing Tom’s presentation (and with a tip of the hat to David Letterman), here is a list of the Top 10 reasons to invest in iDRC verification, with a tool such as RealTime.

(10) Design rules have become incredibly complex – the days when the (majority of) rules could be memorized are long over. The rule descriptions are also very complex, necessitating visual feedback. Interactive DRC tools support the full DRC runset.

Tom W. highlighted that the Design Rule Manual (DRM) for TSMC 16FF+ devotes 80 pages to the MEOL layers alone. 🙁

(9) Using a connectivity-driven schematic model, layout “gen-from-source”, and parameterized layout cells (with abutment and merging support) does greatly assist layout designers. Yet, the rule complexity in #10 above suggests that correct-by-construction for cell/macro layout composition is extremely difficult to achieve – a fast verification method is still required.

(8) Multi-patterning verification requires color assignment to be exercised, and (complex) cyclic errors to be highlighted. These decomposition algorithms are far beyond traditional width/spacing/enclosure checks, and demand automation.

(7) The performance of iDRC tools provides fast turn-around time. It completely replaces the traditional interactive method – i.e., “pop up a ruler, measure, and compare to the DRM”.

There is a caveat, to be sure, on the size of the layout macro that is suitable for iDRC. Tom W. indicated that the Calibre RealTime guideline is to work with a layout cell with less than 3 million shapes.

(6) RealTime performance can be further enhanced by using the “Recipe Editor”, as shown in the figure. iDRC can be quickly configured to define a subset of rules and/or layers that will be presented to the checking engine.

Tom W. provided the example of “density checks” as a rule subset that would typically be excluded from RealTime verification during initial layout composition.

(5) The computational resource applied to iDRC – typically, a local workstation or a remote login server dedicated to interactive applications – alleviates the “server farm” from this resource demand. There’s no need to streamout, then submit, queue, dispatch, track, and write report files from batch DRC jobs, a workload which can otherwise be accommodated by interactive execution.

(4) iDRC tools are readily integrated into all layout platforms. As illustrated in the figure, toolbars and menus for iDRC are an integral part of the layout cockpit (as is the Calibre error report and viewing feedback). There is no need to exit from the interactive layout session, a big boost in productivity.

Tom W. is a big layout bindkey user — he has set up several bindkeys for common RealTime commands, as well.

(3) To be sure, iDRC does not replace batch verification. However, it is the most productive means to quickly verify the layout updates made to address batch run errors. The consistency of runsets used for both batch and interactive checking enables fast clean-up iterations using iDRC.

(2) Tom W. specifically highlighted that also iDRC enables a much quicker learning curve when starting layout design in a new process technology. The fast check, visualize, and fix loop helps the layout and circuit design team quickly explore initial cell/macro power rail and signal track template options.

The emphasis on a short learning ramp is consistent with a major theme of the 2015 TSMC OIP symposium. Early adoption and partnership with TSMC on advanced nodes is more important than ever, especially when making PPA design trade-offs.

and, finally, a very subjective advantage, but a critical one nonetheless:

(1)Every layout engineer wants to be as productive as possible. Schedule milestones are always tight, both during initial design feasibility assessment and the tapeout crunch. The morale (and stress) of the layout team is typically shared across the entire design team.

The enthusiasm that Tom W. displayed for iDRC with RealTime was infectious – you could tell the entire audience got a boost. Ensuring the design team can develop and maintain that high energy level throughout a project provides great benefits – this may seem somewhat intangible, but ultimately does affect the bottom line.

And, as an aside, if your team utilizes layout contractors for assistance with the (peak) workload, you want to be sure that word gets around this close-knit community that you’re making the investments to maximize layout productivity – you definitely want it to be known that you’re a great place to work!

If you haven’t looked at iDRC tools such as Calibre RealTime in a while, I would encourage you to do so – or, contact Tom W. and experience his ebullient recommendations directly. 🙂

-chipguy

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EDA By the Numbers, Phil Kaufman, Emerging Companies and More

EDA By the Numbers, Phil Kaufman, Emerging Companies and More
by Paul McLellan on 10-01-2015 at 7:00 am
Categories: EDA, Events, IP

The quarterly numbers are out from the EDAC Market Statistics Service (MSS) for Q2. The headline number is that revenue for the industry increased by 8.5% for Q2 to $1906.5M versus $1759.9M in Q2 last year. The four quarter moving average, that smooths out a lot of seasonality by comparing the most recent four quarters to the prior four quarters also increased by 8.5% (this is not an identity, the numbers are usually different). Just to emphasize, these are Q2 numbers and it is happenstance that this blog is going to occur on the first day of Q4.

The graph above shows growth by category, 2015 on the left and 2014 on the right. All categories grew except PCB.

Employment in the industry is up too. Companies that were tracked employed a record 32,806 professionals in Q2 2015, an increase of 4.9 percent compared to the 31,259 people employed in Q2 2014, and up 2.1 percent compared to Q1 2015.

Wally Rhines in his position as the EDAC board sponsor for MSS said…The EDA Industry continues to show solid revenue growth in the second quarter, with double digit growth in semiconductor IP and services. CAE and IC physical design also reported solid growth. Geographically, all regions except Japan saw revenue increases, especially Asia/Pacific.


Talking of Wally Rhines, he is also the recipient of this year’s Phil Kaufman award, which is jointly sponsored by EDAC and IEEE CEDA. I am assuming that you don’t need me to tell you that he is also the CEO of Mentor Graphics. The awards will be presented at the Phil Kaufman Award Dinner which will be held at the award presentation and dinner at 6:30 PM on November 12, 2015 at the 4th Street Summit in San Jose (address is 88 4th Street). You can register for the dinner here.

Coming up later this month is the next EDAC Emerging Companies meeting. It will be at 6-9pm on Thursday October 29th at the SEMI headquarters (also the EDAC headquarters) at 3081 Zanker Road, San Jose. This is the first of a new series on legal issues and is titled Patents and Patent Litigation: Develop, Strengthen, and Protect Your Intellectual Property. The event will be cicked off by the mayor of San Jose, Sam Liccardo, and the director of the new Silicon Valley United States Patent Office, John Cabeca. Hands up if you didn’t know that there was a Silicon Valley USPTO. It will be a West Coast regional office, serving California, Nevada, Oregon, Washington, Arizona, Alaska and Hawaii and opens on October 16th, in San Jose City Hall.


The panel session, on patents and patent litigation, will be moderated by Salumeh Loesch of Klarquist Sparkman, with panelists John Cabeca, who I just mentioned, Karna Nisewaner of Cadence, Robert Sahs of Fenwick & West and John Vandenburg, also of Klarquist Sparkman. The evening is free but space is limited and so you must register here.

I was going to reference a previous blog I wrote about patent valuations, but it is actually going out tomorrow morning. In a discussion I had with Amit Gupta and Jim Hogan last week, Jim told me:Patents are important, research shows $300-900K per patent in additional exit valuation over and above forward revenue multiple.

So that is another segue into the acquisitions that have been going on in the last few months, both in the EDA industry itself and also in the customer base.

Mentor acquired Tanner EDA and also Calypto (where they were already a majority shareholder). The biggest acquisition for sometime was Synopsys acquiring Atrenta the evening before DAC. Synopsys also enriched their IP portfolio with a number of acquisitions of Bluetooth and security technology. In a sort of cross-border acquisition involving an EDA company and a company normally perceived as a customer, Intel acquired Docea Power.

In the customer base, there have been acquisitions too. The change this year is not so much the number of acquisitions but the size of them. Intel acquired Altera (it hasn’t finally closed yet) for $16.7B.

Avago acquired LSI Logic for $6.6B last year, and broke it up, selling the flash business to Seagate, and the networking business to Intel. Then they acquired PLX Technology and Emulex. Finally, the big one: earlier this year, Avago acquired Broadcom for $37B (again, still not closed). After it closes the merged company will keep the Broadcom name. It will have annual revenue of around $15B.

The potential cloud on the horizon of all of this for EDA/IP is two fold. Firstly, in a merger the EDA budget for the merged company never goes up. Avago/Broadcom will have one of the largest IP portfolios (both IP in the patent sense and IP in the structures-on-silicon sense) which means it is likely to acquire less 3rd party interface IP from companies like Cadence and Synopsys. This probably won’t have an immediate affect, all the companies have EDA software and IP already, and designs in progress where they are not going to suddenly change the methodology, but as those contracts come up for renewal it is possible that the EDAC MSS will be reporting less rosy numbers next year and beyond.

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Xilinx Beats Altera to the First FinFET FPGA!

Xilinx Beats Altera to the First FinFET FPGA!
by Daniel Nenni on 09-30-2015 at 10:00 pm
Categories: FinFET, FPGA, Xilinx

Why do I stalk the FPGA industry? Well, FPGAs are an important part of the fabless semiconductor ecosystem for two reasons: 1.) They enable very cost effective design starts which are the life’s blood of the semiconductor industry and 2.) FPGA prototyping allows designers to verify their designs before committing to silicon and gives software developers a head start with working programmable silicon. And if that isn’t enough, the battle between industry leaders Altera and Xilinx is Kardashian-like reality TV. Or, if you are into sports, it would be a UFC Championship Match inside the Octagon. In this scenario Xilinx would be Women’s Bantam Weight Champion Ronda Rousey! Oh yaaaaa…

For me the FPGA fight really got interesting when Xilinx moved from UMC to TSMC at 28nm. I remember seeing an entire floor at UMC headquarters filled with Xilinx employees. Then disaster struck and Xilinx was late to the 40nm node. Next thing I know the 4[SUP]th[/SUP] floor was empty and Xilinx people were all up in TSMC’s business. Given the close relationship between Altera and TSMC it really was like adding a second wife to your marriage. The result of course was Altera divorcing TSMC and marrying Intel.

In the FPGA business being first to the new process nodes directly translates into increased market share. Xilinx lost market share to Altera at 40nm but reclaimed quite a bit by beating Altera to 28nm. At 20nm Xilinx beat Altera by more than a year so even more market share will move to Xilinx in the coming quarters.

And this just in:

Lift-off! 16nm Zynq UltraScale+ MPSoC ships to customers
From tapeout to “Hello World” in 2.5 months!


The full specs are HERE. There is even a YouTube video:

Of course Apple beat Xilinx to TSMC 16FF+ silicon by a few days but still that is very impressive, tape out to silicon in two and a half months. To be fair, Xilinx was already in production at TSMC 20nm which uses the same backend as TSMC 16FF+ so they did have an advantage over Altera who moved from TSMC 20nm across the street to Intel 14nm. I do know that Altera has taped out at Intel 14nm (with MUCH help from Intel) but I do not know when customers will start getting samples. Soon I hope because competition is what makes the fabless semiconductor ecosystem a force of nature, absolutely.

The other interesting news from Xilinx is from an email I just got this afternoon:

Subject: $99 FPGA kit for the curious engineer (that’s you)!
From: “Xilinx, Inc.”
Date: Wed, September 30, 2015 12:23 pm

Okay, I’m not a curious engineer, but even worse I’m a curious blogger, so yes I’m totally going to get one:

The $99 Arty Evaluation Kit enables a quick and easy jump start for embedded applications ranging from compute-intensive Linux based systems to light-weight microcontroller applications. Designed around the industry’s best low-end performance per-watt Artix®-7 35T FPGA from Xilinx. Arty kit features the Xilinx MicroBlaze™ Processor customizable for virtually any processor use case.

More information is HERE.

Also read: Xilinx Skips 10nm

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Automotive MCU code fault-busting with vHIL

Automotive MCU code fault-busting with vHIL
by Don Dingee on 09-30-2015 at 7:00 pm
Categories: Automotive, EDA, Synopsys

With electronic and software content in vehicles skyrocketing, and the expectations for flawless operation getting larger, the need for system-level verification continues to grow. Last month, we looked at a Synopsys methodology for virtual hardware in the loop, or vHIL Continue reading “Automotive MCU code fault-busting with vHIL”

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IoT need Low-cost, Low-power…and Silicon Proven IP

IoT need Low-cost, Low-power…and Silicon Proven IP
by Eric Esteve on 09-30-2015 at 4:00 pm
Categories: IP, Synopsys

Today, IoT devices are available in our daily life through wearable, smart appliances or metering application and some prediction call for 33 billion connected objects, 25 billion being IoT by 2020 (Gartner, 2014). Being very synthetic, IoT device (smart appliance or wearable object) will be wirelessly and securely connected to a “server” (smartphone, PC or else) itself connected to the cloud. By the way, we can expect most of the added value to come from cloud located services, but this scenario appears anyway to be an outstanding opportunity for the semi ecosystem. Building these 20+ billion devices will necessarily generate upside revenue. We think that these devices will have to be secured, extremely low-power… and low-cost. IoT has to be secured because hackers should absolutely not be allowed to meddle in the system. Low-cost to allow an adoption rate as fast as predicted and low-power as the user will not accept to change or charge the battery every day, or even every week (except maybe for wearable). In fact, the development of IoT systems could lead to revolutionary change in H/W and S/W design practice, similar to mobile phone explosion pushing to design incredibly more power efficient SoC in the 2000’s.

This sounds theory, but the recent launch by Synopsys of Silicon proven IP platform on TSMC 40ULP to support IoT designs is a real case. If you look at the IP market landscape, ARM is the undisputed #1, but only addresses CPU and GPU. By opposition, Synopsys ( #2) supports foundation IP (logic libraries, memory compilers), Non-Volatile Memory (NVM), Data Converters (ADC, DAC) IP, the long list of interface IP (USB, PCIe, DDRn, LPDDRn, SATA, HDMI, MIPI, Ethernet…) and wireless interface IP with BLE solution coming from Silicon Vision acquisition. Synopsys is leader on every IP segment, except CPU/GPU and NVM, and the company can support a complete SoC or ASIC design. Noblesse oblige, the IP vendor had to be the first to port these IP to ultra-low power processes (55nm and 40nm). In fact, more than a simple porting, Synopsys has re-architected and optimized most of these IP for smaller area, low voltage and lower power to propose energy efficient IP.

To support wireless connectivity, Synopsys has bet that Bluetooth Low Energy (BLE) will be the preferred protocol integrated in IoT systems. This sound like a wise choice to support systems developed today, as WiFi appears to be too power hungry and mesh network like ZigBee too advanced (but this may change as Bluetooth SIG plan to add mesh capability). This picture illustrate a Bluetooth (BLE supporting 4.0, 4.1 and 4.2) demo board on 55 nm.

Security is more than a concern for IoT… it’s a requirement! “As it’s increasingly important to secure devices against the growing number of data breaches and malicious attacks, IP providers need to stay ahead of the security standards,” said John Koeter, vice president of marketing for IP and Prototyping at Synopsys. Security must be addressed at different levels for IoT, from Firmware integrity assurance, secure bootstrap, ID and authorization and cryptography IP. Synopsys has just announced the industry’s first security IP solutions compliant to the Secure Hash Algorithm-3 (SHA-3) cryptographic standard to enable developers to protect the integrity of electronic information in applications such as message authentication and digital signatures, random number generation and key derivation functions.

Last but not least, you can expect IoT device to be equipped with sensors capturing data from the real world and you need controlling these sensors and processing data. SoC architect can rely on a complete set of power optimized IP, as above described, and on ARC based sensor & IP control subsystem, to support always-on processing required for sensor fusion and voice recognition applications. ARC EM4 is buss-less architected and hardware accelerators help again decreasing the global processing power consumption. Sensor processing at low cost (low area), optimized for low power is the last piece of the winning puzzle to address IoT application, with energy efficient set of IP, security IP (SHA-2, SHA-3) and modules and wireless connectivity (BLE 4.0, 4.1 and 4.2).

From Eric Esteve from IPNEST

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Can the Likes of iPhone 6s Bring New Disruptions?

Can the Likes of iPhone 6s Bring New Disruptions?
by Pawan Fangaria on 09-30-2015 at 12:00 pm
Categories: Mobile

In more than 30 years of semiconductors, we have seen many technology-induced disruptions in our ecosystem, be it healthcare, consumer, mobile, aerospace, or any other field for that matter. To name a few are portable healthcare devices at much lower prices, video conferencing over internet that reduced the need of physical travel, smartphones that have made many businesses much efficient, and so on. One thing is for sure, all these developments have happened because of newer and newer semiconductor technologies being infused in the equipment that are core to these applications.

Applehad a record breaking sale of more than 13 million iPhone 6s and 6s Plus in the first 3 days of their availability, not without reason. Of course Apple has a ‘built over the years’ fan club, but the key ingredient in iPhone 6s and 6s Plus is a bunch of new technologies including 3D Touch, camera with 4K video recording, unique storage solution, low power and high performance CPU and GPU powered by FinFET technology from TSMC 16nmand Samsung 14nm, and so on. I will talk more about these later in the context where such technologies vis-à-vis iPhone can disrupt some of the established markets; I’m already seeing one very good possibility.

A couple of months ago I was reviewing a comedy movie ‘Tangerine’ which was shot completely using an iPhone 5. It’s a nicely shot commercial movie with wide screen, saturated colors, intimately woven, level of details, etc. all at a meagre budget of slightly above a hundred thousand dollars. I just grabbed a scene from this cinematic movie to put it into context here.

Look at the clarity and quality of the picture, and the level of details captured! The writer and director of ‘Tangerine’, Sean Baker filmed this movie entirely using iPhone 5 in the vicinity of Hollywood at Los Angeles encompassing the magnificence of the city. The iPhone lens was fitted over with an adapter from Moondog Labsto achieve the kind of cinematic feel we see in this movie. The iPhone also had inexpensive app from Filmic Pro that helped in controlling focus, exposure, white balance, and so on. Well it’s not only for low-budget that iPhone was used but also for better quality, ease of setup and handling, familiarity with iPhone, and so on. Baker was frustrated with standard-definition videos normally used in low-budget films.

So, what’s the key here? Definitely camera quality and other technologies related to camera. But it’s more than that, the video recording, image processing, graphics, and not to mention performance and latency in capturing all activities. Imagine Baker wants to make an animated movie, or a movie with high graphic content and gaming. The GPU along with CPU is equally important.

This is where I see iPhone 6s and 6s Plus much advanced in supporting more of such filming in the movie making industry. It provides 4K video recording, the best-in-class high performance low latency storage solution, FinFET enabled GPU for high performance graphics processing and gaming at much lower power, and higher CPU performance to assist the high performance GPU in validating the right API calls for setting up the frames. Does that sound like these phones can be used in the main stream movie production? Let’s park this thought here and see some of the initial performance benchmarks AnandTech has performed on the iPhone 6s and 6s Plus.

The storage controller uses a hybrid SLC/TLC NAND solution where any write goes through a large SLC cache before being committed to TLC NAND. There are many other benchmarks including games, graphics processing, and battery life which can be seen at AnandTech website here. Clearly iPhone 6s and 6s Plus stand apart from the rest. It’s the power of FinFET, newer NAND, state-of-the-art storage controller and other semiconductor technologies that have enabled such developments; of course Apple has mastery in hardware as well as software.

Coming back to the kind of disruptions we can see in the film industry and elsewhere. I checked Moondog and Filmic are already organizing contests for movie making by using their inexpensive app and other technologies along with iPhones. Imagine these kinds of contests evolving into a commercial movie contest across the world, something like an “Oscar on iPhone” :). Definitely, other than USA, there are many regions on the Globe which needs awareness about such low-budget good-quality move making option. More awareness can bring disruption in movie making industry bringing up hidden talent in acting. The talent will not have to wait to enter Hollywood or Bollywood to show it on the screen. Moreover, Bollywood movies in India can be targeted to be developed on low-budget using iPhones, absolutely. Use the money needed elsewhere!

Are there any other thoughts on disruptions which can be brought up by such cutting-edge semiconductor technologies? Expert Drones?

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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Samsung Device Solutions Has a New Home

Samsung Device Solutions Has a New Home
by Paul McLellan on 09-30-2015 at 7:00 am
Categories: Foundries, Samsung Foundry

Last week it was the formal opening of Samsung’s new office building in North San Jose. They have brought together all of semiconductor device solutions in a huge new office building. The building can hold 2000 people. Samsung Device Solutions consists of:

  • memory
  • system LSI
  • LED
  • display

Dr OH Kwan, the CEO of Samsung Electronics, gave some of the history. Samsung first came to Silicon Valley in 1983 over 30 years ago. Just to put the technology of that era into perspective, the state-of-the-art was an IBM PC-XT with 128K of DRAM (yes, kilobytes) and a 10MB disk drive. I believe it was the first personal computer that came with a hard disk, not just floppy drives. The cost was $5,000, about 10 times the cost of one of the Samsung Galaxies that seemed to be everywhere, and nowhere near the power or capacity.

The new building is ten stories high with 1.1 million square feet. It is shaped with a large atrium open to the sky and even a couple of the levels are designed to allow employees to be outside. There is even a putting green. Somehow Samsung had arranged for perfect weather. The building is mirrored and the bright blue sky and the white clouds made for a photogenic scene.

The building was constructed in just two years. There was Mike Rossi a special adviser to Governor Jerry Brown, and not just the current mayor of San Jose, Sam Ricardo, but the previous mayor, Chuck Reed, on whose watch the building was started. I was pleased that the politicians resisted the temptation to talk at excessive length. Finally, there was a performance by the dance/music group Eclipse.

Following that, the Samsung employees went off to the cafeteria, which is in a separate building, and the press was divided into groups and given a tour of the building. Our tour guide was Kelvin Low, who runs foundry marketing. He moved into the building a couple of weeks ago and can just about find his way around the building now. His office is on the top (10th) floor and since it is the highest building anywhere near the views are dramatic in all directions.

We got a quick tour of some of the engineering areas. The previous week at the flash memory summit Samsung had just announced a 16TB solid-state disk drive, the world’s largest. The progress since Samsung arrived here when 10MB was the state of the art is amazing, an increase in capacity of over a million times and probably around the same price. Isn’t Moore’s Law wonderful, I’m not quite sure how the world is going to look now that it is slowing down or stopping, and we won’t ever get a million-fold increase for the same price.

One of the advantages of having a single large office building is that accidental meetings are much more likely to happen than when spread around a multi-building campus. The interior of the building has also been designed to make such fortuitous meetings still more likely, with various open areas, coffee rooms, a gym, the two levels open to the outside and so on.

In other Samsung news, that took a bit of the shine of the new building, there were reports that Samsung were cutting capex by 20% due to overcapacity. This is not entirely unexpected since Samsung is the biggest DRAM supplier which is often a sort of canary in the coalmine, signaling weakness early.

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Semiconductor Inventories Under Control

Semiconductor Inventories Under Control
by Bill Jewell on 09-29-2015 at 7:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

The semiconductor market is currently in a slow growth period. After 10% growth in 2014, the market is expected to only show low single-digit growth in 2015. Our own forecast at Semiconductor Intelligence is 1.5%. In several previous market slowdowns, inventories in the channel have climbed as some companies were slow to adjust their inventories to match lower demand levels.

The chart below shows total inventory as a percentage of quarterly revenue for five of the top six semiconductor companies. Samsung is not included since it does not disclose inventory data for its semiconductor business. Most of the companies show no significant change in the inventory ratio over the last six quarters. The exceptions are Intel and Qualcomm. Intel’s ratio went from 29% in 2Q 2014 to 37% in 2Q 2015. This is primarily due to lower revenues, with Intel’s 2Q 2015 revenue down 5% from a year ago. Qualcomm’s ratio climbed from 24% in 2Q 2014 to 41% in 2Q 2015. Qualcomm’s 2Q 2015 IC revenue was down 22% from a year ago due to increased competition for its smartphone chipsets.


Are inventories at electronics companies getting out of alignment with revenues? The chart below illustrates total inventories as a percentage of quarterly revenues for key electronics companies. The companies are six of the top eight purchasers of semiconductors, according to Gartner. The other two are Dell, which is now private, and Huawei, which does not disclose inventory data. The inventory to revenue ratio varies significantly from company to company, with Apple averaging about 4% and Sony ranging from 30% to 50%. These differences are due to factors such as number of product lines (relatively few for Apple, numerous for Sony) and supply chain strategy. Some companies (such as Sony, Samsung and Lenovo) tend to build inventory in the third quarter in anticipation of stronger fourth quarter sales. None of the companies show any significant change in their inventory ratio for 2Q 2015 compared to a year ago.

The links in the semiconductor supply chain which usually show the largest variation in inventories are distributors and electronic manufacturing services (EMS). The chart below displays the ratio of total inventories to quarterly revenues over the last fifteen years for major distributors and EMS companies. The two largest semiconductor distributors, Avnet and Arrow Electronics, are used for the distributor ratio. Each company has over $20 billion in annual revenues. The EMS companies are Jabil, Sanmina, Flextronics and Celestica. Hon Hai (Foxconn) is the largest EMS company, but it does not disclose inventory data for its EMS business.


When the Internet bubble burst in 2001 the semiconductor market plunged 32%, following strong 37% growth in 2000. Distributors’ inventory ratio peaked at over 80% from the low 60% range in 1999. The distributors did not reduce their inventories quickly enough to match the decline in revenues. Since 2001, the distributors have done a better job of managing inventories. For the last eight years their inventory ratio has held at close to 40%.

The EMS companies were caught by surprise by the semiconductor downturn. Most of these companies did not become significant factors in electronics manufacturing until the 1990s and did not experience the previous double-digit semiconductor market downturn in 1985. Their combined inventory ratio ballooned to over 70% from below 50% in 1999. Flextronics, the largest EMS company at the time, saw its ratio double from 44% in 2Q 1999 to 87% in 1Q 2001. The EMS companies reduced the ratio to 39% in 4Q 2004. As the semiconductor market slowed from 28% growth in 2004 to single digit growth in 2005 to 2007, the ratio jumped to 55% in 1Q 2007. Since 2007 the ratio has been fairly steady, even through the 2008-2009 semiconductor downturn. In the last few years the ratio has risen slightly from about 50% in 2011 to 57% in 2Q 2015. This latest increase in the ratio is likely due to deliberate plans to run higher levels of inventory following conservative inventory levels in 2010 and 2011.

Semiconductor inventories appear to be under control throughout the semiconductor device supply chain. Thus companies are making adjustments for the slowdown in the semiconductor market. Companies walk a fine line between carrying too much inventory – which can become a major burden when demand falls off – and too little inventory – which can lead to missed sales when the market is growing. The improved inventory management is largely due to better inventory management systems and better communications between semiconductor suppliers and the buyers of their products: electronics companies, EMS companies and distributors.

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Indian Railways and SoCs

Indian Railways and SoCs
by Sivakumar P R on 09-29-2015 at 4:00 pm
Categories: EDA

Last week I woke up late as usual and decided to flip through the news paper on Coffee to enjoy the lazy Sunday morning, but I ended up reading a sad news about a train accident. Everyday virtually we hear about minimum one accident. Indian Railways, wow, what a reliable transportation system we have built. It clearly indicates we have to learn how to plan meticulously before jumping into execution.

I was not really surprised when Harry Foster at DVCon mentioned “Average number of Chip respins in India is more than any other countries, though we are the best in adopting latest verification methodologies”. In my imagination, Indian railways which has been built over the legacy British railways system reflects the structure and complexity of an SoC which is built using legacy chips and IPs. Although our SoCs don’t crash like our Indian railways, still we need to improve our project planning and execution to achieve First-Time-Pass.

‘First Time Silicon Pass’ pretty much depends on how you plan the whole project execution, especially the RTL verification. So as a verification consultant I would like to explain the project planning from a verification perspective.

Team – Are they skilled enough to do their job?
Build the team with right resources and train them on the technologies and methodologies which are relevant to the project. Also implement a process to identify their readiness with respect to spec understanding and skills. Everyone doesn’t need to know everything. Experienced engineers will implement TB infrastructure and mid level engineers will write only Testcases and coverage models and junior engineers will monitor and automate the regression. For example mid level and junior engineers must be skilled enough to use EDA tools to debug the simulation failures.

Project manager/TB Architect – Have they understood the methodology properly and perfected their approach?
In my consultancy experience what I have identified is that most of the project managers are traditional verification folks who have limited understanding of latest methodologies like constrained random verification. So they end up mixing traditional approaches with latest methodologies. I have seen them using UVM/OVM with traditional test plans. There is a huge difference between test plan and Vplan. In UVM/OVM, we do not think about test cases while creating the Vplan. Similarly sometimes experienced verification engineers who are new to SystemVerilog end up writing lot of directed test cases by narrowing the constraint range to specific conditions.

TB Architect – Has he considered his customer?
Architect the test bench infrastructure in such a way that it can be reusable with any technology at any level [IP/Chip/SoC verification on Simulation/Formal/Emulation]. Also your VIP should be able to accommodate the spec and design changes at any time in the future. Always try to simplify the user interface, aiming towards making your VIP as a push button type [ON & OFF] verification component. Write necessary scripts to automate the regression and report generation.

Finally I would say, ‘Make it simple’. That’s what your customer wants. He does not want to go through thousand pages of your user manual just to understand how to use your VIP. Most importantly, he doesn’t want to miss the tape out debugging and fixing your VIP functional bugs. So you need to be creative enough to invent a methodology/flow too to verify your VIP, as a competent Project Manager.

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EUV – So late to the party it may already be over!

EUV – So late to the party it may already be over!
by Robert Maire on 09-29-2015 at 12:00 pm
Categories: Foundries, Lithography

Stocks in the semiconductor equipment space continue to fall only this time along with the broad market. We had recently pointed out that LRCX was the last to fall among the large cap companies in the space but now the question becomes when have they fallen enough to say its over, and which stocks have more to fall……

ASML stock always at a premium…
We have always had an issue with the apparent premium that the stock of ASML trades at. Although it clearly deserves a premium due to its margins and market dominance the premium it commands versus its US peers was well beyond just those factors. It seem obvious that there is clearly a “scarcity” premium of European investors looking for large cap technology companies that keep ASML at a much higher than industry average due to a lot of money chasing too few stocks with few alternatives. As alternative European technology companies such as Nokia and Ericsson have fallen so has ASML gained. We see a similar issue propelling some Asian technology companies to well above US equivalent valuations, such as Hermes. (US semi equipment company management has always had a bit of P/E envy over this valuation differential….)

How Much of a Premium?Not worth a Double…
ASML seems to command more than double the valuation of similarly situated US companies such as AMAT, LRCX & KLAC. ASML trades at a forward P/E of about 18 versus 9 for LRCX, 10.5 for AMAT and 11.7 for KLAC. On a price to trailing twelve months sales ASML trades at 5.3 versus 1.9 for LRCX, 1.8 for AMAT and 2.7 for KLAC. Obviously all these ratios will change as earnings are likely to drop for everyone in the industry along with a slowing of revenue as the downturn takes hold.

ASML has the potential to fall further than US counterparts…
Even if we presume a deserved quality premium versus US counterparts and a European stock premium there is still likely excess air in the valuation of ASML shares that could come out if we continue to see a capitulation of the sector and compression of valuations. At this point one could argue that European stocks deserve a discount rather than a premium.

A Pair trade with the US?
If I were a US shareholder the obvious question is why should I continue to hold ASML at such lofty valuations when I can buy similar US companies at half the price. I could further argue that a pair trade short ASML and long a US counterpart might not be such a bad way to hedge the market in the near term volatility given the valuation differential.

ASML fundamentals no better than anyone else… maybe worse?
There hasn’t been a whole lot of news in a relatively long time about the progress of EUV. The last thing we heard was an alleged 15 unit order over the span of several years purported to be from Intel. But that was before Intel stretched out its technology cadence from 2 years to 3 years and has continued to lower its capex, so the true value of that order is likely a lot less than the initial investor reaction.

Nor have we heard about anyone about to put EUV into production or production throughput getting to high volume manufacturing levels. In fact we continue to hear a “buzz” in the industry that other chipmakers, in addition to Intel, have process flows for 7nm that work just fine without EUV barring some major breakthrough we could very well see 7nm start out without EUV (or very much of it). ASML’s expectation that they will get some process steps or get in on the end of 10nm is starting to feel shaky.

The near term memory spending concerns at chip makers such as Samsung certainly impact ASML at least as much as its US counterparts. These concerns continue to echo in the stocks. ASML has significant exposure here in its current scanner offerings.

Memory may never go EUV…
Given that current memory technology line widths are well behind logic and foundry we would be hard pressed to find a memory maker that has EUV anywhere in its plans in the near term let alone long term plans. Given the spending patterns this suggests that EUV is shut out of at least half the market spenders.

So where is the EUV upside?

EUV is a very, very daunting task and we admire that ASML has continued to stick with it but you have to wonder. EUV has been in the works for such a long time, it goes all the way back to Bell Labs (remember them??) The question is will there be a payback??

Back in 2001 when the industry was running .25 micron (250nm for you newbies…) and Intel just announced .13 micron plans it was thought that EUV would start at about .07 micron (70nm) and perhaps EUV could be pushed as far as .03 micron (30nm) and if we were really lucky perhaps even stretched to .007 micron (7nm).

Fast forward almost 15 years and here we are wondering if EUV will even get introduced for the 7nm node….
The reality is there likely aren’t all that many nodes left in the semiconductor technology path after 7nm to try to recover the huge expense of developing EUV before we likely move on to some new non traditional technology to try continue Moore’s Law which may or may not require the same litho tools.
In the end , EUV could still be a losing bet even after the industry has doubled down several times…..

The figure above is a copy of the original Wall Street Journal article from 2001 about the advent of EUV. We found this ancient yellowed copy in our archives. (Yes, I am a pack rat who has files going back to our involvement in the IPO of ASML 20 years ago in 1995). Here is a link to a more legible copy of the article: Wall Street Journal 2001 EUV article

We dug the article up when we read this past weekends article in the Sunday NY Times about Moore’s Law slowing which also talked about lithography issues:Sunday 9/27 NY Times article about lithography & Moore’s Law slowing

Robert Maire
Semiconductor Advisors LLC