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Secured SAM A5D4 MCU for Industrial, Fitness or IoT Display

Secured SAM A5D4 MCU for Industrial, Fitness or IoT Display
by Eric Esteve on 10-06-2015 at 12:00 pm
Categories: Arm, Foundries, IP

The new SAMA5D4, ARM Cortex-A5-based, expands the SAMA5 microprocessors family, adding a 720p resolution hardware video decoder to target Human Machine Interface (HMI), control panel and IoT applications when high performance display capability are required. Cortex-A5 offers raw performance of 945 DMIPS (@ 600 MHz) completed by ARM NEON 128-bit SIMD (single instruction, multiple data) DSP architecture extension. To target applications like home automation, surveillance camera, control panels for security or industrial and residential gateways, high DMIPS computing is not enough. To make the difference, on top of dedicated video decoder (H264, VP8, MPEG4) in hardware, you need the most complete set of security features.

Whether for home automation purpose or for industrial HMI, you want your system to be safeguarded from hackers and also your investment to be protected against counterfeiting. You have the option to select 16-b DDR2 interface, or 32-b if you need better performance, but security is not anymore an option. Designing with Atmel SAMA5D4 will guarantee secure boot, include ARM Trust Zone, encrypted DDR bus, tamper detection pins and secure data storage. The SAMA5D4 also integrates hardware encryption engines supporting such as AES (Advanced Encryption Standard)/3DES (Triple Data Encryption Standard), RSA (Rivest-Shamir-Adleman), ECC (Elliptic Curves Cryptography), as well as SHA (Secure Hash Algorithm) and TRNG (True Random Number Generator).

If you design fitness equipment, such as treadmills and exercise machines, you may be more sensitive to connectivity and user interface functions than to security features, even if it’s important to feel safe in respect with counterfeiting. Connectivity includes Gigabit and 10/100 Ethernet and up to two High-Speed USB ports (configurable as two hosts or one host and one device port) and one High Speed Inter-Chip Interface (HSIC) port, several SDIO/SD/MMC, dual CAN, Etc. Because the SAMA5D4 is intended to support industrial, consumer or IoT application requiring efficient display capabilities, it integrates LCD controllers with graphics accelerator, resistive touchscreen controller, camera interface and the above mentioned 720p 30 fps video decoder.

The MCU market is very competitive, most of the products are developed around the same ARM based family of cores (from Cortex-M series to Cortex-A5), so the key importance of differentiation. Performance is an important differentiation factor, and the SAM A5D4 is the highest performing MPUs in the Atmel ARM Cortex-A5 based MPU family, offering up to 945 DMIPS (@ 600 MHz) completed by DSP extension ARM NEON 128-bit SIMD (single instruction, multiple data). Using safety and security on top of performance to augment differentiation is certainly an efficient architecture choice. As you can see in the block diagram below, the part features the ARM TrustZone system-wide approach to security, completed by advanced security features to protect the application software from counterfeiting, like encrypted DDR bus, tamper detection pins and secure data storage. But that’s not enough and the MCU also integrates hardware encryption engines supporting such as AES/3DES, RSA, ECC, as well as SHA and TRNG.

The SAMA5 series target industrial or fitness applications where safety is also a differentiating factor. If security helps protecting the software asset and makes the system robust against hacking, safety directly protects the user. The user can be the woman on the treadmills above pictured, or it can be the various machines connected to the display that SAMA5 MCU pilots. The SAMA5 series includes functions that ease the implementation of safety standards such as IEC61508. These include a main crystal oscillator clock with failure detector, POR (power-on reset), independent watchdog timers, write protection register, etc.

Cortex A5 Atmel’s SMART SAM A5D4 is a medium-heavier processor and well suited for IoT, Control Panels, HMI, and the like, differentiating from other Atmel’s MCU by the means of performance and security (and safety). The ARM Cortex-A5 based MCU delivers up to 945 DMIPS when running at 600 MHz, completed by DSP architecture extension ARM NEON 128-bit SIMD. The most important factor differentiating SAM A5D4 is probably the many security features implemented, from ARM TrustZone to encrypted DDR bus, tamper detection pins, secure data storage and various hardware encryption engines (AES/3DES, RSA, ECC, SHA and TRNG). These security features protects OEM software investment from counterfeiting, user privacy against hacking and safety features make the SAM A5D4 ideal for industrial, fitness or IoT applications.

From Eric Esteve from IPNEST

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Nine Cost Considerations to Keep IP Relevant –Part2

Nine Cost Considerations to Keep IP Relevant –Part2
by Pawan Fangaria on 10-06-2015 at 7:00 am
Categories: EDA, IP, Semiconductor Services

In the first part of this article I wrote about four types of costs which must be considered when an IP goes through design differentiation, customization, characterization, and selection and evaluation for acquisition. In this part of the article, I will discuss about the other five types of costs which must be considered to enhance the value of IP and keep the IP-based SoC business model growing. In general these costs are known by their simple terminology; however they need to be better understood in the modern context of IP so that the right level of investment in the IP can be justified from both sides – the IP provider and the SoC integrator. Let’s analyze these in their right perspective here.

Cost of Qualification – The quality of IP, specifically design IP is a big question mark today. As you obtain the third-party IP blocks from different regions (which may have different quality culture) of the world, it’s imperative that they must be qualified in the premises of the SoC integrator before they can enter into the works. A preliminary assessment and evaluation of an IP must have been done as part of acquisition, but its actual qualification from quality and security perspective according to its intended use in the actual SoC environment must be done in-house by the SoC vendor. For example, an IP for automotive applications must be tested in the SoC environment under the intended temperature ranges and possible electromigration effects. This is essential to ensure the IP is bug-free to avoid resolving the IP bugs at the system-level which can be very unworthy and extremely costly. It’s not a complete verification of the IP or system; I will talk about verification in detail in a subsequent section. It’s a quick qualification of the IP in focus. Fractal Technologieshas a tool called Crossfire which has an option to quickly qualify your IP with all formats and the SoC environment in which the IP is intended to be used. Similarly there is IP Kit from Atrenta (now Synopsys) available at TSMCfor partners to qualify their soft IP against Atrenta’s SpyGlass provided checks. There may be other commercial or internal tools as well to assist in this acute need of qualifying the IP before its use.

Cost of Integration – Although the cost of integration of an IP into an SoC falls into the purview of the SoC vendor, the onus of integration may come on the IP provider who needs to make sure the IP or subsystem along with the software bring-up works properly in the SoC environment. The matter of the fact is that the SoC integrator does not understand all of the IP that are going to be integrated into the SoC; so the SoC vendor has to hire domain experts in different areas. The IP provider in most cases has to work at the subsystem level when integrating an IP into an SoC.

For an IP provider it’s like envisioning the system requirements and making provisions for those while working at the IP level. For example, in case of an interface IP the whole channel has to be modeled as per the system requirements; for a physical IP, the PPA has to be modeled with right level of trade-off according to the system requirements. The PHY has to be programmed to make a trade-off between PPA. In modern age, the range of PPA can be very wide in which case the IP has to be segmented into high-range for performance critical applications, mid-range to save power, and low-range to save cost. Again, for an IP with FinFET and smaller geometries, you may need to increase the area to spread the heat. Also the FinFET process varies between foundries, so if you are sourcing an IP from two different foundries, then you will also have to spend in unifying those characteristics to keep the final SoCs uniform. As an example Applesourced A9 SoCs for its iPhones 6s and 6s Plus from TSMC 16nm as well as Samsung 14nm foundries. So, at the system level their characteristics have to be matched to keep the power and performance uniform for all phones.

Another level of complexity comes when you integrate analog with digital on the chip. The analog portion needs confirmation from the foundry, so it’s advisable to keep the analog content as less as possible. However moving things from analog to digital can be another complexity and will surely incur cost.

Considering an IP from system perspective, it’s important that the package aspects are taken into account. This includes effects such as noise, signal integrity, ESD, and so on.

More and more of system companies prefer team integration with the IP vendors where the IP team can work with the system team and contribute in SoC roadmap development for future innovative technologies. This is a smart move for giving a lead time to future technologies, provided confidentiality is maintained. These days we are also seeing full merger of IP companies into SoC companies. A flip side to these mergers is that a sustained continuation of such mergers may defeat the purpose of IP-based business model in the longer run.

While integrating an IP into an SoC and optimizing it within the cost parameters for a particular target segment, the integration has to go through several trials to obtain the best optimized architecture. To save the cost of these trials, the IP and SoC industry is gearing towards automating this effort.


ARMhas already developed tools for such automation. In the picture above there is ARM[SUP]®[/SUP] Socrates[SUP]TM[/SUP]design environment along with CoreLink[SUP]TM[/SUP] Creatorfor interconnect optimization and CoreSight[SUP]TM[/SUP] Creatorfor debugging. Read the article, “New Tool Suite to Accelerate SoC Integration” for more details on the “ARM IP Tooling Suite”.

Cost of Verification – This is the most significant cost in an SoC, almost 2/3[SUP]rd[/SUP] of the total cost of the SoC. There are multiple verification engines for simulation, emulation, formal verification, virtual prototyping, FPGA prototyping, and post-silicon verification at different stages of an SoC design. The key idea is verification closure through complete coverage of the overall SoC. It’s in general very difficult and hard problem to get complete coverage of an SoC. These days the SoC vendors bring up the whole system and run applications on full chip through emulation, or validate the SoC through FPGA prototyping which has its own limitations. There is no way to guarantee complete verification other than the verification coverage metrics, so coverage driven verification gained importance where coverage obtained through different verification methods gets added up.

With the expansion of SoC’s size and complexity including hardware, software, and firmware, the verification space of SoC also has expanded enormously. In such as scenario, imagine a configurable IP getting added up. How do you ensure all of its configurations are validated? It expands the verification space further, multiplied by the number of configurations. This keeps the cost of verification increasing.

In the IP-based business model, along with the design IP, the idea of verification IP (VIP) also came with the sole intention of verification automation and reuse of test plan, test bench, and test suite across multiple designs to boost verification productivity. Similarly, standard verification methodologies came into practice for verification automation and testbench reuse, UVM (Unified Verification Methodology) being the most popular. However, UVM is good for IP and at most subsystem level. The system level test is the bottleneck and that is where the verification space blows up. At the system level, as we have seen, there are multiple verification engines in work and there are multiple IP and subsystems. There is no automated methodology and reuse of tests and testbench across these multiple design levels and engines. This increases the cost of verification exponentially.

To automate verification and reuse at the system level, key initiatives are going on to establish software driven methodology based on use-cases and test scenarios. Accellerahas initiated a Portable Stimulus Working Group (PSWG) to establish a common standard of test and stimulus which can be used by a variety of users across different levels of design hierarchy (IP, subsystem, and system) under different execution platforms (simulation, emulation, FPGA prototyping, post-silicon, or any other) using different verification tools. Cadence, Mentor, and Brekerhave developed tools for system level verification; and they along with other PSWG contributors are working on establishing the common test standard and making their tools compliant with this standard. This can definitely start a new chapter in verification from system-level and reduce the burden of cost of verification by a large extent through test automation and reuse across multiple design hierarchies as well as verification engines. However, this methodology is yet to be established and needs semiconductor industry level investment, effort, and time. Read the article “Moving up Verification to Scenario Driven Methodology” for more details on this initiative.

Cost of Learning – As the complexity of SoCs keeps growing the verification space is always open for new learning. In the last section, we talked about the use-case based verification methodology which is being explored for verification at the system-level. Even after this methodology is established, there will be a cost involved in training the verification engineers on this new methodology.

In verification space newer formats, protocols, and standards keep emerging, especially in IoT, mobile, and automotive segments. This needs budget, time and effort set aside for design and verification engineers to learn. Moreover, the verification engineers need to have complete knowledge about the system and the environment or market segment in which the system is going to operate.

Apart from the system and design, the learning has to happen at the process and foundry level as well. The advanced process nodes such as FinFET nodes are distinct with foundries and hence the learning effort gets multiplied. The design, verification, and process engineers need to work closely to understand the new process and its associated rules. The process engineers may need to work in the actual foundry environment to learn about the advanced technology aspects and impart that knowledge to the design and verification engineers for them to incorporate the same in the design and its verification.

Cost of Redundancy – A peculiar scenario arises when you configure an IP to serve multiple requirements for different market segments. Not all the segments are served at the same time, so there are unused portions in the design and those can vary in different situations. This brings redundancy along with configurability. The redundant circuit may also consume power unnecessarily if not architected well enough to remain shut when not in use. Such wastage of power may not be completely eliminated through multi-mode operation of the SoC. Another case of redundancy comes when an IP characterized for a particular technology node is no longer reusable for another technology node through the use of automated technology migration tools; the IP needs a fresh architecture and rework. In such cases, a proper ROI analysis must be done for the IP to remain profitable in single use.

Summary – There are methodologies being explored to reduce different types of costs through automation. However, it depends on the specific methodology and the type of cost that can be reduced. Moreover, the automation methodologies such as system-level synthesis and verification need to be established before they can be explored for wider use. Intermediaries such as eSilicon have come up that provide IP services for SoC vendors to do a pre-evaluation of IP integration into their SoCs before buying it. The eSilicon business model is very flexible where they can be paid for an IP either after pre-silicon evaluation or after production. The semiconductor ecosystem is trying to establish a series of drivers that can keep the IP costs in control and the IP-based SoC development model afloat.

First part of this article is HERE.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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Moore’s law limitations and gravitational collapse at lower process nodes

Moore’s law limitations and gravitational collapse at lower process nodes
by Vaibbhav Taraate on 10-05-2015 at 4:00 pm
Categories: Foundries

As stated in my previous article, about the complexity of the SOC with billions of transistors. It is essential to consider the real practical scenario for the two dimensional verses three dimensional structure of the chip. Although the new technological changes and evolution for the shrinking process node can create ease for the design of SOC still there is limitation due to fundamental laws.

At the lower process node there is limit due to Einstein’s relativity theory. As none of the particle can travel through the material with more than speed of light ( Mainly affected due to dielectric constants). So the reality is the uneven distribution of power density at Tera Hertz of frequency. Even if the three dimensional routing architecture is also used then it will give birth to the variation of electric field across the surface of interconnect and it creates issues for the interconnect modeling and interconnect test validation. So this area need to be evolved. The 2 dimensional architecture of any chip can have variation in the form of ( x,y,p,v,t) but for the three dimensional chip architecture has always variation in the form of (x,y,z,p,v,t,E and power density) so it really involves the eight dimensional analysis below 14nm process node.

According to uncertainty principle published during 1925-1927 by Heisenberge ” The more precisely the position is determined, the less precisely the momentum is known in this instant, and vice versa.” So for the 3 dimensional chip architecture it involves the tight relationship between the energy , time and even space and time. Due to shrinkage as atomic spacing reduces it creates the vertical and horizontal components at the surface of conductor and it leads to the power losses across the surface and can affect on the overall data convergence. For billion transistor SOC at Giga Hertz or Tera Hertz the performance is real bottleneck due to the atomic spacing and the speed of data transfer between the carriers.

According to Landauer’s principle” There is minimum possible amount of energy required to erase one-bit of information and called as Landauer’s limit.” So according to Landauer’s principle if observer looses the information then it loses the ability to extract work. So for SOC at the lower process nodes it has greater impact in the data transfer from one node to the billion of nodes.

According to Bekenstein the black holes should have well defined entropy. And even if we consider the variation of the temperature across the chip then according to the Bekenstein bound, ” There is maximum amount of information can be stored in the space which has finite energy” By considering this for the 3-dimensional SOCs the real issue is the decay of the data transfer at the higher speed due to the losses across the surface of interconnect and even it can lead to the gravitational collapse due to uneven distribution of the power density at lower process node at higher speed .

So below 14 nano-meter for billion density SOC the performance and life of SOC is the real challenge for any chip designer and due to that shrinkage will have limitation even with the three dimensional architecture of the chip. The effect of the data transfer from one of the node to billions of nodes and gravitational collapse can be much higher below 10 nano-meter process node.

In such scenario the doubling of transistor in Integrated Circuit will affect heavily and it will take much more time to double the transistors. So according to my mathematical calculations and analysis using the fundamental laws, “For billion transistor SOC below 10 nano-meter will take 36 to 38 months to double the transistors with the required improved performance.”.

So at the lower process node there is requirement of the real evolution of the manufacturing processes and even design flows. So the universal modification in the Moore’s law is very much required. And the modified Moore’s law can be stated as ” The number of transistors in dense Integrated Circuit has to be doubled in approximately 36 to 38 months”. Even this will have greater impact on Rock’s law and manufacturing processes for three dimensional integrated circuits!

Also read: Moore’s law observations and the analysis for year 2019

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Solidly Across the Chasm

Solidly Across the Chasm
by Paul McLellan on 10-05-2015 at 12:00 pm
Categories: EDA, Solido

Last week I wrote about EDA companies crossing the chasm, with Jim Hogan (who needs no introduction) and Amit Gupta, CEO of Solido. So how did those rules work out for Solido?

See also Getting EDA Across the Chasm: 15 Rules Before and 5 After

The founding team of Solido:

  • discovered process variation for analog was a problem as companies moved to more advanced nodes
  • validated with 3 major accounts
  • raised $9M in VC funding
  • hired team, developed initial variation for analog products
  • innovated technology, and captured in 15 patents
  • partnered with Synopsys, Mentor, Cadence, Agilent for flow integration
  • Established the business licensing model
  • Iterated with lead customers to develop minimum viable product and establish product-market fit
  • generated first POs
  • survived the 2008 downturn when evals were canceled and customer budgets froze

Post-chasm (now):

  • broadened product to address custom digital, standard cell and memory markets
  • iterated on sales recipe until found a winning formula
  • over 30 customers, over 1000 users
  • growing 60% year-on-year revenue, margin growth over 90% YoY, generating cash (so no need for further capital)
  • adding new product to leverage existing infrastructure

As for that third phase for Solido, (exit aka liquidity event) they are still private so it hasn’t happened yet. But maybe the Hogan Midas touch will strike again: appear on Hogan’s small company stage one evening, get acquired (or in the case of Jasper, don’t even make it to the stage first).

One part of the secret sauce of Solido (and also of Amit’s previous foray into founding EDA companies, Analog Design Automation) is that it is based mostly in Canada. Not even in a hipster city like Montréal or Vancouver, they are in Saskatoon, Saskatchewan. Outside of the city itself, there is a lot of farming all around, and not much else. Plus there is not even wheat around for a lot of the year, just snow.

There are several advantages to being in Canada. An engineer (masters degree in CS or EE) is paid $C50-80K (that is $40-60K at the current exchange rate although the US dollar is unusually strong right now). However, the Canadian government provides R&D refundable tax credits and the loaded cost of an engineer ends up being about $20K/year. This is equivalent to India but with a much more convenient time-zone (they are due north of Denver).

These credits apply anywhere in Canada, and not just for EDA. As a result there are startup ecosystems in a few cities such as Vancouver and Toronto. But there is more competition for hiring, leading to higher salaries (costs) and more issues with turnover than in Saskatoon.

There is also Canadian investment money available from sources such as Golden Opportunities or BDC Venture Capital, the VC arm of the Business Development Bank of Canada.

People who live in Saskatoon have a reason to be there, typically family. EDA is cool there, unlike in Silicon Valley, and there are limited hi-tech alternatives. There is no Facebook or Uber. As a result it is relatively easy to attract and retain talent. The University of Saskatchewan is there with Masters and PhD programs in electrical engineering, and another university not far away in Regina.

Most exits are cross-border. The company is founded in Canada but gets acquired by a US company. Amit’s previous company, Analog Design Automation, was acquired by Synopsys, for example. If a company in Canada exits then there is one nice perk. In order to make it easy for farmers to pass their farm on to their children without having to break it up, Canada has a one-time capital gains tax exemption of $C750K. But it applies to everything, not just land transfer.

Oh, and you remember that part from last week about selling the company as well as the product. You just got sold to. Probably not relevant, you are almost certainly not going to buy a company, but Wall Street types and CFOs read SemiWiki too. You never know when the right serendipitous conatct will come by. When I was at VaST we did a sizable deal with Intel because a random engineer wandered by our booth at DAC and wondered (the other meaning of wandered) what we did.

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What NoCs with virtual channels really do for SoCs

What NoCs with virtual channels really do for SoCs
by Don Dingee on 10-05-2015 at 7:00 am
Categories: IP, Sonics

Most of us understand the basic concept of a virtual channel: mapping multiple channels of traffic, possibly of mixed priority, to a single physical link. Where priority varies, quality of service (QoS) settings can help ensure higher priority traffic flows unimpeded. SoC designers can capture the benefits of virtual channels inside a chip with network-on-chip (NoC) strategies. Continue reading “What NoCs with virtual channels really do for SoCs”

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Something Old, Something New…EDA and Verification

Something Old, Something New…EDA and Verification
by Ellie Burns on 10-04-2015 at 12:00 pm
Categories: EDA, Siemens EDA

When I got the opportunity to blog about verification, I thought, what new and interesting things should I talk about? Having started my EDA career in 1983, I often feel like one of the “oldies” in this business…remember when a hard drive required a static strap, held a whopping 33 MB, and was the size of a brick? Perhaps they should get someone who has just a few less EDA miles on them? However, thinking further on it, “we veterans” have experienced big changes in design and verification and the impact that tools and technology have had in creating new devices and exciting new markets that are changing the way we live. We have a lot to share.


That’s why I’m initiating a series of blogs to discuss valuable insights into the methodologies, tools, and flows we will need to move into the next generation of high technology. I’ll begin with several blogs about a trend I am seeing now—further reducing the power in designs in a world of increasing performance using a fairly complex interaction of HW and SW. After looking at the most important trends in low power, we’ll broaden our conversation to encompass other trends in verification.

We are seeing that how a typical ASIC or SoC low power design is done is starting to change dramatically. Current low power design and verification methodologies are breaking down, with some of the most successful leading semiconductor companies even losing business because they did not reduce power enough. The traditional implementation-focused low power methodologies are being strained because they ignore a whole phase of the verification process—those that exist at the RTL or above. And companies everywhere are feeling the pain.

We need new low power methodologies, we need new tools and flows, and we need low power techniques that make it easier to incorporate low power design and verification very early in the design cycle. Waiting until the entire SoC/ASIC is assembled and implemented is not the best way to optimize for power. We are now seeing SoCs going from 10 to 100 power domains, which introduces a whole new level of complexity in the design. How do you know that you have properly verified all of the states and interactions? Should you have a methodology that considers low power coverage now?

It’s neither feasible, nor prudent, to wait until the back end of the design flow to start paying attention to low power design techniques and their validation, as it is done presently. Too many interactions with lower power circuitry are missed, and it is too late to make design changes that either fix bugs introduced by low power cell insertions or optimize the balance between power, performance, and area. You need to move up in abstraction and have the tools that support there. You need to start thinking about power at the RTL or above.

First of all, we need to take full advantage of new capabilities in the Unified Power Formant (UPF) that allow you to begin power management at a higher level of abstraction. Up until now, the UPF has tended to be implementation-oriented. But describing power intent at this low-level of abstraction is inefficient, forcing power intent information to be managed across different stages of the design flow and across different implementations of a particular system.

EDA companies have been working diligently with the semiconductor industry to develop an enhanced and more useful standard that provides more capabilities. After all, you have to make sure that all of those things you’re doing to achieve lower power in your designs—like power gating, multi-voltage design, etc. —don’t screw everything up. Adding these to your design can essentially create a brand new design. So there are BIG differences between traditional simulation and low power simulation. You need to make sure you are using the best, and the appropriate, power aware tools and techniques in your entire verification flow—from simulation to formal to emulation.

As I implied, some of us may be old, but we “ain’t dead yet.” Our experience can help guide the industry toward a brave new technological world. In forthcoming blogs I’ll explore in more depth what’s changed in low power technology and what you need to look for in solutions you WILL need to stay nimble.
My next blog will look at what’s been happening in UPF to help facilitate the new wave of changes coming in low power solutions. We’ll delve into a new power-design methodology, called “successive refinement,” as used by ARM®, which integrates low power verification techniques starting from the IP block through SoC integration and implementation.

Subsequent blogs will talk about specific aspects of the successive refinement flow: things like issues with multi-clock domain designs when low power circuitry is introduced, what you should be looking for when debugging low power designs, the way you should approach low power coverage, and why you need emulation to for HW/SW co-simulation in a low power environment.

I would also like to hear your stories about your successes—and stumbling blocks—in our constantly and rapidly evolving electronic landscape.

Until next time, if you want to read a good overview of low power challenges and solutions, check out the on-demand web seminar “New Low Power Verification Techniques” at:http://www.mentor.com/products/fv/multimedia/new-low-power-verification-techniques

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Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes

Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes
by Pawan Fangaria on 10-04-2015 at 7:00 am
Categories: EDA, Synopsys

There was a time when design goals were decided in the beginning, targeted on a particular technology node, design planning done for the same, and implementation done through point tools connected indesign flows customized according to the design. It’s no longer the case for modern SoC designs; there are multiple technology nodes to consider before planning for a design, a complete design system has to be in place with tools at all levels sharing design information as required, smart methodologies must be employed to gain best accuracy, and planning done at each stage for better QoR and faster design closure. While there is no relaxation in PPA (Power, Performance, and Area) optimization, in Synopsys’ terminology the design completion has to “shift-left” with fewer resources and shorter time.

With that notion in my mind, when I came across the webinar from Synopsyson their Lynx Design System which was used to implement a network design with 16 ARM®Cortex®-A53cores and ARM Corelink[SUP]TM[/SUP] CCN-502on Samsung14LPP process, I happily attended it. Although new capabilities of IC Compiler II and Lynx Design System were introduced during this year’s DAC, I was interested to know more about these in a real design environment.


The Lynx Design System is ready for advanced technology nodes with leading foundries such as TSMC, Samsung, GLOBALFOUNDRIES, UMC, etc. Technology plug-ins are available to help customers quickly setup desired technology nodes. The design case in this webinar used the technology plug-in for Samsung’s 14nm technology node and Synposys’comprehensive RTL-to-GDS design flow in conjunction with ARM standard cell libraries. The platform already is being used by 50+ companies. The IC Compiler II P&R system is equipped with a versatile infrastructure to support multi-corner, multi-hierarchy, multi-mode, multi-voltage, and multi-view design; and powerful new floor-plan, clock-tree, timing and optimization engines. It provides up to a 10x increase in productivity with 5x faster implementation and half the iterations, all with better QoR.


Lynx employs a plug-in architecture where a technology independent layer of global methodologies can be combined with a technology specific layer as per foundry process requirements. The customized flow provides significant productivity for designers.


The system provides a flexible, user-friendly, iterative, and productivity-oriented flow where designers can explore for better alternatives and tune the flow accordingly with the help of a Runtime Manager. The Design Tracker provides progress reports in different forms including tables, graphs, and bar charts with links to original data files for faster access and analysis. There can be multiple tables, plots or bar charts in a report. Also proper data security is maintained for authorized access of files and reports. Separate reports can be obtained for designers’ and managers’ needs where a designer can dig into design specific attributes whereas a manager can check the project status. A good demo on design tracking is available in the webinar.


The QoR Viewer in the Lynx Design System provides many built-in reports for designers to analyze and ensure the best QoR for a design.

By using Lynx Design System designers could create an energy efficient processor subsystem reference implementation in just four weeks of time.


Frequencies of 1.44 GHz at ssa/0.72v/40c process corner and 1.7 GHz at tt/0.8v/25c process corner were obtained against planned 1.5GHz. The Lynx Design System provided best efficiency by combining fast hierarchical synthesis at pre-route stage and flat P&R implementation down the stream. The hierarchical synthesis employed Synopsys Physical Guidance (SPG) technique in Design Compiler Graphicaland flat P&R implementation leveraged the best capacity, runtime and QoR provided by IC Compiler II. The combined hierarchical synthesis and flat P&R approach reduces the overall TAT by 40% in this case.

Interactive design planning at the top level coupled with intelligent techniques such as module placement optimization and timing optimization through effort indicators on fly-lines makes the design more productive down the flow. The implementation flows at both synthesis and P&R stages can be tuned for best QoR and runtime. The Design Tracker can be used to review design summary, synthesis, clock-tree synthesis and other reports at various stages in both hierarchical and hybrid flows.

Chad Gamble at Synopsys has explained the system in more detail with good demos during the presentation. After a small registration step, the webinar of ~40 minutes can be attended HERE.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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TSMC Award Recognizes Andes’ IoT Credentials

TSMC Award Recognizes Andes’ IoT Credentials
by Majeed Ahmad on 10-03-2015 at 7:00 am
Categories: Andes Technology, IP

The system-on-chip (SoC) movement is intrinsically linked to external IP products, and here, it’s not just fabless chipmakers who work closely with IP suppliers. Large foundries like TSMC also maintain close relationships with IP vendors to optimize their process nodes and libraries for processor cores and other design architectures that these IP firms provide.

Now if you look at the SoC landscape, while mobile markets provide the bulk of volumes, the Internet of Things (IoT) platform is clearly the next frontier. The testament of IoT’s growing clout is TSMC’s strategic focus on expanding its ecosystem to serve the IoT markets. Case in point: the world’s largest pure-play fab has built a close liaison with Andes Technology Corp., a supplier of low-power and low-cost embedded CPU cores also based in Hsinchu, Taiwan.


Andes wins TSMC’s 2015 Partner of the Year award for New IP

TSMC has presented Andes the 2015 Partner of the Year award for New IP during the company’s recent Open Integration Platform Ecosystem Forum. TSMC’s symposium is aimed at having its customers and ecosystem partners under the same roof and share with them new solutions for the prevalent design challenges.

The award, received by Emerson Hsiao, Senior VP of Andes Technology USA, underscores the three-way ecosystem between chipmakers, fabs and IP suppliers. Hsiao claims that Andes’ CPU cores have been shipped in over 700 million chips, and the majority of these chips have been fabricated at TSMC. The Hsinchu, Taiwan-based IP licensor, which houses its key CPU designers in Sunnyvale, California, also boasts 85 customers worldwide.


Hsiao: 700 million CPU sockets and counting

At the OIP symposium, Suk Lee, Senior Director of TSMC’s Design Infrastructure Marketing Division, acknowledged the crucial importance of power efficiency in the emerging IoT applications and subsequently the role of processor IP in power savings in the next-generation IoT chip design.

Andes offers a series of 32-bit processor cores labeled as N7, N8, N9, N10 and N13 and these IPs are targeted at IoT applications encompassing areas such as smart sensors, smart appliances, medical, touch panels and wireless charging.

Andes’ IoT Play

There are clear signs that IoT has started to disrupt the microcontroller segment where the growth now mostly depends on how MCU makers innovate and differentiate their chips for specific IoT markets. Here, Andes’ 32-bit processors and associated SoC platforms offer a viable alternative to other processor cores such as ARM and MIPS to better differentiate their products.

Second, given the fact that the IoT industry is still in an embryonic stage and most IoT products have low or medium level volumes, Andes’ low-cost structure goes a long way for the IoT-centric chip designs. Third, a smaller code size greatly helps in longer battery life that epitomizes the IoT value proposition.

Andes was founded in 2005 with the vision of hardware functionality specific to power saving needs of the new computing paradigm that would serve machine-to-machine (M2M)-like services. Since then the company has been making steady gains with its 32-bit processor cores in the emerging IoT markets like smart home and connected wearables.

Andes scored a major design win earlier this year when the SoC powerhouse MediaTek announced to license its N9 processor core. It’s worth noting that MediaTek has so far been exclusively working with ARM processor cores.


MediaTek licensing N9 core is a major endorsement for Andes

Andesis also exploring the diversified potential of IoT markets through the community platform Knect.me. The website showcases IP solutions, software stacks, and tools for SoC implementation for chipmakers, application developers and system houses. Next up, Andes is planning to create the “IoT League” to showcase products that have been developed through the Knect.me community.

Also read:

Andes: 32-bit MCUs Way to Go for IoT

A Brief History of Andes Technology

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What’s Testing Design Limits at ITC?

What’s Testing Design Limits at ITC?
by Beth Martin on 10-02-2015 at 12:00 pm
Categories: EDA, Siemens EDA

The 46[SUP]th[/SUP] IEEE International Test Conference (ITC) will be held the week of October 5, 2015 at the Disneyland Hotel Conference Center in Anaheim, California. ITC is where you will discover the latest ideas and learn about practical applications of test technologies.

As you take in panels, tutorials, presentations, and the exhibits, you might find that some common themes emerge as the folks in the world of test grapple with finding solutions to today’s biggest issues. I talked with Ron Press, Technical Marketing Director of Tessent Solutions at Mentor Graphics, and Vice General Chair of the ITC Steering Committee about the trends he sees that are testing the limits of test technologies.

According to Ron, “We see two growing trends that people are trying to resolve. The first issue is how to provide efficient test methodologies when dealing with giga-gate designs. The other issue is how to manage pattern-set sizes in these huge designs as well as supporting designs with additional patterns, such as cell-aware, in order to meet quality requirements.”

To address the deployment of giga-gate testing, Ron said, “Hierarchical test is beneficial for designs with 20 million gates and often viewed as required for designs over 40 million gates.” Divide and conquer has been the methodology employed for all phases of enormous chip design and design-for-test (DFT) now joins that practice. Using hierarchical test, the DFT features and test patterns are completed on individual blocks and then reused at the top level.

Teams bringing hierarchical test to bear on big designs are looking to achieve these goals:

  • Move up DFT insertion and pattern generation earlier in the design process
  • Reuse block-level patterns
  • Allow geographically-dispersed teams to work on individual blocks without needing the top-level design
  • Enable automatic test pattern generation (ATPG) to be performed on smaller workstations
  • Significantly reduce test time and ATPG run time

It is a myth that top-level pattern generation for the entire chip in one ATPG run is more efficient for test time versus testing blocks individually. Actually, hierarchical test is often 2-3x more efficient than top-level test. Annapurna Labs is presenting a conference paper on their hierarchical test methodology. Spreadtrum Communications and Mediatek will be discussing their successful use of hierarchical test techniques in the Mentor Graphics Theater.

Huge designs fuel the growth of scan pattern-set sizes. Ron said, “A new approach is necessary to greatly improve the ability to efficiently test designs with large pattern sets. This approach applies a new type of test point identification to embedded deterministic test (EDT). We have seen a 2x-4x reduction in test-pattern count using this new approach.”

With the growing use of cell-aware patterns, test teams see bigger demands on test time. That is why there is growing interest in the new EDT test point solution. For example, Intel is presenting a paper at the conference that relates their success in using EDT points for compact, cell-aware tests. In the Mentor Graphics Theater, Broadcom will be discussing real-life data on their experience using EDT points.

If you are heading to Disneyland for ITC, be sure to attend the hierarchical giga-gate testing and managing pattern-set size sessions. Drop by the Mentor Graphics Theater to hear real world applications of these solutions. And, introduce yourself to Ron Press. He is always happy to talk about test.

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Getting EDA Across the Chasm: 15 Rules Before and 5 After

Getting EDA Across the Chasm: 15 Rules Before and 5 After
by Paul McLellan on 10-02-2015 at 7:00 am
Categories: EDA, Solido

Crossing the Chasm by Geoffrey Moore (not that G. Moore!) is one of the most well known books on high technology marketing. When I worked at VaST, Mohr Davidow Ventures (MDV) invested in us and Moore (not Mohr), who was a partner there, spent an afternoon with us brainstorming what it would take for us to cross the chasm. Coincidentally, Crossing the Chasm is actually a similar, but more readable, version of an earlier book called Marketing High Technology by Bill Davidow (yes, the D of MDV) which is where the concept of the whole product was introduced. The key insight of both books is that while early adopter enthusiasts will do a lot themselves to compensate for missing pieces of the ecosystems, the mainstream will not. Having a whole product that is ready for the mainstream is really what it takes to get across the chasm.

Jim Hogan and EDAC have been running a series of discussions with founders of EDA startups on what it takes to cross the chasm. Kathryn Kranen (of Jasper, now part of Cadence), Ravi Subramanian (of BDA, now part of Mentor) and Amit Gupta of Solido (still independent). The next evening is in December but I don’t yet have a date. The guest will be John Lee, now a VP at ANSYS having been the founder and CEO of Gear before selling it to them.

I sat down last week with Jim and Amit to talk about what it takes to get over the chasm. Very few EDA companies cross the chasm to, say, $5-7M in revenue. It is fairly easy to get to $1M, everyone has some friends. But $5M to $10M to $20M is a hard progression to achieve. I should point out that Amit’s views are not just based on Solido. He was the founding CEO of Analog Design Automation (ADA) which was acquired by Synopsys in 2004.

I read somewhere that listicles are click-bait on the net, so here is a recipe listicle style:
[LIST=1]

  • Find out what the customer pain points are from technology enthusiasts
  • Validate customer pain points across many technology enthusiasts in many different companies. Don’t design a solution for only one company/enthusiast
  • Ensure that there is a large enough market if the product is successful. Avoid the “Intel only needs one copy” products.
  • Ensure that there is alignment between technology enthusiasts, company pain points, and what companies will pay for. Avoid science projects for technology enthusiasts (Intel doesn’t need any copies at all)
  • Figure out a business model to capture the value being delivered (floating licenses, site license, royalty…)
  • With 1-5 raise any investment needed to execute
  • Innovate to solve customer pain points with 10X differentiation from competition (especially big guys who can say they will have it next year if it is just 2-3X better)
  • Hire a product development team capable of delivering product with the customer in the loop
  • Develop minimum viable product
  • Iterate until successfully deployed minimum viable product with technology enthusiasts (early adopters) finding product-market fit
  • Establish needed partnerships with big EDA companies to integrate product into customer flows (Cadence Connections, Synopsys InSync, Mentor OpenDoor etc). This will also require customer references.
  • Survive any market downturns, there will probably be at least one period of weakness/trauma
  • Execute fast enough that competition doesn’t catch up, market window doesn’t pass (although being too early is often more of a problem), and you don’t run out of money
  • Fail fast on stuff that isn’t going to work out
  • Close first purchase orders. The only validation that counts.

    If and only if (aka iff for mathematicians) you successfully complete all these steps do you have a shot at crossing the chasm. Then you can read Geoffrey Moore’s next book Inside the Tornado (which uses Synopsys as one example). This is the point at which you throw gasoline on the fire. In my opinion, it is the critical decision point in an EDA company (and many other types): when do you ramp sales. Too early and you run out of money paying a sales force who cannot sell the immature product. Too late and…this never happens.

    Then you need to:
    [LIST=1]

  • Mature the whole product solution for deployment to a larger mainstream audience (proliferation)
  • Develop a sales recipe for short evaluations at high success rate. Aim for 90 days from discovery to close, not 9 months
  • Build out the company: engineering, AEs, marketing, sales, G&A
  • Deploy and support larger customer base
  • Grow

    Then in the third phase there is a very short list:
    [LIST=1]

  • Be acquired
  • IPO…this never happens, especially post Sarbanes-Oxley
  • Grow profitably, generating cash (Denali showed it can be done for many years before Cadence made them an offer they could not refuse)

    For the biggest picture of all, the whole company, there are also a few rules. First, never take more than $10M in investment ($5M is better) or it will be really hard to sell in a way that makes everyone whole (carve-out and cram-down are not good words). Patents are important, research shows $300-900K per patent in additional exit valuation over and above forward revenue multiple. But don’t do too many since they are expensive to file and expensive to maintain. Market the company too, not just the product. Sell the sizzle as well as the steak.