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Processors Rule the Day

Processors Rule the Day
by Tom Simon on 10-09-2015 at 7:00 pm
Categories: IP

It used to be that if you went to a processor conference, you could expect to spend hours listening to talks about pipelining, cache schemes and processor architecture. Well, I went to the Linley Processor Conference this week in Santa Clara and found the topics pretty compelling. Processors are in just about everything. It is easier to ask what does not contain a processor. So this conference was, in many ways, about just about everything. Chief among the topics was automotive, mobile, networking, IoT, consumer and enterprise.

The keynote was given by Linley Gwennap, principal analyst and founder of the Linley Group. His talk was titled Processor Technology and Market Trends. He covered general embedded trends, processor IP, networking, IoT and advanced automotive. The presentations over the two days drilled into all of these areas.

In 2014 Intel had the lion’s share of the embedded market. This comes about from them leveraging the PC ecosystem for things like ATM’s, signage and other appliance type applications. Next in market share is Freescale who has a strong lead in the comms sector. Next, each with smaller shares are Broadcom, Cavium, AMD, LSI, Marvell and AppliedMicro.

If you have been following the news, you already recognize many of the above companies from the business pages. There is a wave of consolidation. NXP acquires Freescale, Avago acquires LSI and Broadcom. Look for the ripple effects from these changes.

Consumer, IoT and mobile/wearable all require cost, power and footprint reduction. The most effective way to accomplish this is through integration. There is an increase in SOC complexity. During the conference, many examples of processor based SOC’s had many other functional blocks on board, and also in some cases many processors – each targeted at a specific sub function.

Designing these SOC’s requires a deep understanding of application needs, so they can operate most efficiently. The right processors need to be used, along with specific IP and the software to drive the whole system. Complexity is rising.

Linley sees the benefits of Moore’s law only applying to companies with the money to take advantage of it. The increases in mask costs due to double patterning is contributing to this. 28nm is a hinge node, where for the first time if you go to a smaller node you will pay more per transistor. This is forcing costs sensitive products to stay on 28nm.

There is real movement in the high end embedded space to ARMv8. AMD, AppliedMicro, Cavium, Freescale are already shipping ARMv8 cores. Broadcom and Marvell are in development. This is a big push into the 64bit ARM architecture for applications that need the horsepower.

With smartphones containing 2 to 4 chips with CPU IP, this segment drives the most shipments. However, the fastest growing segment is embedded, growing at 29% in 2014. Most of this is MCU’s. In 2014 CPU IP was used in 15.3 billion chips. Two thirds of which were mobile and embedded.

Heterogeneous processors are now commonly combined onto one chip. This enables each processor type to be optimized for specific tasks. Listening to music might be done with a DSP, email can be handled with a small, slow CPU; but video will be shifted to heavier duty processors that consume more power. Turning off unneeded processors can dramatically increase battery life. This trend is increasing for other reasons. Physically partitioning tasks offers greater security as well.

Automotive applications were a big topic for the entire conference. As cars add safety and convenience systems a large need for processors is developing. Some notable applications include adaptive cruise control, which can maintain a safe following distance to the car ahead. Drowsiness detection and lane detection are two other significant safety systems that will require significant processing power. The big prize of course is the self driving car. Linley expects fully autonomous technology to be available as an adder of less than $10K by 2022.

The talk and the conference showed just how much technology is moving to adapt to our needs. During the conference I realized that the idea I had in my mind about what my first robot would look like was wrong. Of course I imagined something that could ‘see’ its surroundings through sensory input and respond to them. I also imagined that it might have a neural network, and processes information much like a human brain. It would have awareness of its location and be able to move from place to place. What I did not realize is that I would sit inside of it – and that it would probably be a car.

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Five Areas at #53DAC That Require Your Contribution

Five Areas at #53DAC That Require Your Contribution
by Daniel Payne on 10-09-2015 at 12:00 pm
Categories: EDA

The 53rd DAC (Design Automation Conference) is some 8 months away, however to make this conference and exhibit another success requires planning, people and awareness. That’s where you come in, because you can contribute your expertise in five different areas:

[LIST=1]

  • Panels – broad interest, interesting, timely, engaging, informative
  • Special Sessions – track specific, original angle, educational
  • Tutorial – hands-on, immediate value, 1.5- 3 hours in length
  • Workshops – not vendor-specific, two – nine hours, multiple speakers
  • Research Papers– papers on design of circuits, architectures and systems

    I’ve organized a DAC panel session before all about SPICE circuit simulators and it was a blast to select the topic, find speakers, and then come up with interesting questions for each panelist to answer in front of an audience. An open Q&A time is also part of every good panel to allow the attendees a time to ask their own questions or challenge what panelists just talked about.

    If you have ever attended a past DAC and thought about sharing what you’ve learned about our industry with others, then take that bold first step and consider contributing in any of these five areas. The DAC folks on the committee are quite helpful in answering your questions and leading you through the process, so why not give it a try?

    Not only are their five areas for you to contribute in, there are also six different tracks based upon your interests:

    • EDA
    • Embedded Systems and Software
    • Design and IP
    • IoT
    • Automotive
    • Security

    Having six tracks is something relatively new at DAC, and I think that it makes a lot of sense to align with the end-user markets instead of a singular focus on EDA software and algorithms.

    Bloggers from SemiWiki will attend this DAC as in past years and help keep you informed over the next 8 months about what to expect, emerging trends, and which companies look most promising to visit in the exhibit area. When I worked at EDA companies we would focus on showing our best, new features in time for DAC each year, often getting the new code ready just days before DAC started in order to look our strongest against all of the other competitors, so there’s a big benefit to having an annual event like DAC to keep our industry growing and responsive.

    Deadline
    The DAC website is filled with details on how to go about making a contribution, but you have to meet the deadline of November 17th to be considered for this event in Austin, Texas from June 5-9.

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    IMEC and Cadence Disclose 5nm Test Chip

    IMEC and Cadence Disclose 5nm Test Chip
    by Scotten Jones on 10-09-2015 at 7:00 am
    Categories: Cadence, EDA, ESD Alliance, Events

    Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.

    First off Vassilios really stressed the challenge of designing for 5nm and the need for collaborations like this one between imec and Cadence. Timing optimization and routing are very challenging! The IMEC/Cadence collaboration combines detailed process knowledge with EDA.

    The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers. The chips had a dummy metal 1 layer and via 1, metal 2 (M2), via 2 (V2) and metal 3 (M3) layers. The M2 and M3 layers were really the focus of the work and the metal pitch was scaled down from 32nm to 24nm.

    Three different patterning approaches for M2 and M3 that were evaluated:

    [LIST=1]

  • EUV
  • Hybrid 193i SAQP with EUV cut mask
  • 193i SAQP with 3 color 193i cutting

    The EUV approach used single exposure EUV to form the metal lines. The hybrid approach used argon fluoride immersion (193i) with self-aligned quadruple pattering to form the metal line patterns and then a single EUV exposure to define the metal line cuts. The 193i SAQP approach used argon fluoride immersion (193i) with self-aligned quadruple pattering to form the metal line patterns and then three separate 193i cut masks (3 color cutting) to form the pattern. A litho-etch-litho-etch-litho-etch (LE3) approach was used to pattern V2.

    All three approaches were found to be viable. The Hybrid and 193i approaches both use SAQP to define the metal lines and require more dummy lines than the single exposure EUV approach which should lead to better performance for the EUV single exposure. However, things like Line Edge Roughness (LER) might be worse for EUV and negate the advantage.

    Simulations included fins underneath and the resulting interconnect layers meet the timing needs for 5nm. The metal and barrier layers used were not disclosed. EUV throughput was also not disclosed but Praveen did say that imec is upgrading to an 80 watt source.

    The images above are from an article by Debra Volger of SEMI The Roadmap to 5nm: Convergence of Many Solutions Needed where she quotes An Steegen, SVP of Process Technology, at imec:

    “Imec is enabling the roadmap to 5nm via a multitude of process features in close co-optimization with the design to drive down to the required power performance and cost trade-offs,” Steegen noted. “We are convinced that we have identified building blocks to enable the roadmap from 10 to beyond 5nm. But it’s not a one-solution thing – it’s many things that need to come together.”

    Here are the quotes from the Cadence press release in case you are interested:

    “Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of Process Technology at imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-generation platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes.”

    By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “With imec technology and the Cadence Innovus Implementation System, we’ve created a working flow that can pave the way for developing innovative next-generation mobile and computer advanced-node designs.”

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    BATTERYGATE: Is Apple’s Samsung made iPhone 6S Core Rotten?

    BATTERYGATE: Is Apple’s Samsung made iPhone 6S Core Rotten?
    by Robert Maire on 10-08-2015 at 4:00 pm
    Categories: Foundries, Samsung Foundry

    By this time, anyone with a pulse in the tech industry knows that Apple has dual sourced the A9 processor for the Iphone 6S, from both Samsung and TSMC. There are even apps to tell whether your 6S has a Samsung or TSMC part in it. People have run performance comparisons and concluded that the processing performance is the same, which is entirely expected as we are sure both parts have the exact same logic design and are clocked at the same speed. Ones and zeros are ones and zeros on anyone’s chips….all things are equal in the digital world….

    Well…people have started to check in on the analog world of power consumption (where there can be a difference) comparing Samsung Iphones to TSMC Iphones, and low and behold the Samsung and TSMC made chips may not be quite so identical. Initial, amateur reports indicate a significant difference with Samsung parts consuming more power….far more..

    Here is an example of one such test result:


    Samsung A9 versus TSMC A9 power consumption tests

    We would remind readers That TSMC has made a very big deal about their power consumption/leakage advantage over other competitive manufacturing processes. TSMC has claimed up to a 20% power advantage in their 16nm process which may jive with these unconfirmed comparison results.

    Any measurabledifference could be a problem for Apple..
    The initial results look like a significant power consumption difference between the Samsung A9 and the TSMC A9, potentially measured in hours rather than minutes. Even if final analysis shows a 10% differential or less it could still pose a problem as Apple could start to see 6S owners returning their Samsung 6S for a “better” TSMC 6S. The bad press could really hurt Apple and its flawless image very badly.

    We think the difference better be less than 5% or problems will start. A 10% differential in power consumption would be bad, a 20% difference could be horrible and so on…costs and losses could mount up for Apple for returns, repairs etc;…. Even if these initial reports prove to be untrue and there is no significant power difference just the rumor mill buzz of two types of 6Ss can cause issues.

    Cottage industry for phone testers…
    There are already different apps that can tell which processor you have in your Iphone. One even reports the results back to a website that keeps score of TSMC versus Samsung parts. We can imagine that cell phone repair shops will charge customers $20 to see if they should return their beloved Iphone because it has a potentially flawed Samsung A9…..

    Faster than you can say class action lawsuit
    Lets start the stopwatch ticking on Oct 7th at noon and see how long before the first law firm brings a class action suit against Apple and their defective Iphone 6S. Will Apple have a recall? How will they handle the PR? It could be a circus of TV people interviewing people at Apple stores as they return their phones….just in time for the holiday season

    Conspiracy theories?
    We can only imagine the first conspiracy theory that Samsung did it on purpose to sabotage Apple’s phone business in favor of their own…..

    Blowback on Apple due to supplier gamesmanship…
    Apple is well known to press suppliers to the breaking point and beyond. Apple went to a new extreme and got very cute by dual sourcing the most critical component in the phone this way playing Samsung and TSMC off against one another. Could this now have blown up in their face? Who tested and vetted both parts at Apple? Where’s the quality control?

    We would question why Apple would even take the risk of using two different parts in the same phone….its just begging for comparison & trouble. Just use one part in the 6S and the other part in the 6S plus so you can’t compare them. Maybe Apple was forced into this position due to availability issues.

    In too much of a rush?
    We had pointed out almost a year ago that we were surprised that Samsung would be able to get the 14nm part out in time for the 6S launch. Early yields were low and Samsung would have to ramp faster then ever before to make it in time. Maybe it was just too fast a ramp and the part and the process was never fully perfected leading to the power issues.?..

    Intel’s schadenfreude…
    If this turns out to be true and a significant issue we will likely be able to hear the laughter in the halls of Intel all the way in New York (Intel had their own mathematically challenged processor many years ago). There has obviously been concern over Samsung and TSMC catching up to Intel….well maybe this could potentially prove at least Sasmung moved too fast and took too many risks versus Intels more cautious slowing of their tick tock cadence.

    Speaking of Intel, we are pleased with the performance of the stock, nicely and steadily up well over 10% since we turned positive on it a few weeks ago…looking better every day

    Leaky faucets and transistors…
    Transistors are like faucets turning on and off the flow of electrons or water, however transistors never fully turn off and tend to “leak” a little. This “leakage” is the primary culprit of power consumption in semiconductor devices.

    Leakage in transistors is due to a multitude of factors, many of which are interrelated. Transistor design is a big one, especially as the industry has recently switched from “planar” to “FinFET” transistors (which Intel pioneered). Materials and the processing of those materials by semiconductor equipment tools is very critical. Many different tools and materials impact leakage current.

    Though the logic design of Samsung and TSMC’s A9 is the same, the manufacturing process “flow” is quite different, using different sets of tools and materials and different steps in different sequences. TSMC has strongly made the claim that their 16nm process is superior to competitive offerings in terms of leakage/power consumption.

    Samsung is 14nm while TSMC is 16nm…
    Smaller is usually better in the semiconductor industry but everyone’s measure is not quite the same. Samsungs A9 uses a “14nm” process which results in a smaller die size (chip size), while TSMC uses a 16nm process that results in a larger chip which is usually associated with higher power consumption, but not this time around, making the potential difference even more intriguing.

    If Samsungs 14nm process proves to be inferior to TSMC’s 16nm process that will be a boon and huge win for TSMC and a huge loss for Samsung on the foundry side (aside from the obvious Apple problems). It could be a huge torpedo in the side of Samsungs Semiconductor business which has been their primary driver of profitability.

    What about the equipment companies?
    We can already hear the equipment companies taking credit for their equipment making the difference at TSMC and Samsung. If its does turn out to be equipment specific it would obviously have huge impact (Cue Art Z and UTEK) . We would imagine this has to be positive for process control companies like KLAC and smaller cousins Hermes, RTEC, NANO and NOVA etc;. Everyone will clamor to find out the root cause.

    This could turn out to be a circus…
    This has all the makings of a potential circus in the industry and in the stocks. Certainly negative to very negative implications for Apple if true. Negative for Samsung and positive for TSMC. Likely positive for some equipment companies but not all. Positive for Intel as it shows their process still reigns supreme.

    There are many , many moving parts and right now we still don’t even have solid proof that an issue even exists or enough information to analyze but we do understand the potential implications and want guard our portfolio against them.

    We will be waiting for more information and definitive tests…..

    Meanwhile…I am going to test our families new Iphone 6S and get in line to return it at the Apple store if it has a Samsung A9 before the rush happens……

    *Disclaimer: So far we have not seen a credible, reliable, scientific source of comparative power consumption testing – sources on the internet appear to show similar results but are unsubstantiated and therefore questionable so far…..

    Robert Maire
    Semiconductor Advisors LLC

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    Cadence Outlines Automotive Solutions at TSMC OIP Event

    Cadence Outlines Automotive Solutions at TSMC OIP Event
    by Tom Simon on 10-08-2015 at 12:00 pm
    Categories: Cadence, EDA, Events, TSMC

    I used to joke that my first car could survive a nuclear war. It was a 1971 Volvo sedan (142) that was EMP proof because it had absolutely no semiconductors in the ignition system, just points, condensers and a coil. If you go back to the Model T in 1915 you will see that the “on-board electronics” were not that different. However, today’s cars have an ever increasing amount of semiconductor content. Let’s just hope there are no EMP’s anytime soon.

    Automotive electronics systems now have enormous requirements for computation, bandwidth and reliability. I attended a talk by Cadence’s Charles Qi at the recent TSMC Open Innovation Platform (OIP) Forum where he outlined the major trends in this area.

    By comparison to current needs, the previous bandwidth requirements were quite low. Cars have used simple networks like CAN, but increasing complexity is leading to the adoption of Ethernet standards specifically adapted to automotive needs and environments. The diagram below highlights the kinds and numbers of systems that are going to be built into cars.

    As you can tell, there is audio, visual and sensor data that needs to be handled. There are strict requirements for timely delivery of certain data in automotive systems. The umbrella term for this is AVB, or Audio Video Bridging. It is broken down into a set of IEEE standards within 802.1BA. These standards address time synchronization, traffic shaping and priority queuing. Below is a diagram that lists the applicable IEEE standards for automotive communication.

    Ethernet offers many advantages. It can run over twisted pair, it can carry power and it is an established standard that will continue to provide legacy support for many years. Charles outlined Cadence’s IP offerings which address the evolving Ethernet communication needs in automotive applications. Here is his slide that summarizes Cadence’s solution.

    Many of the systems in the first diagram require significant processing power. Today’s systems already perform Advanced Driver Assistance (ADAS), and will be pushed even further when self driving cars arrive in earnest. Already radar based features include front collision avoidance braking, adaptive cruise control and rear collision detection. Additionally, there are vision and audio/sound based systems that will require computing power.

    Cadence is positioning its Tensilica IP as a solution for automotive processing. They have a power sipping architecture that can be fine tuned to specific applications; and the development tools work to create custom compilers and libraries for many of the coding needs encountered in developing systems for emerging automotive standards.

    Tensilica also offers customizable DSP cores to further accelerate automotive product development. Their IVP DSP’s are well suited for ADAS development. The IVP DSP offers VLIW and 64 way SIMD. Coming in under 300mW, they offer impressive performance with minimal power draw. One of the most interesting slides was on the problem of pedestrian detection. ADAS systems will need to do this efficiently and reliably, even if the person only shows in as small an area as 64×128 pixels.

    Charles also spoke about ISO26262; we will be hearing a lot more about this in the coming years. It is a comprehensive standard for ensuring functional safety starting at the requirements phase and going through implementation. Unlike phones and fitness computers, automotive electronics play a role in life or death situations. Everything designed for automotive applications will need to comply with ISO26262. Here is a slide from Charles’ talk that gives an overview.

    Well, I am still waiting for my self driving car. However, it is clear that automobiles will be competing on a lot more than looks and horsepower. In the meantime I look forward to the increased safety and possibly easier driving that things like front collision avoidance braking and adaptive cruise control will offer. For more information on Cadence IP for automotive applicationslook here at their website.

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    UFS or NVMe in Smartphone? See Apple’s answer!

    UFS or NVMe in Smartphone? See Apple’s answer!
    by Eric Esteve on 10-08-2015 at 7:00 am
    Categories: Arm, IP

    There should be a link between iPhone H/W architecture and the incredible success of the product? Let’s assume and claim that this architecture, based on the internally developed ARM based A9 application processor, is simply the best on the market today…

    Apple has implemented SSD in MacBook based on NVM Express (NVMe) protocol. It appears that Apple has adapted the NVMe controller developed for the MacBook to iPhone architecture (the red arrow on the picture below) and we will see that using SSD NVMe (instead of UFS) provide strong differentiation. I have found very exciting information from AnandTech, especially about the way Apple has implemented SSD control.

    We need to take a look at above picture, presented by Sandisk during the last Flash Memory summit. Apple is present in three segments: High-End PC (MacBook), Productivity Tablets (iPad) and Flagship Smart Phone (iPhone 6). In the last segment, storage was based on eMMC until recently and now most of the OEM is implementing MIPI Universal Flash Storage (UFS) specification. Except Apple…

    Let’s take a look at benchmark results: the two graphics at the top are for SSD sequential Read and Write, the other two are for random Read and Write.

    Before explaining why sequential accesses are almost 2X more efficient than for the competition, let’s see the impact of such performance. Sequential read/write is what’s happen when you download/upload a very large file, like for example a movie, the faster, the better it is for user experience!

    Another benefit is not as obvious. Improvement in performance also results in increased battery life: once the task is completed, the device can go back to idle state faster, positively impacting the power consumption.

    Now we will have to understand why using NVM Express (based on PCI Express protocol) provides better user experience than UFS, based on Advanced Host Controller Interface (AHCI) which has been defined to support SATA. Once again a slide extracted from Sandisk presentation will help. According with Sandisk, NVMe has superior S/W stack than UFS, as you can see below. Other facts are supporting Sandisk position: the biggest advantage of NVMe is its lower latency (2.8 us compared with 6 us for AHCI based protocol). Another important improvement is support for multiple queues and higher queue depths. Multiple queues ensure that the CPU can be used to its full potential and that the IOPS is not bottlenecked by single core limitation.

    At this point, we must clarify two points. First, Sandisk is clearly pushing NVMe adoption in flagship smartphone application and not MIPI UFS. The second point is that NVMe usage in smartphone is (most probably) still based on one MIPI specification, as the physical level MIPI M-PHY is selected and not PCIe PHY. It could be synthesized by:

    NVM (Application) –> PCI Express (Transport) –> MIPI M-PHY (Physical Layer)

    Using NVM Express protocol in smartphone application allows benefiting from the many advantages offered by MIPI M-PHY like reduced EMI or lower power consumption compared with other high speed PHY (USB 3.x or PCIe 2.0). One real advantage being that the SoC integrator has to buy (or develop), integrate and maintain a single PHY IP (the MIPI M-PHY) instead of several complexes PHY IP.

    This decision from Apple to integrate NVMe instead of UFS in the iPhone 6s and 6s Plus, leading to better performances in term of Flash memory access and better user experience, is very important as it indicates that PCI Express has been adopted in this key industry sector. In fact, PCIe is used for a while in smartphone, to support the interface between the WiFi device and the AP. It was the reason why the MIPI Alliance and the PCI-SIG have jointly defined Mobile Express (or M-PCIe).

    PCI Express has been initially defined (in 2004) to support the interface between the CPU and the GPU in the PC. Seeing PCIe protocol pervasion in mobile phone is a strong indication of technology merge between applications as different as PC and smartphone. Which work in one direction could also work in the reverse direction, ARM CPU, present in almost every smartphones, could start pervasion of the PC application…

    Article from AnandTech can be found here

    Sandisk presentation here

    Eric Esteve from IPNEST –

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    Dinner with the Man who is Reshaping the Semiconductor Industry!

    Dinner with the Man who is Reshaping the Semiconductor Industry!
    by Daniel Nenni on 10-07-2015 at 4:00 pm
    Categories: CASPA, Semiconductor Services

    The recent mega acquisition of Broadcom Corp by Avago can be traced all the way back to Silicon Valley stalwart Hewlett Packard (founded in a two car Palo Alto garage in 1939). Even more interesting is the man behind the acquisition and how he got to where he is today.Avago began as the semiconductor products division of HP in 1961, supplying parts to internal HP products. In 1999 HP spun off the division as part of Agilent technologies. In 2005 private equity firms KKR and Silver Lake Technologies acquired Agilent for $2.6B and formed Avago. In March 2006 Hock Tan joined Avago as CEO and director. Prior to that, Hock served as chairman of IDT, CEO of Integrated Circuit Systems, VP of Finance at Comodore International, and had senior management positions at Pepsi Co. and General Motors. He also has ties to the investment world in Singapore and Malaysia. Hock’s education is just as diverse as his experience with a BS/MS degree from MIT and an MBA from Harvard. Avago has an impressive 50 year history. You can see examples of their technology leadership and business milestones HERE. Not only does the Broadcom acquisition bring more products and customers under the Avago roof, it also brings the Broadcom name to the company that Hock will now run as Chief Executive. Hock’s other major acquisition for Avago was LSI Logic for $6.6B in 2014. The new Broadcom will be the number three semiconductor company behind Intel and Qualcomm I believe. It should also make Broadcom TSMC’s number one fabless customer (Apple is a systems company in my definition and QCOM is straddling Samsung and TSMC). My first Hock Tan sighting was at TSMC’s 2015 North American Technology Symposium. Hock was guest speaker and he struck me as a no nonsense type of guy who says it like it is. I’m also told he runs a VERY tight ship and has a VERY close relationship with TSMC and other manufacturing partners. In my quest to learn more about the man who is reshaping our industry I will be attending the annual CASPA conference and dinner banquet “Pioneering Technologies – Year 2020 in the Making” on October 24[SUP]th[/SUP] at the Santa Clara Convention Center. Hock Tan will be giving the executive keynote. It was a full house last year so you had better get your tickets quick!Registration: hereAnnual Conference Agenda:

    • 12:00-1:00pm, Registration & Networking
    • 1:00-1:30pm, CASPA Board of Director Election (first 200 voters receive gift)
    • 1:30-1:40pm, Welcome from CASPA
    • 1:40-2:15pm, M2M: The Embedded Revolution

    —- Stephen DiFranco, Senior VP, Broadcom

    • 2:15-2:50pm, Memory Technologies for 2020, Broader Market Survey & Roadmap

    —- Charlie Cheng, CEO, Kilopass Technology

    • 2:50-3:25pm, Global Mega Trends and the New Semiconductor Pioneers

    —- Stuart Ching, Senior VP, ARM

    • 3:25-3:40pm, prize drawing
    • 3:40-4:50pm, Panel: Leaders in the Making – How to Transform from Engineers to Executives

    —- Larry Chang, Executive Advisor at Ascend—- Buck Gee, Member of Committee of 100—- Thi La, COO of Corsair Memory

    • 4:50 ¨C 5:00pm BOD Election Announcement & Prizes Drawing (Apple Watch)

    Dinner Banquet Agenda:

    • 5:00-6:15pm, Registration & Networking
    • 6:15-7:00pm, Banquet Seating & Dinner
    • 7:00-7:15pm, Retiring Board of Directors Service Recognition Awards
    • 7:15-7:45pm, CASPA 2015-2016 Presidential Transition
    • 7:45-8:15pm, Executive Keynote: Hock Tan, CEO, Avago Technologies

    My beautiful wife and I will be there and we hope to see you then!Founded in 1991, CASPA has developed into the largest Chinese American semiconductor professional organization worldwide. CASPA consists of individual members, corporate sponsors, board of directors, board of advisors, board of volunteers, and honorary advisors. Headquartered in Silicon Valley, California, CASPA has 9 local chapters worldwide: Austin & Dallas Texas; Phoenix Arizona; Portland Oregon; HsinChu Taiwan, Pearl River Delta (Hong Kong, ShenZhen), Shanghai, Beijing and Singapore. CASPA also forms alliance with other associations to promote welfare of its members.

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    Coventor prepping MEMS for CMOS integration

    Coventor prepping MEMS for CMOS integration
    by Don Dingee on 10-07-2015 at 12:00 pm
    Categories: Coventor, EDA

    About 11 months ago, I wrote a piece titled “Money for data and your MEMS for free.” In that, I took on the thinking that TSMC is just going to ride into town, fab trillions of IoT sensors, and they all will be 2.6 cents ten years from now. Good headline, but the technology and economics are not that simple. This may be the semiconductor version of putting a man on the moon by 1970, but instead of one big rocket, we are building little things.

    My view is three basic classes of “sensors” are likely to emerge on that 10-year horizon: the RFID-like passive tag at something around 2 cents, the mass-market accelerometer at maybe 50 cents, and the high-performance RF switch or spectrometer at $5. The first category will have everything from printed electronics to integrated CMOS tags from TSMC and others. The last category will remain territory for boutique MEMS fabs.

    In the middle, there is room for debate and innovation.

    I also noted recent discussion in our “Inside the iPhone 6s” thread. In that, our Tom Simon noted two different accelerometers from different suppliers on the BOM, and reader @nick_rb replied that one is a high precision, higher power 6-axis IMU (Invensense), and the other a basic 3-axis unit (Bosch). That is a very revealing fact about the state of MEMS sensors today: performance isn’t cheap, in either BOM cost or power.

    The problem in the middle, and the biggest barrier to the TSMC vision, is the MEMS process itself and the integration challenges with CMOS logic. Coventor draws on the Chipworks teardown of the Apple Watch for a compelling example:


    The Apple S1 is not just a chip. It is a system on module, with 30 die integrated in a single package. It has everything from the processor to the touch sensor to the Bluetooth and Wi-Fi controller and more. Everything, that is, except the MEMS components, a 6-axis ST motion sensor and a Knowles microphone.

    Ample IoT opportunity exists, even when one tones down the hype of trillions of units. Better CMOS process integration would certainly create more design flexibility and open the potential for lower costs – at least for some MEMS sensor types. The question: how do we do this? The current CMOS and MEMS processes are at direct odds, from EDA tools and design rules to physical construction:


    Coventor has collaborated with X-FAB to launch MEMS+ 6.0, the latest version of their MEMS EDA tool with all new capability for process design kits (MEMS PDKs). Rather than leaving MEMS design up to handcrafted microbrewing, the idea centers on a library of simplified high-order finite elements for faster simulation and smoother exporting into a CMOS EDA flow. By enforcing process constraints and design rules, the generic MEMS library components can be customized to meet many requirements without breaking everything.

    MEMS+ 6.0 also improves the flow for the experienced MEMS designer. Its model reduction capability exports in MathWorks Simulink or Verilog-A, with automated reduced-order models providing higher accuracy and faster results. These models abstract design details, so they can be provided to third parties without exposing the secret sauce – again, critical for integration. There is also a notion of design hierarchy and sub-structures for improved schematic reuse and faster model changes.

    The resulting EDA flow with MEMS+ 6.0 looks like this, using Cadence as an example:


    Coventor has done two things with MEMS+ 6.0. They have lowered the traditional wall between the MEMS designer working in the microstructure domain and the CMOS designer working in a typical mixed-signal EDA flow. If we are going to create and build more IoT devices quickly, this is a big step – similar to the improvements in mixed-signal EDA tools just a few years ago.

    The second has bigger implications. CMOS foundries can now offer a level of mainstream MEMS fab capability, reliably modeled and compatible with their flow. MEMS purists will probably point out this won’t tackle every MEMS sensor type or precision requirements, and I don’t expect it to put the boutiques out of business. TSMC is probably in the “see, I told you this was happening” camp. I’d go back to something I’ve said before: we don’t have 2 cent MCUs for a reason. Never confuse technology with economic feasibility, especially for consumer space.

    This type of development could open up what I’ll call the sub-$1 integrated MEMS segment for now. One aspect to watch is who else adopts Coventor MEMS+ 6.0 for on what process. (From the announced partnership, I’m assuming we can count X-FAB in.) TSMC, Intel, and others are pushing the big wafer start and advanced node story for digital SoC design. Wearable and IoT parts may very well be built on a generation or two back – remember, ARM recently came out with a strong focus on TSMC 55ULP.

    It is good to see energy applied toward solving this for MEMS and the IoT. Full press release:

    Coventor Announces MEMS+ 6.0 Platform for MEMS/IoT Integration

    More articles from Don…

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    12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers

    12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers
    by Daniel Payne on 10-07-2015 at 7:00 am
    Categories: EDA, MunEDA

    My first job out of college was transistor-level circuit design of DRAMs at Intel, so I’ve continued to be fascinated with both the craft and science of designing, optimizing, verifying and debugging custom ICs. Last October I traveled to Munich, Germany to attend a two day user group meeting for engineers using tools from EDA vendor MunEDA. This year the MunEDA User Group Meeting is again a two day event held onOctober 27th and 28th in Munich Germany.


    Munich, Germany

    12 Reasons
    You probably need some reasons to convince your manager that this two day user group meeting will be worth your time, so here are 12 good reasons on why you should attend and learn more about relevant topics like:

    [LIST=1]

  • Custom circuit design migration and IP porting
  • Low-power optimization of custom IC designs
  • Advanced node designs (FinFET, FD-SOI)
  • Ultra high sigma and yield analysis and optimization
  • Memory design (SRAM, DRAM, Flash, FPGA, FTP, PCM)
  • Standard cell and I/O library design
  • Circuit and process modeling and model characterization
  • Reliability, aging and degradation based design
  • Circuit robustness verification and sign-off
  • Multiple topologies exploration
  • Smart power applications in general
  • High power designs (BCD technologies)

    These are the typical topics with presentations from actual tool users, and yes there’ll be a few presentations from MunEDA and I found them to be quite technical and detailed. Last year I watched presentations from companies like: SMIC, Lantiq, Novatek, STMicroelectronics, Infineon, Sapienza University in Rome, Altera, HLMC, Fraunhofer, University of Frankfurt and ARP Microsystems. Attendees receive a binder with all of the presentations, so if you like to take notes on the paper slides then it’s ideal. There was quite the range of process nodes talked about in the presentations from mature 180 nm AMS nodes to bleeding-edge FinFET nodes and everything in between.

    In addition to the technical aspects of a user group meeting, there was plenty of time to network and socialize. My favorite social event was the dinner on the first night at a historic beer hall where we had a private room, great food, beer for the drinkers (water for me), and time to get better acquainted with key people from MunEDA. This user group meeting is kind of unique because of how close you get to know other attendees.

    EDA Tools
    The product family from MunEDA is called WiCkeD and it’s a collection of EDA tools that allow a circuit designer to do five major tasks more easily and efficiently for custom IC designs:

    • Design Migration
    • Modelling
    • Verification and Optimization
    • Design Centering
    • Statistical Design Analysis


    Monte Carlo Analysis

    Summary
    User group meetings like this one are a great place to meet other circuit designers, learn something new, and even talk directly with the development team to learn how to get the best results of your MunEDAtools. Get more information and register here.

    Related

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    A FinFET BSIM-CMG model update from UC-Berkeley

    A FinFET BSIM-CMG model update from UC-Berkeley
    by Tom Dillinger on 10-06-2015 at 4:00 pm
    Categories: EDA

    Every designer relies upon an underlying “compact” device model for circuit simulations – these models are the lifeblood of the IC industry. Designers may not be aware that there is an organization that qualifies models – the Compact Model Coalition – which operates under the umbrella of the Si2 Consortium: http://www.si2.org/cmc_index.php .

    This model qualification is a key milestone, as it enables EDA vendors to adapt their circuit simulation tools accordingly, with the knowledge that foundries will provide corresponding technology process parameters for this model in their process design kit (PDK) releases. (Foundries may add a software layer on top of these underlying models, to provide additional functionality – e.g, TSMC’s Technology Model Interface, or TMI.)

    The initial FinFET process technology model endorsed by the CMC was the BSIM-CMG format in March, 2012, from the theoretical device modeling team at the University of California-Berkeley (CMG = Common Multi-Gate FinFET topology):http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG

    This site includes the current model documentation and source code.

    The existing model made some simplifying assumptions when solving field/charge distribution equations, most notably that the fin cross-sections were rectangular. The initial fins from the fabs were most definitely not rectangular:

    The BSIM modeling team at UC-B has developed an enhanced FinFET model format, to support an arbitrary fin profile, as described in their recent VLSI Technology Symposium technical paper:

    Khandelwal., S., et al, “New Industry Standard FinFET Compact Model for Future Technology Nodes”, 2015 Symposium on VLSI Technology, paper 6-4, pages T62-63.

    Rather than rectangular measures of fin height and thickness as inputs, the new field/charge model formulation uses the fin area, perimeter, and gate-to-channel capacitance to describe the (arbitrary) fin profile.

    This new model also incorporates additional features, in anticipation of new fin materials and/or different device construction (e.g., for the 5nm process node):

    • a pFET fin channel comprised of Germanium (requiring unique mobility modeling support)
    • an nFET fin channel comprised of a III-V semiconductor (with unique mobility modeling for InGaAs)
    • a new model formulation for the “density-of-states” energy levels and free carrier occupation
    • new model support for a gate-all-around (GAA, or “nanowire”) device topology

    Note that the electric field-dependent carrier mobility equations are significantly different for Germanium and (especially) III-V materials from Silicon.

    Also, at very small dimensions, the density of free (electron/hole) states in the channel at the (conduction/valence) band edges is limited – a unique carrier density versus energy calculation is required. The net result is the device currents are reduced.

    The expectations for this new model are better fitting accuracy to silicon, and better preparation for future process nodes, whether extending traditional fin technology with new materials, or the introduction of nanowires. The technical paper highlights examples of the improved fitting, both for 14nm FinFET’s and (early) GAA devices:

    Of course, model accuracy is important, but not at the expense of the circuit simulation runtime, as a significant percentage of the calculations are within device models. The UC-B team profiled model performance and has also significantly enhanced the throughput with this new model.

    The figure shows runtime comparisons between the current and proposed models for field/charge calculations, the temperature- and voltage-dependent equations, and the total execution time. (Runtime results for both bulk FinFET’s and FinFET’s fabricated on an SOI layer are shown.)

    The CMC qualification and EDA vendor simulation plus foundry PDK techfile support for this new, increased accuracy model is still in flight. Ideally, the impact of this transition to designers will be as straightforward as installing a new release. (It wouldn’t hurt to contact your CMC council representative to encourage a prompt review of this new model, as the performance improvements alone are compelling.)

    To be sure, there are still plenty of model development challenges ahead.

    The (mature) BSIM models for planar FET devices include current-modifying parameters representing layout-dependent and materials stress effects. The related layout widths and spacings around the modeled devices as included as base BSIM model parameters:

    http://www-device.eecs.berkeley.edu/bsim/Files/BSIM6/BSIM6.1.1/BSIM6.1.1_Technical_Manual.pdf (Chapters 16 and 19)

    FinFET’s add the complication of “N fins per layout finger”, where layout-dependent effects (LDE’s) may modulate the behavior of edge fins relative to internal fins.

    That level of maturity is not yet reflected in the BSIM-CMG model. For example, LDE’s must currently be supported as part of the foundry’s software algorithms, which then invoke the underlying BSIM-CMG code.

    Kudos to the BSIM-CMG model development team for their recent breakthrough!

    Look for ongoing enhancements from the team to this new “arbitrary fin profile” model. And, look for announcements from the CMC, both for their endorsement of this latest model format, and approval of a (relatively new) initiative for a standard application programming interface for the foundry’s software layer that invokes the BSIM-CMG model.

    -chipguy