As I sat down in the SEMI Arizona Chapter breakfast meeting a few weeks ago, a moment of semiconductor history flew right before my eyes before the IoT sessions started.
We were seated in the cafeteria of Freescale Building 94 on Elliot Road in Tempe, a place I’d been many times before, except this time may have been the last. NXP is consolidating facilities in Arizona early in 2016 Continue reading “A moment of IoT silence before we disrupt”
An interesting thing happened during the driving tour of the GlobalFoundries Fab 8 in Malta, NY. We happened by an old structure with quite a bit of history. As it turns out, the “Malta Test Station”, a former US Army fuel and explosives testing facility, was the actual birthplace of the United States’ Space & Missile programs. In fact, Hermes Road, one of the main access roads, is named for the Hermes Missile Program circa 1944.
According to Wikipedia, after World War II we “borrowed” some German V-2 missile parts and the engineering team that invented them including Wernher von Braun. Wernher worked for the U.S. Army on ballistic missiles, then NASA where he was director of the Marshall Space Flight Center, and was later dubbed the “greatest rocket scientist in history”. Check out this guy’s resume:
[TABLE] cellspacing=”3″ style=”width: 352px”
|-
| Born
| Wernher Magnus Maximilian, Freiherr von Braun
March 23, 1912
Wirsitz, Posen Province, Prussia, Germany
(now Wyrzysk, Piła County, Poland)
|-
| Died
| June 16, 1977 (aged 65)
Alexandria, Virginia, U.S.
|-
| Resting place
| Alexandria
|-
| Nationality
| German/American
|-
| Alma mater
| Technical University of Berlin
|-
| Occupation
| Rocket engineer and designer, aerospace project manager
|-
| Spouse(s)
| Maria Luise von Quistorp (m. 1947–77)
|-
| Children
| Iris Careen von Braun
Margrit Cecile von Braun
Peter Constantine von Braun
|-
| Parent(s)
| Magnus von Braun (1877–1972)
Emmy von Quistorp (1886–1959)
|-
| Awards
| Elliott Cresson Medal (1962)
Wilhelm Exner Medal (1969)[SUP][1][/SUP]
National Medal of Science (1975)
|-
| colspan=”2″ | Military career
|-
| Allegiance
| Nazi Germany
|-
| Service/branch
| SS
|-
| Years of service
| 1937–1945
|-
| Rank
| Sturmbannführer, SS
|-
| Battles/wars
| World War II
|-
| Awards
| Knights Cross of the War Merit Cross (1944)
War Merit Cross, First Class with Swords (1943)
|-
| Other work
| Rocket engineer, NASA, Chief Architect of the Saturn V rocket of the Apollo manned moon missions, engineering program manager
|-
Back to the Fab 8 tour, Scott Jones and I got the VIP treatment. Scott not only has worked in fabs, he has built them, so he was my translator and chief question asker. Scott will be writing about this trip as well so you may want to read his observations and opinions here: “Global Foundries Visit – Part 1 – It’s All About Execution”.
The clean room tour is always interesting. Since I have been through about a dozen of these around the world I have quite a few reference points and can tell how modern a facility it is, where they are in the production cycle, and how busy they are. Contrary to popular belief, the less people working inside a clean room the better and I do count people. I also look at the wafer transport system, how modern it is, how fast it goes, and how many wafers are flying around. They never talk about who the wafers belong to but in this case I already knew (AMD, both CPU and GPU, GPUs first). There are no secrets in Silicon Valley… Needless to say Malta did not disappoint in all categories above, not even close.
GLOBALFOUNDRIES Achieves 14nm FinFET Technology Success for Next-Generation AMD Products
“FinFET technology is expected to play a critical foundational role across multiple AMD product lines, starting in 2016,” said Mark Papermaster, senior vice president and chief technology officer at AMD. “GLOBALFOUNDRIES has worked tirelessly to reach this key milestone on its 14LPP process. We look forward to GLOBALFOUNDRIES’ continued progress towards full production readiness and expect to leverage the advanced 14LPP process technology across a broad set of our CPU, APU, and GPU products.”
After Malta, Scott and I drove down to Burlington for a day at Fab 9 with presentations about the history of the fab, the RF and ASIC groups. I will wait for Scott to post his blog then add my two cents.
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Fabless companies and the need for foundries
The success of fabless semiconductor companies is well documented with companies such as Qualcomm, Broadcom, MediaTek, AMD, Avago and others selling semiconductors made using the fabless model (see Fabless: The Transformation of the Semiconductor Industry by Daniel Nenni and Paul McLellan for more information). Fabless semiconductor companies are growing faster than the overall semiconductor industry and are becoming more important with each passing year. Mobile devices such as cell phones and tablets are particularly dependent on the fabless semiconductor industry. There are also companies such as Apple and Cisco that produce products that are dependent on semiconductors they design and manufacture using the fabless model. Of course the fabless model can only exist if foundries are available to produce the products the fabless companies design.
In the foundry industry today there are really only four companies that are driving to be first producers of the latest technologies, TSMC, GlobalFoundries, Samsung and Intel. The first four are the only foundries ramping 14nm class processes today and of them only TSMC and GlobalFoundries are pure play foundries. Companies such as UMC and SMIC are now followers with 14nm plans that are not yet implemented. All other things being equal, pure play foundries are the preferred solution because they are focused on foundry, it is their core business. The IDM’s such as Samsung or Intel that offer foundry have other corporate priorities and may even compete with their customers.
The fabless industry is well aware of the dangers of being sole sourced. This was really driven home as recently as the 28nm node where TSMC was the only viable supplier for over a year. It is critically important to the fabless industry to have two or more sources of leading edge technology available and as previously discussed they would ideally be pure play foundries.
In my opinion the preceding discussion makes the case that GlobalFoundries succeeding as a foundry is of great importance to the fabless semiconductor industry!
A Brief History of Global Foundries
Advanced Micro Devices (AMD) is a manufacturer of Microprocessors for Personal Computers (PCs) (among other products). For many years AMD was an Integrated Device Manufacturer (IDM) manufacturing microprocessors in their own fabs and locked in a battle with Intel for success in the PC market place. Intel consistently had larger market share, greater profitability and ultimately greater manufacturing scale and ability to invest in new technologies and facilities. Over time AMD’s cash position eroded to the point where they could no longer afford to make the investments required to stay on the leading edge for fab technology and risked falling behind Intel in performance further eroding their market share. In 2009 AMD reached an agreement to divest their fabs to Advanced Technology Investment Corporation (ATIC) a subsidiary of the Emirate of Abu Dhabi and Global Foundries (GF) was born.
GF started with two 300mm wafer fabs in Dresden Germany with a combined capacity of approximately 45,000 wafers per month and an empty site in Malta, New York where a new 300mm fab was planned. With ATIC as a backer, GF had the financial resources to update and expand Dresden and to break ground in Malta on a new fab. GF also received contracts to supply AMD as part of the deal. From AMD’s perspective, they got a manufacturing source for their microprocessors and no longer had to make the enormous investments to build and upgrade state-of-the art wafer fabs.
In 2010 ATIC followed up their initial acquisition of AMD’s fabs by acquiring Charted Semiconductor. Chartered was a pure play foundry headquartered in Singapore and at the time of the acquisition was the third largest foundry in the world on a revenue basis behind TSMC and UMC. Chartered had always struggled with profitability trailing their larger rivals and the acquisition offered Chartered greater scale and financial resources.
Finally in 2015 GF acquired the microelectronics business of IBM. IBM microelectronics adds additional fabs, a huge portfolio of patents and a large and highly experienced development team. IBM had a long history of leadership in semiconductor technology development having invented scaling, the 1T DRAM cell (used in all DRAM today), developed CMP and copper interconnect and more.
GF now has four – 300mm fabs around the world, Fab 1 (former AMD site) in Dresden producing 45nm to 28nm technologies (22nm is in development) with 60,000 wafers per month (wpm) capacity, Fab 7 (former Chartered site) in Singapore producing 180nm to 40nm technology with 68,000 wpm capacity (they also have several 200mm fabs in Singapore), Fab 8 (greenfield GF fab) in Malta, NY producing 28nm and 14nm, and developing 10nm and 7nm technology with 60,000 wpm capacity and Fab 10 (former IBM site) in East Fishkill, NY producing 90nm to 14nm technology with 14,000 wpm capacity. The IBM acquisition also added a 200mm fab in Burlington, VT producing 180nm to 130nm RF wafers (more about this in part 2).
To-date GF has successfully brought up 28nm technology in Dresden and in Malta NY but they were later than TSMC. At 14nm GF was developing their own 14nm technology but they abandoned the development effort and licensed 14nm from Samsung. As an outside observer the impression I have of GF is they have a lot of worldwide scale and resources but that they have struggled with execution.
When Daniel Nenni offered me the opportunity to visit the GF Malta and Burlington sites, tour the sites and meet key GF executives for briefings on the company I jumped at the chance to go. In the balance of this article I will discuss our visit to the Malta NY site; in a following blog I will discuss the Burlington VT visit.
Malta Fab 8 Visit
Fab 8 is GF’s flagship site and the home of their most advanced technology development efforts.
Site Tour
Our visit began with a driving tour of the Fab 8 site. There is currently a massive cluster of buildings on the site. Looking at the buildings from the front there are two large administration buildings, behind the administration building to the left is fab 8 – phase 1 and phase 2. Phase 1 is a 200,000 square foot cleanroom with a capacity of approximately 40,000 wpm and phase 2 is a 100,000 square foot cleanroom. The combined phase 1 and phase 2 cleanrooms are equivalent to approximately six US football fields in area! Behind the right side of the administration buildings is another 100,000 square feet of cleanroom space originally used as a Technology Development Center but now renamed phase 3. Phase 1 is currently fully fitted-out with tools and phase 2 and 3 are being fitted-out. Current capacity is stated as approximately 60,000 wpm, presumably when phase 2 and 3 are completely fitted-out that number may be higher depending on the complexity of the technologies being run.
The Malta site also has space for two more fabs similar in size to the existing fab providing the potential to ramp the total site up to approximately 180,000 wpm.
The site also has some interesting pre GF history in rocket development with a lot of old buildings and test structures still in place.
The overall site and buildings are simply massive. The employee parking lot appeared to be full and there was a large contractor area that was also full and busy.
Meeting with Gary Patton
Gary Patton ran development for IBM microelectronics for eight years prior to GF acquiring IBM microelectronics. Gary is now the Chief Technical Officer for GF and responsible for all of their technology development. I asked Gary is being CTO at GF required a change in mind set. I suggested that at IBM development was likely performance first and cost a distant second but Gary disagreed sighting his work on the bulk technologies for the common platform. He said he had a lot of experience with developing for cost and performance per watt. His job now is to accelerate technology development at GF and make sure there aren’t silos. Gary has established a process council with members from the sites around the world to promote cooperative technology development across the company. One of the things that were clear early on in talking to Gary was a focus on execution, “Say what you do and do what you say to establish credibility”. Gary noted that GF was late on 14nm and late starting on 10nm, at 7nm they started early and they are really pushing. The 7nm technology can be run using multi-pattering but EUV may offer some advantages if it is ready.
Gary also noted that even with the acquisition of IBM Microelectronics by GF, IBM is still involved in semiconductor R&D. IBM retained Yorktown Heights and the Almaden Research Center and is involved in Albany Nanotech. R&D developed at those locations then feeds into Malta where the development team bolstered by the influx of IBM researchers is focused on 10nm and 7nm development. The IBM acquisition brought in a lot of experienced researchers to Malta and there is now a dedicated 10nm and 7nm development team whereas in the past development was done by manufacturing. From the IBM perspective the deal has freed IBM from having to invest in low volume production. GF will provide customized processes to IBM for their relatively low volume server requirements. Former IBM operations such as RF that was constrained to Burlington and ASIC that was constrained on IP are now unconstrained (more on that in part 2).
The IBM 14nm technology will stay in East Fishkill (Fab 10 now). 14LPE acquired from Samsung is run in Malta plus 14LPP is built off of the 14LPE base and will also run in Malta. 14LPP is the same design rules as 14LPE and offers a 10% to 14% performance improvement over 14LPE. When 28nm was brought up in Malta there was no base to work off of, now the 14nm ramp is leveraging the 28nm experience. Both 14LPE (E for early) and 14LPP (P for performance) are ramping in Malta and have “world class yields”. 10nm and 7nm development is all being done in Malta.
I asked Gary for his view of FDSOI versus FinFETs. He said he didn’t see it as “versus”. FDSOI body bias is a great capability but FinFETs are better for high-end smart phones and performance and FDSOI is better for low power. Throughout the interview Gary was very poised and confident. He was very interesting to talk to and I would have been happy to have had more time for the discussions.
Gary’s Presentation
Meeting with Tom Caulfield
Tom is the senior VP responsible for the Fab 8 site. Tom noted that Fab 8 was originally going to be an AMD fab. Phase 1, 2, and TDC (now phase 3) are now close to 400,000 square feet. Development on the site is now done as a development “corridor” inside the manufacturing “corridor”.
As was covered above the 14nm technology was licensed from Samsung, the transfer was done as a copy smart. Some recipes were transferred one to one, some had to be modified because the tools were different. There were approximately twenty Samsung engineers on site and morning and afternoon conference calls. During the transfer they were always within one quarter of where Samsung’s S1 fab was and typically within 2 months. By buying Samsung’s process Samsung and GF basically split the cost of the development. The Samsung and GF 14nm processes are PDK compatible.
At 10nm/7nm the technology will be IBM driven. He thinks 7nm options are so limited that industry wide the processes will be similar. Current optical technology capabilities have defined how 7nm will be done. The usage of 14nm and even 10nm is driven by performance, at 7nm the driver will be economics. 7nm as defined today is economical even if done optically; EUV will be an opportunistic adder.
We talked a bit about the pyramid of systems companies supported by semiconductor companies supported by materials and equipment companies. Equipment companies used to just build tools but now they have to provide processes. They even supply some modules but individual steps are better. Tom talked about how the Eco system has to have a value proposition at each level or the model collapses.
In terms of why GF acquired IBM microelectronics:
[LIST=1]
GF now has the “Malbany” corridor, Malta to Albany in about 29 minutes. The scale they are building is reaching the point that suppliers are setting up locally. For example, bulk hydrogen peroxide transportation is a big part of the cost coming from Texas, but now a hydrogen peroxide plant is being set up near Malta.
Tom also noted that 28nm launched at Fab 8 in June of 2014 established manufacturing so that infrastructure was in place for 14nm. GF currently has 14LPE in production on one part and 14LPP has two parts ramping production now and they will exit Q1-2016 with a least six parts.
We also talked about 20nm/16nm and the possibility that 10nm/7nm will be similar. Daniel has noted that 20nm and 16nm shared the same equipment set and 20nm ended up being a very short lived node. Daniel thinks 10nm may also be a short lived node with a quick shift to 7nm using the same equipment. Tom noted that at 20nm foundries didn’t make their R&D investment back and 10nm could be similar. 20nm succeeded at TSMC because Apple designed down to it and paid for the technology. Others who didn’t design down to it weren’t successful because the power performance wasn’t there.
I asked Tom about FDSOI versus FinFET and got my favorite quote of the trip. “FDSOI and FinFET competition is like a screwdriver and hammer fighting, they are different tools”. FDSOI is Internet of Things (IOT) and FinFET is big data. Earlier in the session we had discussed how IOT doesn’t really get interesting until you load the data up into a server and start running expert systems on it. They are complimentary pieces.
As a final observation Tom said you put values in place to judge behaviors. GF is focused on execution and measuring against that. They have met everything they said they would at 14nm.
Throughout our interview Tom was enthusiastic and energetic about GF and where they are going. I would also say that everything I heard from Gary and Tom matched up very well especially on the need for execution.
In summary at Fab 8 in Malta GF seems to have gotten the message that they have to execute and they are focused on making it happen! I came away both impressed and optimistic for the future of GF.
In the next installment I will discuss Burlington. Going in I expected Malta to be the highlight of the trip but Burlington held it own and has it’s own really interesting pieces to add to the GF puzzle.
An indecision is actually a very bad decision. It is an implicit decision for the status quo. It is worse than an explicit decision regardless of how bad that decision turns out to be. In my experience, our indecisiveness is caused by various reasons involving trade-offs.
Continue reading “What Makes Us Indecisive?”
Respected Gordon Moore has given the real computing power to the world and Respected Stephen Hawking’s work from past many years has given the reality of physics and mathematics to the universe. We can imagine the shrinking and intelligence in computing due to the real evolution of semiconductor technology. The process node has shrunk from 250 nanometer (Year 1997) to 14 nanometer (Year 2014). And continues to shrink but have limitations due to fundamental laws of Physics.
Continue reading “Moore’s Law Linear Approximation and Mathematical Analysis!”
(Two Star Wars™ allusions in one title – eat your heart out George Lucas.) Most of us are comfortable with the idea that you design more or less whatever you want in RTL and let the synthesis tool pick logic gates to implement that functionality. Sure it may need a little guidance here and there but otherwise synthesis is more or less a hands-free operation (subject to meeting timing). Not so for microprocessor designers who until recently, thanks to demands of very tight margins, had to manage sequential stages using special large macros more often than not, even while they relied on synthesis for other logic.
Now it seems FinFET technologies are driving us all back to large macros. The problem is that, in several cases for a variety of reasons to do with the arcana of FinFET technology, an aggregate of small cells placed and routed using standard methods often has significantly lower performance and higher power than a custom-crafted macro (cue old designers muttering “Well – duh”). Some opportunities to optimize are large bit count register trays, pulse latches and retention flops. There are even valuable performance and power improvements possible in folding larger logic gates into registers.
As always, there’s a challenge. Actually two challenges, both in characterization. Large macros simulate exponentially slower than smaller macros because run-time dramatically increases with number of nodes. Worse yet, Monte Carlo Spice, required to deal with acute on-chip variation in FinFETS, massively amplifies run-time on these large circuits. You’re caught between an unavoidable need to use these macros to meet power and performance goals and impossibly long times to characterize with sufficient accuracy to be able to trust that characterization in chip-level analysis.
Maybe you could sample a sparser space in Monte Carlo and apply margins to handle whatever you might have missed? It’s pretty clear this approach is no longer viable, especially if you are running at low voltages (0.6V) where the difference between early and late arrivals can be as much as 100%. And we all know (or should know) about the evils of over margining, perhaps resulting in a problem in a device that came out in spec from one foundry but much higher power (and lower battery life) from another.
So you have to do comprehensive variance analysis and you know that any standard approach is impossibly slow. What you need is a way to simulate large circuits with Spice-level accuracy but much faster, and a better way than Monte Carlo to deal with mapping the effect of variations on many paths into the characterization. Macro FX™, based on the CLKDA FX simulator, combines solutions to both problems. FX is an intrinsically fast Spice accurate simulator (“check” on the first problem), but what I find most interesting is how it deals with the second problem. To elaborate a little more on that issue, no matter how fast any one Spice simulation runs, Monte Carlo techniques multiply that time by hundreds or thousands in order to cover a sufficiently representative sample space. Whatever gain you may have in simulation speed, you lose that and much more in having to run many, many simulations.
FX on the other hand solves for sensitivities based on variances as it runs simulation, which is a lot more efficient than running simulations many times over. The outcome is a parameterization of variances within the characterization data. This can be output as AOCV, LVF, POCV or SOCV tables, or can be used directly in-line in PathFX™ to get the ultimate in signoff accuracy.
You can learn more about how FinFETs are driving a need for larger macros, and how MacroFX helps HERE. To learn more about the effects of variance on timing, especially at low voltages, click HERE.
May the FX be with you.
For the fourth consecutive year, China’s semiconductor consumption growth far exceeded worldwide market growth. At the end of 2014, the country had a record 56.6% of the global semiconductor consumption market.
China’s semiconductor consumption grew by 12.6% in 2014, exceeding the worldwide chip market growth of 9.8%. To put that in a broader perspective, over the past 11 years China’s semiconductor consumption has grown at an 18.8% compounded annual growth rate (CAGR), compared with a 6.6% CAGR for total worldwide consumption.
At the end of 2014, China had three semiconductor companies with US$1 billion or more in annual revenue. Collectively, these companies have experienced an 18.5% CAGR over the past 11 years. In the future, we expect to see more Chinese semiconductor companies break the billion-dollar revenue mark either organically or through mergers.
Even with Chinese semiconductor companies growing in number and size, non-Chinese global semiconductor companies remain the dominant semiconductor suppliers to China. This contributed to China’s integrated circuit (IC) consumption/production gap of US$120 billion at the end of 2014—US$12 billion wider than at the end of 2013. The growing production/consumption gap and the strategic importance of the industry will continue to favorably influence the policies of the Chinese government as far as the semiconductor industry is concerned.
So what areas contributed to China’s chip consumption during 2014? We saw heavier concentrations in the data processing (computing) and communications applications sectors, and slightly more concentration in the consumer sector versus the worldwide market. Contrasting with the worldwide market, however, China’s semiconductor consumption was less concentrated in the automotive sector, and noticeably less concentrated in the industrial/medical/other, and military/aerospace sectors.
China’s IC consumption over the past decade has grown by more than US$134 billion, compared with just US$99 billion for the worldwide market. The country’s growth in this area has come at the expense of other regions’ IC markets, but we’re also seeing China’s rate of IC consumption market growth gradually moving closer to the worldwide rate. China’s IC consumption increased by more than US$20 billion in 2014, which was US$6 billion less than the worldwide market.
China’s O-S-D (optoelectronics-sensor-discrete) segment tells a similar story, with consumption growing 8.1% during 2o14 to reach a new peak of US$34.3 billion. Sensors are fundamental to the Internet of Things (IoT), and will help drive an increase in semiconductor industry billings. But for the first time in four years, China’s O-S-D increase was slightly less than the worldwide market increase, meaning China’s O-S-D market share remained relatively flat in 2014, at 56%.
When we look at China’s pragmatic government policies in this area, and combine them with a culture of entrepreneurship and a vast pool of engineering talent, we believe the Chinese semiconductor industry should continue to gain strength over the rest of the decade.
I’d love to hear your opinion in the comments. How do you see China’s semiconductor industry taking shape over the next several years? Are there additional factors you see influencing the space?
Also, I encourage you to stay informed in the coming months as we explore this area more. You can register for updates on our microsite covering China’s impact on the semiconductor industry.
Raman Chitkara leads the global technology practice at PwC. Read his full biography here.
Don’t forget to follow SemiWiki on LinkedIn HERE…Thank you for your support!
When I first moved to Oregon in 1978 the largest industry was forestry, but then the endangered Spotted Owl was found and that put an end to many forestry companies and decimated the economy of many rural cities. Strangely enough it turns out that the Spotted Owl was found in great numbers across multiple states, so it never should’ve been placed on the endangered species list in the first place. Fast forward to 2015 and the number one Oregon industry is semiconductors, with Intel at the top revenue position. Many Californians have made the move to Oregon because housing is affordable in the Silicon Forest, the air is clean, and our Pinot Noir wines are world-class.
SEMIis a global industry association and they just hosted an event in Wilsonville (aka Mentor Graphics) with over 150 techies in attendance, the theme was Moore’s Law and I attended after a short 7 mile drive from Tualatin.
Mentor Graphics
Wally Rhines waxed energetically about extending semiconductor cost reduction for another 20 years, although even Gordon Moore is quoted as saying that, “No exponential is forever”. Here’s the log-log chart defining the learning curve where the X-Axis is cumulative units produced and the Y-axis is cost per unit:
Rhines showed historical data that followed this exact curve for:
In general Wally has seen that EDA revenue is about 2% of total Semiconductor revenues over the past 20 years now.
The costs per wafer show about a 20% increase per new node, but at the 20nm node the costs were more expensive than 28nm per transistor. At 14nm the cost per transistor still too high because we’ve missed the commercialization of EUV sources. In spite of all that, he expects that we’ll have continued progress per Moore’s Law for another decade.
ASML
Chris Spence started out by humorously apologizing for EUV being late to market, then presented an info-packed slide on 30 years of Litho progress.
EUV is still beset by slow throughput as measured in Wafers Per Hour (WPH) and high costs. ASML’s 3rd generation EUV tool, the NXE 3350B, can product up to 125 WPH, it’s progress but it isn’t easy
Defects can be related to IC layout patterns, not defect particles, so OPC can predict those patterns with a tool like Tachyon. Yes, multi-patterning allows us to reach lower than 10nm, however it will be pricey.
INTEL
Our speaker from the supply chain side was David Bloss, and he was quick to emphasize that, “Moore’s law is thriving at Intel”. The most controversial thing that David shared was that Intel has found a way to make cheaper transistors at 22nm and smaller nodes, contrary to what the rest of the industry seems to be saying. Their 7nm node is about a decade out, so that means 2025.
This slide is from Bill Holt’s investor meeting presentation of November 2014, one year ago. Intel was pleased that their suppliers are helping make Moore’s Law continue on. As for 450mm wafers we can expect that Intel will wait for the industry to drive demand.
IBM
From the R&D side we had Dr. Vamsi Paruchuri talking about the materials and process technology for advanced CMOS nodes. Although I don’t have permission to show you any of the slides that Vamsi presented, I can show you the IBM 7nm test chip that came out of fab in July, designed with silicon germanium for FinFET transistors, using EUV to get the small geometries.
Credit: Darryl Bautista/IBM
I found it interest that at the 7nm node they needed to use SiGe channels on FinFET for lower power and faster switching. Gate lengths are 15nm in 7nm technology, transistor width is 8nm minimum, and the height is 20nm.
Other interesting research technologies include Si Nanowire, Carbon Electronics (Carbon Nanotubes – optics and semi together), III IV FinFet, Stacked Nanowires, Stacked Nanosheet, and Gate All Around FinFET (GAAFET).
ASE
Representing the package and assembly business we heard from John Hunt. The hot acronym to remember is for Wafer Level Chip Scale Package, WLCSP.
Popular consumer devices like the Apple Watch and iPhone will be using technology like WLCSP to enable extremely thin products. TSMC will build the Apple A10 with fanout packaging technology. For IoT devices you can expect to see Fan Out SiP (System in Package).
Yole Development
Dave Towne showed us how more than Moore is being enabled by advanced packaging. Yole Development has standard reports for sale, custom research reports, and they know the market trends. On Fan Out Wafer Level Packaging (FOWLP) they are predicting this market segment to grow from $174M this year to $790M next year when the A10 is announced from Apple and using TSMC for both the chip and packaging technology. TSMC calls this Integrated Fan Out (InFO).
Take a quick look at how 2D versus 3D packaging features compare:
Source: Yole Development
Mobile phone companies like Apple and Samsung are routinely using Wafer Level Packaging to achieve the thinnest integrations. CMOS Image sensors are a big user of 3D packaging, and that trend continues on strongly.
Summary
It was a pleasant surprise to be exposed to such diverse presentations from SEMI members in one setting, because I normally have my EDA blinders on and get too focused on software-only solutions to semiconductor design challenges. It was clear that all of these companies must collaborate closely in order to exploit everything that silicon has to offer us. For now, Moore’s Law continues and the only question is, “At what cost per transistor?”
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Of all the live events I attend ARM TechCon is one of my favorites. The keynotes are always very good but the real meat of the conference is who attends because that is who the content is specifically developed for:
You probably have seen many times this graphic showing that the number of IP blocks has exploded, going from a few dozens in SoC designed in 65 nm to 120 if not more for last generation SoC targeting 16FF or 10FF. This graphic is very good at synthesizing the raw IP count, but it doesn’t tell you about another strong trend: more agents are participating in coherency. We may turn this another way: complex SoC designs are moving from homogeneous zone of comfort to heterogeneous, and this reality has started as soon as designs have moved to single core (single cache level) to TWO cores supporting cache memory. Looking at the picture below, you realize that certain designs may integrate several very complex multi-CPU (and GPU) clusters, architectured around three cache levels. Cache coherency is becoming a key issue, when integrating a Network-on-Chip, better to make sure that the NoC is cache coherent!
NetSpeed has initially built Gemini NoC IP to explicitly support cache-coherent designs, the new version, Gemini 2.0, has been developed to support SoC requiring coherency across multiple IP clusters. Customers are using NoCStudio to create ARM compliant interconnects using AMBA-compliant, ACE and ACE-lite, as well as coherency details. Gemini 2.0 improves configurability, adding a last level cache option and generates synthesizable RTL. Gemini 2.0 is an automated coherent NoC generator and the design team will take benefit of the tool, especially when being under the pressure of an aggressive schedule.
A new feature has been added into Gemini 2.0, Pegasus cache. In fact, Pegasus is a configurable IP and the designer will determine cache capacity, associativity, banking, internal power gating and allocation policies for each Pegasus, as a SoC can include several Pegasus modules. For example, the number of outstanding cache misses and other cache configuration features are configurable.
Using NetSpeed coherent NoC architecture allows improving cache utilization by controlling address ranges serviced by each cache, or defining which IP blocks can access the cache. A coherent cache only allows coherent access. What about the non-coherent traffic? It goes directly to memory.
Pegasus only supports one layer of coherency, and if different IP blocks including the same Pegasus cache, they will be non-coherent to each other. NetSpeed NocStudio enables cache hierarchy customization. Gemini 2.0 architecture is flexible enough to adapt to different scenario. Clearly explained on the above picture, different clusters made of two CPU with cache can be implemented in a variety of manners. One cluster will require the two CPU to share the same Cache Coherency Controller (CCC), the same Last Level Cache and the same (external) memory. Another cluster will be architecture with CPU still sharing the same CCC, but one CPU directly accessing on-chip RAM when the other will access external memory through Last Level cache…
Such greater flexibility explains why customers developing complexes coherent systems would greatly benefit from Gemini 2.0 to accelerate Time-To-Market. Architects who need a scalable, high-performance, correct-by-construction SoC interconnect should evaluate NetSpeed’s technology, especially if the design requires cache coherence.
