ARM’s mbed operating system is winning attention in the highly fragmented embedded software space by promising a solid software foundation for interoperable hardware and thus scale the Internet of Things (IoT) designs by narrowing the development time.
Continue reading “mbed Evaluation Boards Showcase Focus on IoT Software, Connectivity”
Academia and TCAD Grow Closer
On my first trip to Austria for EDA business I traveled by car from Germany, and I couldn’t wait to see how fast we would travel on the fabled Autobahn. Oddly enough it was summertime and the Autobahn was filled with vacationing families driving cars with shiny, aluminum campers in tow, so our car only traveled about 60 mph, nothing like the unlimited speeds that I’ve seen on YouTube. Located in Vienna, Austria is the TU Wien Institute for Microelectronics, a place where researchers focus on defining models, write software and create new tools for the simulation of both semiconductor devices and the technology processing steps (aka TCAD). To actually test out their ideas in silicon they partner with fabs and IDMs in Europe and around the globe. TU Wien has ongoing research in these five areas:
- Device Simulation
- Process Simulation
- High Performance Computing
- Meshing
- Very Large Scale Integration
The folks at TU Wien are now partnering with Silvacoto create the new Christian Doppler Laboratory (CDL) for High Performance TCAD, along with some financing provided by the Austrian Ministry of Science, Research and Economics. The CDL opened up just last month on October 5th and there’s a group photo taken at the official opening below.
I’m not certain how many American or other Universities are partnering with TCAD vendors, but the concept certainly makes a lot of sense because of how critical it is to design and optimize any new process technology prior to actual fabrication. Dr. Josef Weinbub will be heading up the new CDL, and he even has his own web site. He has been doing TCAD research since 2010, and has won an award from the NVIDIA GPU Research Center. I’m wondering if his involvement with GPUs may indicate that Silvaco will port a TCAD tool to work with GPUs, speeding up the time required for simulations.
The research team at CDL will be using Silvaco TCAD tools, and the close collaboration will certainly improve the features in these tools. Silvaco also has research sites in Grenoble, France and Cambridge UK. I often make the mistake of thinking that smaller EDA vendors are located in a single building, but with Silvaco they have people in North America, Europe, Japan and Asia. This partnership between academia and Silvaco looks like a good deal between science and business.
Here’s a list of TCAD tools that Silvaco offers to give you an idea of the breadth:
- 3D Device Simulator (Victory Device)
- Layout-driven 3D Process Simulator (Victory Process)
- Virtual Wafer Fab (VWF)
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Advances in DDR IP Solution for High-Performance SoCs
In this era of high-performance, low-power, and low-cost devices coming up at an unprecedented scale, the SoCs can never attain the ultimate in performance; always there is scope for improvement. Several methods including innovative technology, multi-processor architecture, memory, data traffic management for low latency, and software have been explored with great success in enhancing SoC performance. Continue reading “Advances in DDR IP Solution for High-Performance SoCs”
Samsung Versus Intel at 14nm
Daniel Nenni recently blogged about Intel’s claims of industry leading process density that were made at their analysts meeting. It isn’t clear to me why Intel makes this such a big focus at the analysts meetings, they really don’t compete with the foundries much but this seems to be a big deal to them. I thought it would be interesting to take a detailed look at Intel’s 14nm process and contrast it to Samsung’s 14nm process and put some of these claims in perspective. I picked Samsung because Samsung has the densest 14nm foundry process.
Dan’s blog is available here.
With 14nm parts now out in the market from both Intel and Samsung a lot is known about both processes, in fact I believe I have a good detailed understanding of both processes. In this article I am going to focus on the back end of line (BEOL) because I believe it really illustrates the differences in approaches.
Samsung 14LPE process
Samsung’s 14LPE process is a foundry process and as such it has to accommodate a wide variety of customer needs. The process offers 4 levels of minimum pitch metal (64nm). The minimum pitch metal layers at 64nm are below the single patterning limit of ~80nm and therefore require multi-patterning. Samsung has chosen to use litho-etch-litho-etch (LE2) where the pattern is broken up into two masks that are exposed and etched separately. There are advantage and disadvantages to LE2 as a multi patterning approach versus other approaches such a self-aligned double pattering (SADP). The big advantage to LE2 is that the pattern produced can be 2D with metal runs in both the X and Y directions; the disadvantage is that the achievable minimum pitch isn’t as small as it is with SADP. For a foundry process flexibility in metal routing is very important and trading off some pitch for routing flexibility makes sense.
The Samsung 14LPE process also employs self-aligned vias. Basically the LE2 metal pattern is done first and memorized into a hard mask and then the via pattern is overlaid. The via pitches are also relaxed and this allows the vias to be single patterned.
Intel P1272 process
Intel develops microprocessor processes first and then adapts the processes for foundry later (typically around a year later). Because Intel controls both the process and the design for their microprocessors it allows them to impose much stricter design rules than a foundry can typically require and the P1272 process is an excellent example of this. For the first four metal layers Intel has used SADP with block masks. SADP creates a mandrel and then spacers on the mandrel edges doubling the mask pitch. SADP can in theory double an 80nm single exposure mask to a 40nm pitch. The drawback is the 40nm pitch is only achieved in one direction basically creating parallel lines and spaces in that direction. You get tightly spaced lines in the X direction but no lines in the Y direction. The lines also have to be cut or in the case of interconnect blocked by one or more additional masks.
By using SADP Intel has achieved pitches of 56nm, 70nm, 52nm and 56nm for the first four metal layers. These are however 1D gridded lines and spaces allowing much less metal routing flexibility. In fact to some extent what was a single 2D metal layer has to be broken up into two 1D metal layers. This has resulted in a significant increase in the number of metal layers required for the 14nm process. Intel’s 130nm, 90nm, 65nm, 45nm, 32nm and 22nm processes had 6, 7, 8, 9, 9, and 9 metal layers respectively, at 14nm the metals layers jumped to 13!
The Intel P1272 process also utilizes self-aligned via so the critical via are single patterned.
Conclusions
After reading this you may wonder which BEOL is better and the answer is it depends. For Intel’s microprocessor designs where they can impose very strict design rules Intel has undoubtedly done an exhaustive analysis to decide on their process. For Intel, foundry is a distant second to microprocessors in priority and I would suspect the process decisions were heavily weighted towards optimizing it for microprocessors. For Samsung the 14LPE process is a foundry process and needs to support more flexible metal routing. Intel achieves a tighter pitch on individual metal layers but depending on the routing requirements this may or may not achieve a denser design or may require additional metal levels and therefore higher process costs.
See also Apple versus Zebras
Internet of Things in 2016
2015 was a big year for the Internet of Things (IoT). In our minds, it seems to have been the year nearly all big companies developed an IoT strategy. At the risk of sounding cliche, you could say IoT became mainstream in 2015.
Continue reading “Internet of Things in 2016”
5 ways FPGA-based prototyping shrinks design time
Engineers are trained to think linearly, along the lines of we started here, then we did this, and that, and this other stuff, and here is where we ended up. If you’ve ever presented in an internal review meeting, sales conference, or a TED-like event, you know that is a dangerous strategy in winning friends and influencing people. Continue reading “5 ways FPGA-based prototyping shrinks design time”
The Fog Begins to Lift on 5G Cellular
5G mobile communication is widely forecasted to be a market reality seven to ten years from now. As envisioned by the International Telecommunications Union Radiocommunications sector (ITU-R), in their next generation International Mobile Telecommunication or IMT-2020 documents, 5G comprises three top-level goals: enhanced mobile broadband; massive machine type communications; and ultra-reliability and low latency communications. There are eight technical criteria which underpin these goals: peak data rate; user-experienced data rate; area traffic capacity; spectrum efficiency; network energy efficiency; mobility; connection density; and latency. The IMT-2020 manifesto sets daunting performance enhancement goals for each of these criteria that range from the geometric (such as a 3x increase in spectrum efficiency) to the exponential (such as a 100x increase in network energy efficiency).
The 3rd Generation Partnership Project (3GPP) standard setting organization, having successfully driven the 4G LTE / LTE-Advanced standards into more than 450 networks in about 140 countries worldwide, is starting to establish study items, to be followed by work items, for their Release 15 (5G Phase 1) and Release 16 (5G Phase 2) specifications targeted for 2018 and 2019, respectively. Research organizations in the US, Europe and Asia are actively investigating digital wireless communications and networking technology alternatives and enhancements, such as RF channel modeling above 6 GHz, non-orthogonal waveforms, and network slicing.
One area of relative clarity is the technical consensus that carrier frequencies above 6 GHz are almost certainly required to achieve the IMT-2020 peak data rate target benchmark of 20 Gbps and the user-experience data rate target benchmark of 100 Mbps. This month, the World Radiocommunication Conference 2015 is being held in Geneva. US FCC delegates to this conference are proposing five frequency bands for 5G services: 27.5 to 29.5 GHz; 37 to 40.5 GHz; 47.2 to 50.2 GHz; 50.4 to 52.6 GHz; and 59.3 to 71 GHz. This is a total of 22.4 GHz of potential new spectrum, enabling channels bandwidths up to 2 GHz. Obviously, the FCC must work diligently with other major international regulatory organizations to encourage globally harmonized 5G spectrum, in preparation for the next WRC meeting in 2019.
A little math reminds us that 5 GHz corresponds to 6 cm wavelength, and 30 GHz corresponds to 1 cm wavelength. Frequencies above 30 GHz are considered millimeter waves, and mm waves have significantly different propagation characteristics (such as free space loss, diffraction and delay spread) than cm waves below 6 GHz. Both atmospheric water vapor (peaking at about 22 GHz) and oxygen (peaking at about 63 GHz) absorb significant RF energy. While 60 GHz channel modeling has been conducted in the context of 802.11ad WiGIG, the 5G standardization process requires a more comprehensive effort. Recognizing this shortcoming, in March of this year, Nokia Networks put forward a 3GPP Work Item Description (RP-150308) to organize and unify the mm wave channel modeling effort, explicitly acknowledging the opportunity to leverage the research work currently underway outside the 3GPP.
One of the intriguing aspects of mm wave cellular is the potential for user equipment (i.e., smartphone) high order MIMO two dimensional antenna arrays. Cellular MIMO has been impractical on LTE smartphones largely due to the small physical dimensions of handheld devices, despite antenna innovations from SkyCross and others. On the infrastructure side, LTE eNodeB base stations since 3GPP Release 12 have included 2×2, 4×4, 8×8 single-user MIMO radio options with digital beamforming, and Release 14 supports eNodeB “full dimensional” (i.e., elevation and azimuth “pencil” beamforming) supporting dozens of multi-user MIMO client devices. With mm wave cellular, there is the potential to include an 8×8 array antenna in less than 40 square mm of area, small enough for use in 4.7″ screen size smartphones.
The relatively short range of mm wave cellular has led to a consensus view that 5G’s ambitious 5G peak and average data rates will be practically achievable only using small cell base stations addressing indoor high bandwidth use cases, such as streaming UHD video. Complementary to this view is the conception of 5G as overlay to existing 4G LTE-A networks, with enhancements to LTE-A, such as LTE-M (machine-to-machine) and LTE-U (unlicensed band) likely to be positioned by carriers as 4.5G.
There is much to anticipate with respect to cellular transceiver research and development in the coming decade!
An Easier Way to Reach Design Closure for SoC
It’s really challenging to reach design closure of an SoC by meeting timing constraints, staying within the power budget, tracking progress, communicating within the team, minimizing the floorplan, maximizing manufacturability and eliminating hotspots. Most SoC design teams have EDA tools from multiple vendors, and yet no single vendor has figured out a simple way to accomplish all of these objectives in an automated tool flow. These multiple challenges can be addressed, and in fact one company in particular has an EDA tool that does work with multiple point tools to distill data and analytics into design information. That company is Dassault Systemes, and their EDA tool is called ENOVIA Pinpoint.
Paul McLellan first blogged about PinPoint back in 2013, but there’s been a lot of progress since then in terms of new features. The Pinpoint tool provides both engineers and managers a dashboard-based system for design closure, and it uses analytics to help the team members debug closure issues more quickly than manually looking at gigabytes of EDA tool log files.
What’s New in Pinpoint
You can now easily analyze all of your SoC timing paths across all modes of operation and all corners using the Timing Scenario feature.
Timing on SoCs is dominated by interconnect, so knowing the capacitance values of your interconnect is critical to reaching timing closure. In Pinpoint there’s a timing DRC report for max trans and max cap which appear on your IC layout as red and orange colored circles.
Pinpoint works with all of the major EDA tools for static timing analysis, place and route, and IC layout. It even supports the Synospys PTPx power report and lets you visualize layout overlays based on leakage, internal and dynamic info taken from the Primetime static timing analysis tool.
There’s a new timing scenario mode summary that lets an engineer consider timing paths that span all modes and corners. You can now look at your timing paths that violate timing on most of your analysis points at once, instead of having to review each mode and corner one at a time.
SoC design managers will like using Pinpoint because it makes the whole team more efficient, especially during a design review meeting by presenting all the data quickly without having to create manual reports. Managers can start with a summary of how their project is tracking against schedule and then proceed to lower levels of detailed by just clicking. They will know where each block is at in getting to closure and the full-chip. Historical metrics tell you how the project is trending, and if its converging or not.
Design engineers get to spend more time designing and less time reporting because they have an environment that lets them collaborate with their entire team, creating a way for all engineers from RTL to physical keep in touch, and allowing anyone to make a comparison of all experiments tried so far.
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How Can Big Data and EDA Tools Help?
2016 EDA Dead Pool
The most commonly asked question during conference calls with Wall Street of late is in regards to the massive consolidation the semiconductor industry is experiencing. How will the consolidation affect the Foundries? How will the consolidation affect EDA and IP? How will the consolidation affect the semiconductor industry in general? Good questions of course so let me share my opinions, observations, and experiences.
For me it is déjà vu 1980s all over again. Massive consolidation amongst the IDMs shocked the industry putting thousands of semiconductor professionals out of work. The result of course is the fabless semiconductor ecosystem we have today with hundreds of thousands of people driving the silicon based innovation that brought us all our clever mobile devices we have today. We really were like U.S. Marines back then: “Improvise, Adapt (and) Overcome!”
Yes, thousands of semiconductor people will leave their jobs this year and next but they will again do it for bigger and better things. You will not see us serving coffee at your local Starbucks. Some will go to systems companies like Apple or internet companies like Google, Amazon, or FaceBook. The automotive companies are stocking up on semiconductor people as well. Others will start new companies and continue to innovate even faster than before. It really will be like the Tortoise and the Hare fable except there will be a dozen tortoises against hundreds of hares and some of the hares will win.
Yes, the foundries will have 10% of their customers buying 90% of their wafers but that will allow much deeper collaboration which will be required moving down to 10nm and below. TSMC knows all too well how much money it takes to stay on the leading edge and the new fabless semiconductor giants will have no choice but to write some very big checks if they want to stay competitive. Apple is leading the way as they have already written some very big checks and the rest have no choice but to follow. The same thing goes for EDA and IP, there will be much closer collaboration with the foundries and the semiconductor giants amongst the chosen few suppliers.
The hardest hit in my opinion will be EDA. Not the overall EDA busines but the little EDA companies, ones that are not well positioned within the ecosystem and not accretive enough for acquisition. Back in the day, the venture community, the foundries, and the fabless companies were in full support of emerging EDA companies. As we all know this is no longer the case. If Big EDA (Synopsys, Cadence, Mentor) can do anything close to what Little EDA can do then you are a likely candidate for the 2016 EDA Dead Pool.
Place and Route is an easy example. In fact, I would be very concerned if I were a point tool in any part of the flow for 16nm and below. FinFETs are hard and unless you have a VERY close relationship with the foundries and top fabless companies you are as good as dead. You have to wonder if Synopsys saw this coming since they have been the most active with EDA consolidation. Take a look at the EDA Merger and Acquisition Wiki, it grew quite a bit this year. 28nm and above is a different story all together and we can talk about that another time. We should also talk about the ASIC business because I see huge upside there.
Bottom line: Synopsys, Cadence, and Mentor will thrive during the semiconductor industry consolidation cycle. Moving forward, much more intimate relationships amongst the big fabless companies, foundries, and EDA will be required and that means fewer companies will be able to participate. Purchases may be delayed during the acquisition process but overall Big EDA will be in a stronger position to get a bigger piece of the semiconductor pie, absolutely.
Create your 5 company 2016 EDA Dead Pool list in the comments section. Whoever picks the most acquired EDA companies in 2016 will win a new iPad Air 3!
My Life at Fairchild Semiconductor – 1979
This week it was announced that Fairchild Semiconductor was sold to On Semiconductor for $2.4B. The end of an era. As I look back at my career of 36 years with the only company that I have worked for since graduating college, I can’t help but feel a bit sad but extremely grateful for the wonderful experience that Fairchild has provided to me. It has been a wild ride but I wouldn’t trade it for any other career on the face of the Earth.
Please allow me to reminisce….
The day was Monday, June 4, 1979. I had just graduated from the University of Maine at Orono with a BSEE degree. I was 22 years old, a young, wide-eyed kid raised from a large family (5 brothers and one sister and two great parents) in Lewiston, Maine. It was my first day of work at Fairchild Camera and Instrument located at 333 Western Avenue in South Portland, the exact same location that I will be retiring from on March 4, 2016 at 8:05am. This factory is the oldest semiconductor fabrication site in existence, starting operations in 1962.
I was one of many new engineers to report for work that week. The business climate was strong and the semiconductor market was growing rapidly. My first stop was HR, where I was given basic orientation on the work requirements and company benefits. A guy by the name of Peter Wiberg was the HR Manager and my boss was Mike Pawlik who was the Engineering Supervisor in charge of the Diffusion Fabrication area. Mike was an excellent supervisor and engineering talent. Shortly into my new job, He spent a week with me working on second shift, providing personalized one-on-one training. It was probably the most significant week of my entire career. I learned a tremendous amount about fabrication processing, parametric testing (measuring transistor beta, BVcbo and LVceo, etc.) and people. At that time, approximately 2000 people worked at the factory of roughly 100,000 sq. ft and I was proud and excited to be among the workforce. Today, the workforce has been reduced to less than 300.
I was hired to be a sustaining Process Engineer in charge of the Diffusion area for the 3″ Class 100 Fab. My starting salary was $16,800/yr. At that time, the fab had a start level of approximately 13,000 wafers per week and we ran TTL, Low Power and Standard Schottky logic products that had minimum feature sizes in the range of 4um – 7um. Our new technology was FAST logic, which was semi-recessed locos oxide isolated that offered tremendous speed power performance benefits relative our junction isolated technologies.
The Diffusion area used Thermco furnaces which had all copper plumbing (not stainless steel) with leak-prone swagelok fittings. Gas flows in the diffusion tubes were regulated using manual flowmeters as mass flow controllers were not developed as yet. This was the era before ion implantation so all semiconductor dopants were sourced through diffusion predeposition processes. antimony trioxide (Sb2O3) and arsine gas (AsH3) was used for bipolar collectors, boron nitride (BN) and boron trichloride (BCL3) to form base junctions and phosphorus oxychloride (POCL3) used to form emitter regions. Diborane (B2H6) was used for junction isolation. Each of these predeposition processes were quite unique in how they introduced dopant to the silicon surface. Although these dopants were quite hazardous and potentially deadly to work with, we did not have all the safety interlocking systems that are commonplace today but we did educate the workforce on the material properties of the dopants and the need to follow strict procedures.
Silicon wafers were loaded onto long quartz ladders using stainless steel tweezers (imagine the contamination induced) and the loaded ladders were then slid onto a carrier (quartz lined stainless steel) that would enable the operators to carry the ladder from a loading station to the diffusion tube. The wafers were then slid into the the furnace manually using a long quartz push rod. Once loaded, the operator capped the tube using a quartz end cap that had a hole to direct exhaust gases to the vestibule exhaust of the furnace.
Equipment and processes were significantly more manual than the advanced equipment of today. Of course wafer and die yields were very low by today’s standards. The average bank of diffusion furnaces cost far less than $100K.
We did have cleanroom garments that consisted of lab coats and booties and hairnets.
The office area of that time was quite different than today. The floors were all tile and we had cubicles that housed 6 to 8 desks. It was common for people to smoke cigarettes at their desk and ashtrays were commonplace. We had no PCs as they hadn’t been invented yet. There were no cell phones, no beepers, no emails. When we wanted to contact someone, we called their name on the intercom and asked them to call our number. When we wanted to write a report, we wrote the report and gave it to the secretary to type up and distribute. When a correction had to be made, they used white-out and typed over the mistake. When the fab had to communicate to the assembly sites overseas, they used teletype (TWX) machines to send written information. Phone service was typically not used as it was prohibitively expensive.
I could go on but you get the idea. The industry has seen much change since 1979 and I feel extremely fortunate for the great opportunity and career that Fairchild has provided me.
…more to come.